coreboot-gerrit December 2019

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Change in em100[master]: curl: Handle errors in curl_easy_perform()
by Stefan Reinauer (Code Review) 06 Dec '19

06 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37479 ) Change subject: curl: Handle errors in curl_easy_perform() ...................................................................... curl: Handle errors in curl_easy_perform() Not much we can do, but at least warn the user that something went wrong. Change-Id: I96374d1b153113a302fa98c27873db863a22f77e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M curl.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/79/37479/1 diff --git a/curl.c b/curl.c index 6895c62..51c4a11 100644 --- a/curl.c +++ b/curl.c @@ -110,6 +110,9 @@ /* Fetch the file */ res = curl_easy_perform(curl); + if (res != CURLE_OK) + printf("Error while downloading %s: %s\n", filename, + curl_easy_strerror(res)); /* Close file */ fclose(file); -- To view, visit https://review.coreboot.org/c/em100/+/37479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I96374d1b153113a302fa98c27873db863a22f77e Gerrit-Change-Number: 37479 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Fix dependencies
by Stefan Reinauer (Code Review) 06 Dec '19

06 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37535 ) Change subject: Fix dependencies ...................................................................... Fix dependencies Jenkins won't let us do perl -pi -e, so let's not do in-place replacement. Change-Id: I74d93713cb97bd2b2c415234710fd2b34f6a1c02 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M Makefile 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/35/37535/1 diff --git a/Makefile b/Makefile index 93a2474..fd1be91 100644 --- a/Makefile +++ b/Makefile @@ -54,8 +54,9 @@ $(CC) $(CFLAGS) $(CPPFLAGS) -o $@ -c $< dep: $(SOURCES) - $(CC) $(CFLAGS) -MM $(SOURCES) > .dependencies - #perl -pi -e 's,^xz,xz/xz,g' .dependencies + $(CC) $(CFLAGS) -MM $(SOURCES) > .dependencies.tmp + sed 's,^xz,xz/xz,g' .dependencies.tmp > .dependencies + rm .dependencies.tmp tarballs: makedpfw makechips.sh printf " CREATE config & firmware images\n" -- To view, visit https://review.coreboot.org/c/em100/+/37535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I74d93713cb97bd2b2c415234710fd2b34f6a1c02 Gerrit-Change-Number: 37535 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: WIP: Add more commands to trace mode
by Stefan Reinauer (Code Review) 06 Dec '19

06 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/36804 ) Change subject: WIP: Add more commands to trace mode ...................................................................... WIP: Add more commands to trace mode This is untested, unfinished work. DO NOT COMMIT Change-Id: I9c478475fe7553ab7e116890461ebd3f72cd9872 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M trace.c 1 file changed, 17 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/04/36804/1 diff --git a/trace.c b/trace.c index 50c2fc6..2fc3d44 100644 --- a/trace.c +++ b/trace.c @@ -115,14 +115,23 @@ struct spi_cmd_values spi_command_list[] = { /* name cmd, addr, pad */ - {"write status register", 0x01, 0, 0}, - {"page program", 0x02, 1, 0}, - {"read", 0x03, 1, 0}, - {"write disable", 0x04, 0, 0}, - {"read status register", 0x05, 0, 0}, - {"write enable", 0x06, 0, 0}, - {"fast read", 0x0b, 1, 1}, - {"EM100 specific", 0x11, 0, 0}, + {"No Operation", 0x00, 0, 0}, + {"Write Status Register", 0x01, 0, 0}, + {"Page Program", 0x02, 1, 0}, + {"Normal Read", 0x03, 1, 0}, + {"Write Disable", 0x04, 0, 0}, + {"Read Status Register", 0x05, 0, 0}, + {"Write Enable", 0x06, 0, 0}, + {"Fast Read", 0x0b, 1, 1}, + {"4-Byte Fast Read", 0x0c, 1, 1}, + {"DTR/DDR Fast Read", 0x0d, 1, 1}, + {"4-Byte DTR/DDR Fast Read", 0x0e, 1, 1}, + {"Write Status Register 3", 0x11, 0, 0}, + {"4-Byte Page Program", 0x12, 1, 0}, + {"4-Byte Read", 0x13, 1, 0}, + {"Autoboot Register Read", 0x14, 0, 0}, + {"Autoboot Register Write", 0x15, 0, 0}, + {"fast dual read", 0x3b, 1, 2}, {"chip erase", 0x60, 0, 0}, {"read JEDEC ID", 0x9f, 0, 0}, -- To view, visit https://review.coreboot.org/c/em100/+/36804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I9c478475fe7553ab7e116890461ebd3f72cd9872 Gerrit-Change-Number: 36804 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: FSP 2.0: Add fsp_relax_security
by Patrick Georgi (Code Review) 06 Dec '19

06 Dec '19

Patrick Georgi has uploaded a new patch set (#15) to the change originally created by Julien Viard de Galbert. ( https://review.coreboot.org/c/coreboot/+/25437 ) Change subject: FSP 2.0: Add fsp_relax_security ...................................................................... FSP 2.0: Add fsp_relax_security The rationale is that for some hardware testing tools to work properly some register must not be locked, adding this hook allows the platform to define its way of disabling the locks. The implementation is to not call the final FSP notify stage that does the locking. Change-Id: I972e7387c2612ee0053df21afb55b0b264961174 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/notify.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/25437/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/25437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I972e7387c2612ee0053df21afb55b0b264961174 Gerrit-Change-Number: 25437 Gerrit-PatchSet: 15 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/lenovo/w520/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 06 Dec '19

06 Dec '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37294 ) Change subject: mb/lenovo/w520/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/w520/devicetree: Use subsystemid inheritance Change-Id: If7816992e717b4da585b16e5bbe67610c9af867d Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t520/variants/w520/devicetree.cb 1 file changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/37294/1 diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index 8716046..8b2cbe7 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -37,9 +37,13 @@ register "pci_mmio_size" = "2048" device domain 0 on + subsystemid 0x17aa 0x21cf inherit + device pci 00.0 on end # host bridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on end # vga controller + device pci 02.0 on + subsystemid 0x17aa 0x21d1 + end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -73,7 +77,9 @@ device pci 16.1 off end device pci 16.2 off end device pci 16.3 off end - device pci 19.0 on end # Intel Gigabit Ethernet + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x17aa 0x21ce + end device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 @@ -87,10 +93,10 @@ device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on #LPC bridge chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end -- To view, visit https://review.coreboot.org/c/coreboot/+/37294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7816992e717b4da585b16e5bbe67610c9af867d Gerrit-Change-Number: 37294 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t520/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 06 Dec '19

06 Dec '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37293 ) Change subject: mb/lenovo/t520/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/t520/devicetree: Use subsystemid inheritance Change-Id: Iffeb634c73f58aa1cddac5210d75fda75a3d5e92 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t520/variants/t520/devicetree.cb 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/37293/1 diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index 7893daf..0bfa18f 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -37,9 +37,13 @@ register "pci_mmio_size" = "2048" device domain 0 on + subsystemid 0x17aa 0x21cf inherit + device pci 00.0 on end # host bridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on end # vga controller + device pci 02.0 on + subsystemid 0x17aa 0x21d1 + end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -73,7 +77,9 @@ device pci 16.1 off end device pci 16.2 off end device pci 16.3 off end - device pci 19.0 on end # Intel Gigabit Ethernet + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x17aa 0x21ce + end device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 @@ -91,8 +97,7 @@ device pci 1f.0 on #LPC bridge chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end -- To view, visit https://review.coreboot.org/c/coreboot/+/37293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffeb634c73f58aa1cddac5210d75fda75a3d5e92 Gerrit-Change-Number: 37293 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Add Facebook Monolith to maintainers
by Wim Vervoorn (Code Review) 06 Dec '19

06 Dec '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37517 ) Change subject: src: Add Facebook Monolith to maintainers ...................................................................... src: Add Facebook Monolith to maintainers Add Facebook Monolith maintainers. BUG=N/A TEST=build Change-Id: I4e7f44710deada0331ac9b4e77d6144848faf6cb Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M MAINTAINERS 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37517/1 diff --git a/MAINTAINERS b/MAINTAINERS index d4b1935..6c565f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -334,6 +334,12 @@ S: Maintained F: src/mainboard/facebook/fbg1701/ +FACEBOOK MONOLITH MAINBOARD +M: Frans Hendriks <fhendriks(a)eltan.com> +M: Wim Vervoorn <wvervoorn(a)eltan.com> +S: Maintained +F: src/mainboard/facebook/monolith/ + PORTWELL PQ-M107 MAINBOARD M: Frans Hendriks <fhendriks(a)eltan.com> M: Wim Vervoorn <wvervoorn(a)eltan.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/37517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e7f44710deada0331ac9b4e77d6144848faf6cb Gerrit-Change-Number: 37517 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/monolith: Add Facebook Monolith
by Wim Vervoorn (Code Review) 06 Dec '19

06 Dec '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37516 ) Change subject: mb/facebook/monolith: Add Facebook Monolith ...................................................................... mb/facebook/monolith: Add Facebook Monolith The board is booting Linux and has been briefly tested. SeaBIOS, TianoCore payload and Linux as payload all seem to work fine. BUG=N/A TEST=tested on Facebook Monolith Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- A Documentation/mainboard/facebook/monolith.md M Documentation/mainboard/index.md A src/mainboard/facebook/monolith/Kconfig A src/mainboard/facebook/monolith/Kconfig.name A src/mainboard/facebook/monolith/Makefile.inc A src/mainboard/facebook/monolith/acpi/dptf.asl A src/mainboard/facebook/monolith/acpi/ec.asl A src/mainboard/facebook/monolith/acpi/mainboard.asl A src/mainboard/facebook/monolith/acpi/superio.asl A src/mainboard/facebook/monolith/acpi_tables.c A src/mainboard/facebook/monolith/board_info.txt A src/mainboard/facebook/monolith/cmos.layout A src/mainboard/facebook/monolith/com_init.c A src/mainboard/facebook/monolith/data.vbt A src/mainboard/facebook/monolith/devicetree.cb A src/mainboard/facebook/monolith/dsdt.asl A src/mainboard/facebook/monolith/gpio.h A src/mainboard/facebook/monolith/mainboard.c A src/mainboard/facebook/monolith/onboard.h A src/mainboard/facebook/monolith/ramstage.c A src/mainboard/facebook/monolith/romstage.c A src/mainboard/facebook/monolith/spd/Makefile.inc A src/mainboard/facebook/monolith/spd/spd.h A src/mainboard/facebook/monolith/spd/spd_util.c A src/mainboard/facebook/monolith/vboot-rw.fmd 25 files changed, 1,267 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/37516/1 diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md new file mode 100644 index 0000000..fdf50f1 --- /dev/null +++ b/Documentation/mainboard/facebook/monolith.md @@ -0,0 +1,71 @@ +# Facebook Monolith + +This page describes how to run coreboot on the Facebook Monolith. + +## Required blobs + +This board currently requires: +fsp blobs 3rdparty/fsp/KabylakeFspBinPkg/Fsp_M.fd + 3rdparty/fsp/KabylakeFspBinPkg/Fsp_S.fd + +Microcode 3rdparty/intel-microcode/intel-ucode + +## Flashing coreboot + +### Internal programming + +The SPI flash can be accessed using [flashrom]. + +### External programming + +The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip. +Specifically, it's a Winbond W25Q128JVSIQ (3.3V), whose datasheet can be found +[here][W25Q128JVSIQ]. + +The system has an external flash chip which is a 16 MiB soldered SOIC-8 chip. +Specifically, it's a Winbond W25Q128JVSIM (3.3V), whose datasheet can be found +[here][W25Q128JVSIM]. + +## Known issues + +- None + +## Untested + +- hardware monitor +- SDIO +- Full Embedded Controller support +- eMMC +- SATA + +## Working + +- USB +- Gigabit Ethernet +- graphics +- flashrom +- PCIe +- serial port +- SMBus +- initialization with FSP +- SeaBIOS payload +- TianoCore payload +- LinuxBoot + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| SoC | Intel KabyLake U | ++------------------+--------------------------------------------------+ +| CPU | Intel i3-7100U | ++------------------+--------------------------------------------------+ +| Super I/O, EC | ITE8256 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[W25Q128JVSIQ]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.p… +[W25Q128JVSIM]: https://www.winbond.com/resource-files/w25q128jv%20dtr%20revb%2011042016.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 60302cb..038689d 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -32,6 +32,7 @@ ## Facebook - [FBG-1701](facebook/fbg1701.md) +- [Monolith](facebook/monolith.md) ## Foxconn diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig new file mode 100644 index 0000000..2a54401 --- /dev/null +++ b/src/mainboard/facebook/monolith/Kconfig @@ -0,0 +1,94 @@ +if BOARD_FACEBOOK_MONOLITH + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select SOC_INTEL_KABYLAKE + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_IFD_GBE_REGION + select INTEL_GMA_HAVE_VBT + +config CBFS_SIZE + hex "CBFS_SIZE" + default 0x00900000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "facebook/monolith" + +config MAINBOARD_PART_NUMBER + string + default "Monolith" + +config MAINBOARD_FAMILY + string + default "Facebook Monolith" + +config MAX_CPUS + int + default 4 + +config DEVICETREE + string + default "devicetree.cb" + +config IFD_BIN_PATH + string + depends on HAVE_IFD_BIN + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" + +config ME_BIN_PATH + string + depends on HAVE_ME_BIN + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" + +config GBE_BIN_PATH + string + depends on HAVE_GBE_BIN + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin" + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xd00 + +config DIMM_SPD_SIZE + int + default 512 #DDR4 + +config UART_FOR_CONSOLE + int + default 0 + +config DIMM_MAX + int + default 2 + +config TPM_INIT + bool + default n + +config HAVE_SKYLAKE_CPU + bool + default n + +config HAVE_KABYLAKE_QUAD + bool + default n + +config RW_REGION_ONLY + string "Files in RW only" + +config VBOOT_ENABLE_CBFS_FALLBACK + bool + default y + depends on VBOOT + +endif diff --git a/src/mainboard/facebook/monolith/Kconfig.name b/src/mainboard/facebook/monolith/Kconfig.name new file mode 100644 index 0000000..865aa2f --- /dev/null +++ b/src/mainboard/facebook/monolith/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_FACEBOOK_MONOLITH + bool "Facebook Monolith" diff --git a/src/mainboard/facebook/monolith/Makefile.inc b/src/mainboard/facebook/monolith/Makefile.inc new file mode 100644 index 0000000..0cccd26 --- /dev/null +++ b/src/mainboard/facebook/monolith/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## Copyright (C) 2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +bootblock-y += com_init.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c diff --git a/src/mainboard/facebook/monolith/acpi/dptf.asl b/src/mainboard/facebook/monolith/acpi/dptf.asl new file mode 100644 index 0000000..c33bb06 --- /dev/null +++ b/src/mainboard/facebook/monolith/acpi/dptf.asl @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + + + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/facebook/monolith/acpi/ec.asl b/src/mainboard/facebook/monolith/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/facebook/monolith/acpi/ec.asl diff --git a/src/mainboard/facebook/monolith/acpi/mainboard.asl b/src/mainboard/facebook/monolith/acpi/mainboard.asl new file mode 100644 index 0000000..2a3ad59 --- /dev/null +++ b/src/mainboard/facebook/monolith/acpi/mainboard.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} + +/* + * Onboard CPLD + */ +Scope (\_SB.PCI0.LPCB) +{ + Device (CPLD) /* Onboard CPLD */ + { + Name(_HID, EISAID("PNP0C01")) + Name(_CRS, ResourceTemplate() + { + /* Reserve 0x280 to 0x2BF for the CPLD */ + FixedIO (0x0280, 0x40) + IRQNoFlags () {7} + }) + } +} diff --git a/src/mainboard/facebook/monolith/acpi/superio.asl b/src/mainboard/facebook/monolith/acpi/superio.asl new file mode 100644 index 0000000..0f5790d --- /dev/null +++ b/src/mainboard/facebook/monolith/acpi/superio.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ + +Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + FixedIO (0x03F8, 0x08) + FixedIO (0x6E, 0x02) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + FixedIO (0x03F8, 0x08) + FixedIO (0x6E, 0x02) + IRQNoFlags () {4} + } + EndDependentFn () + }) +} diff --git a/src/mainboard/facebook/monolith/acpi_tables.c b/src/mainboard/facebook/monolith/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/facebook/monolith/acpi_tables.c diff --git a/src/mainboard/facebook/monolith/board_info.txt b/src/mainboard/facebook/monolith/board_info.txt new file mode 100644 index 0000000..c58669c --- /dev/null +++ b/src/mainboard/facebook/monolith/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Facebook +Board name: Monolith System +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/facebook/monolith/cmos.layout b/src/mainboard/facebook/monolith/cmos.layout new file mode 100644 index 0000000..04b2e15 --- /dev/null +++ b/src/mainboard/facebook/monolith/cmos.layout @@ -0,0 +1,121 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2016 Intel Corporation. +## Copyright (C) 2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +# reboot_counter reserved for core, not used by platform. +388 4 h 0 reboot_counter +#390 2 r 0 unused + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +#400 1 e 2 unused +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#416 568 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/facebook/monolith/com_init.c b/src/mainboard/facebook/monolith/com_init.c new file mode 100644 index 0000000..f19aba3 --- /dev/null +++ b/src/mainboard/facebook/monolith/com_init.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include "onboard.h" + +#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */ + +void bootblock_mainboard_early_init(void) +{ + /* Enable the serial port inside the EC */ + pnp_set_logical_device(SERIAL_DEV); + pnp_set_enable(SERIAL_DEV, 1); +} diff --git a/src/mainboard/facebook/monolith/data.vbt b/src/mainboard/facebook/monolith/data.vbt new file mode 100644 index 0000000..d2c3e6c --- /dev/null +++ b/src/mainboard/facebook/monolith/data.vbt Binary files differ diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb new file mode 100644 index 0000000..ef659b1 --- /dev/null +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -0,0 +1,248 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # CPLD host command ranges are in 0x280-0x2BF + # EC PNP registers are at 0x6e and 0x6f + register "gen1_dec" = "0x003c0281" + register "gen3_dec" = "0x0004006d" + + # LPC serial IRQ + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "EnableAzalia" = "0" + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + #register "ScsSdCardEnabled" = "2" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Enabled" + register "SaImguEnable" = "0" + register "Cio2Enable" = "0" + register "PmTimerDisabled" = "1" + register "HeciEnabled" = "0" + register "EnableLan" = "1" + + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 0, \ + [2] = 0, \ + [3] = 0, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x1C, \ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x88, \ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C ,\ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C, \ + .voltage_limit = 0x5F0 \ + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable Root ports. + # PCIE Port 1 disabled + # PCIE Port 2 disabled + + # PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard + register "PcieRpEnable[2]" = "1" + # Disable CLKREQ# + register "PcieRpClkReqSupport[2]" = "0" + + # PCIE Port 4 disabled + # PCIE Port 5 x1 -> MODULE i219 + + # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "0" + + # PCIE Port 7 Disabled + # PCIE Port 8 Disabled + + # PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA + register "PcieRpEnable[8]" = "1" + # Disable CLKREQ# + register "PcieRpClkReqSupport[8]" = "0" + # Use Hot Plug subsystem + register "PcieRpHotPlug[8]" = "1" + + # USB 2.0 Enable all ports + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2 + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 2 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 1 + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # M2 Port + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # Audio board + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled + + # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 2 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 1 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled + + register "SsicPortEnable" = "0" + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # + device pci 08.0 on end # Gaussian Mixture Model + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 17.0 on end # SATA + device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN + device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 + device pci 1d.0 on end # PCI Express Port 9 x4 FPGA + device pci 1e.0 on end # UART #0 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1f.0 on # LPC Interface + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Bridge + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/facebook/monolith/dsdt.asl b/src/mainboard/facebook/monolith/dsdt.asl new file mode 100644 index 0000000..2f00110 --- /dev/null +++ b/src/mainboard/facebook/monolith/dsdt.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + // Chipset specific sleep states + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/facebook/monolith/gpio.h b/src/mainboard/facebook/monolith/gpio.h new file mode 100644 index 0000000..02b91e3 --- /dev/null +++ b/src/mainboard/facebook/monolith/gpio.h @@ -0,0 +1,207 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ +#define EC_SCI_GPI GPE0_DW2_16 +#define EC_SMI_GPI GPP_E15 + +#ifndef __ACPI__ +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PM_SLP_S0ix_N */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +///* PIRQA# */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* SLEEP */ PAD_CFG_NC(GPP_A11), /* available on the module not used here */ +/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* V0.85A_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), +/* V0.85A_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), +/* GP_VRALERTB */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), +/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), +/* CPU_GP2 */ PAD_CFG_NC(GPP_B4), +/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5), +/* CLK_REQ_SLOT1 */ PAD_CFG_NC(GPP_B6), +/* CLK_REQ_SLOT2 */ PAD_CFG_NC(GPP_B7), +/* CLK_REQ_SLOT3 */ PAD_CFG_NC(GPP_B8), +/* CLK_REQ_SLOT4 */ PAD_CFG_NC(GPP_B9), +/* CLK_REQ_SLOT5 */ PAD_CFG_NC(GPP_B10), +/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* PCH_SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GSPI0_CS# */ /* GPP_B15 */ +/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), +/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), +/* GSPI1_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), +///* CB_OVT# */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), +/* SML1ALERT# */ PAD_CFG_GPI_APIC(GPP_B23, 20K_PD, PLTRST), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), +/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +///* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST), +/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* SML1_DATA */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* UART1_RXD */ PAD_CFG_NC(GPP_C12), +/* UART1_TXD */ PAD_CFG_NC(GPP_C13), +/* UART1_RTS */ PAD_CFG_NC(GPP_C14), +/* UART1_CTS */ PAD_CFG_NC(GPP_C15), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), +/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* UART2_RXD */ PAD_CFG_NC(GPP_C20), +/* UART2_TXD */ PAD_CFG_NC(GPP_C21), +///* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), +///* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SCI# not used */ PAD_CFG_NC(GPP_C22), +/* EC_SMI# not used */ PAD_CFG_NC(GPP_C23), +/* SPI1_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), +/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), +/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), +/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), +/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* GPP_D9 */ PAD_CFG_NC(GPP_D9), +/* GPP_D10 */ PAD_CFG_NC(GPP_D10), +/* GPP_D11 */ PAD_CFG_NC(GPP_D11), +/* GPP_D12 */ PAD_CFG_NC(GPP_D12), +/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), +/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), +/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK_1 */ PAD_CFG_NC(GPP_D17), +/* DMIC_DATA_1 */ PAD_CFG_NC(GPP_D18), +/* DMIC_CLK_0 */ PAD_CFG_NC(GPP_D19), +/* DMIC_DATA_0 */ PAD_CFG_NC(GPP_D20), +/* SPI1_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +/* SPI1_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), +/* I2S_MCLK */ PAD_CFG_NC(GPP_D23), +///* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), +/* GPP_E0 */ PAD_CFG_NC(GPP_E0), +/* GPP_E1 */ PAD_CFG_NC(GPP_E1), +/* GPP_E2 */ PAD_CFG_NC(GPP_E2), +/* GPP_E3 */ PAD_CFG_NC(GPP_E3), +/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), +/* GPP_E7 */ PAD_CFG_NC(GPP_E7), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* DDI3_HPD */ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), +/* DDI4_HPD */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), +/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_E23, 20K_PD, DEEP, NF1), +/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), +/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), +/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), +/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), +/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), +/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), +/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), +/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), +/* I2C4_SDA */ PAD_CFG_NC(GPP_F9), +/* ISH_I2C2_SDA */ PAD_CFG_NC(GPP_F10), +/* ISH_I2C2_SCL */ PAD_CFG_NC(GPP_F11), +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* GPP_F23 */ PAD_CFG_NC(GPP_F23), +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), +/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* GPD7 */ PAD_CFG_NC(GPD7), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), +}; + +#endif +#endif diff --git a/src/mainboard/facebook/monolith/mainboard.c b/src/mainboard/facebook/monolith/mainboard.c new file mode 100644 index 0000000..3d6532e --- /dev/null +++ b/src/mainboard/facebook/monolith/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +/* + * Declare the resources we are using + */ +static void mainboard_reserve_resources(struct device *dev) +{ + unsigned int idx = 0; + struct resource *res; + + /* + * CPLD: Reserve the IRQ here all others are within the default LPC + * range 0 to 1000h + */ + res = new_resource(dev, idx++); + res->base = 0x7; + res->size = 0x1; + res->flags = IORESOURCE_IRQ | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses(). + */ +static void mainboard_enable(struct device *dev) +{ + mainboard_reserve_resources(dev); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/facebook/monolith/onboard.h b/src/mainboard/facebook/monolith/onboard.h new file mode 100644 index 0000000..68b5fea --- /dev/null +++ b/src/mainboard/facebook/monolith/onboard.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#define ITE8528_CMD_PORT 0x6E +#define ITE8528_DATA_PORT 0x6F + +#endif diff --git a/src/mainboard/facebook/monolith/ramstage.c b/src/mainboard/facebook/monolith/ramstage.c new file mode 100644 index 0000000..bed1049 --- /dev/null +++ b/src/mainboard/facebook/monolith/ramstage.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016-2018 Intel Corporation + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + params->CdClock = 3; +} diff --git a/src/mainboard/facebook/monolith/romstage.c b/src/mainboard/facebook/monolith/romstage.c new file mode 100644 index 0000000..7c54708 --- /dev/null +++ b/src/mainboard/facebook/monolith/romstage.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016-2018 Intel Corporation. + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include "spd/spd.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + struct spd_block blk = { + .addr_map = { 0x50, 0x52, }, + }; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; + mupd->FspmTestConfig.DmiVc1 = 1; +} diff --git a/src/mainboard/facebook/monolith/spd/Makefile.inc b/src/mainboard/facebook/monolith/spd/Makefile.inc new file mode 100644 index 0000000..b4b42f7 --- /dev/null +++ b/src/mainboard/facebook/monolith/spd/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## Copyright (C) 2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c diff --git a/src/mainboard/facebook/monolith/spd/spd.h b/src/mainboard/facebook/monolith/spd/spd.h new file mode 100644 index 0000000..f2b6f2a --- /dev/null +++ b/src/mainboard/facebook/monolith/spd/spd.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/facebook/monolith/spd/spd_util.c b/src/mainboard/facebook/monolith/spd/spd_util.c new file mode 100644 index 0000000..5ccc810 --- /dev/null +++ b/src/mainboard/facebook/monolith/spd/spd_util.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> + +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/mainboard/facebook/monolith/vboot-rw.fmd b/src/mainboard/facebook/monolith/vboot-rw.fmd new file mode 100644 index 0000000..f1cb5e9 --- /dev/null +++ b/src/mainboard/facebook/monolith/vboot-rw.fmd @@ -0,0 +1,28 @@ + FLASH 16M { + SI_ALL@0x0 0x700000 { + SI_DESC@0x0 0x1000 + UNUSED_1@0x1000 0x2000 + SI_ME@0x3000 0x6fd000 + } + SI_BIOS@0x700000 0x900000 { + MISC_RW@0x0 0x20000 { + RW_MRC_CACHE@0x0 0x10000 + RW_VPD(PRESERVE)@0x010000 0x2000 + RW_NVRAM(PRESERVE)@0x012000 0x6000 + } + RW_SECTION_A@0x20000 0x860000 { + VBLOCK_A@0x0 0x10000 + RW_FWID_A@0x10000 0x40 + FW_MAIN_A(CBFS)@0x10040 0x84FFC0 + } + WP_RO@0x880000 0x080000 { + RO_SECTION@0x0000 0x80000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0x07B000 + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913 Gerrit-Change-Number: 37516 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

8 21

Change in coreboot[master]: [WIP] monotonic_timer: Make them SMP safe
by Kyösti Mälkki (Code Review) 06 Dec '19

06 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37398 ) Change subject: [WIP] monotonic_timer: Make them SMP safe ...................................................................... [WIP] monotonic_timer: Make them SMP safe Fixes regression with commit 45ddb4344 console,boot_state: Exclude printk() from reported times This was witnessed to cause boot regressions together with LAPIC_MONOTONIC_TIMER=y. The code in cpu/x86/lapic/apic_timer.c for timer_monotonic_get() is not SMP safe as LAPIC timers do not run as synchronised as TSCs. TBD: Time spent in printk() for APs is now incorrect in logs. Change-Id: I1ea2c1e7172f8ab3692b42dee3f669c5942d864a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/console/printk.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/37398/1 diff --git a/src/console/printk.c b/src/console/printk.c index a08dd2f..a01ae93 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -32,13 +32,13 @@ static void console_time_run(void) { - if (TRACK_CONSOLE_TIME) + if (TRACK_CONSOLE_TIME && boot_cpu()) timer_monotonic_get(&mt_start); } static void console_time_stop(void) { - if (TRACK_CONSOLE_TIME) { + if (TRACK_CONSOLE_TIME && boot_cpu()) { timer_monotonic_get(&mt_stop); console_usecs += mono_time_diff_microseconds(&mt_start, &mt_stop); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ea2c1e7172f8ab3692b42dee3f669c5942d864a Gerrit-Change-Number: 37398 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: riscv: Implement ipi using clint for emulation to enable smp in qemu.
by Philipp Hug (Code Review) 06 Dec '19

06 Dec '19

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35246 ) Change subject: riscv: Implement ipi using clint for emulation to enable smp in qemu. ...................................................................... riscv: Implement ipi using clint for emulation to enable smp in qemu. testing=Set MAX_CPUS=2 and run qemu with -smp 2 Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae --- M src/mainboard/emulation/qemu-riscv/Makefile.inc M src/mainboard/emulation/qemu-riscv/clint.c M src/mainboard/emulation/spike-riscv/Makefile.inc M src/mainboard/emulation/spike-riscv/clint.c M src/soc/ucb/riscv/Makefile.inc D src/soc/ucb/riscv/ipi.c 6 files changed, 14 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35246/1 diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index eb99544..2ca75fd 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -19,6 +19,7 @@ romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c +romstage-y += clint.c ramstage-y += uart.c ramstage-y += rom_media.c diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c index 367d48d..4a00bc2 100644 --- a/src/mainboard/emulation/qemu-riscv/clint.c +++ b/src/mainboard/emulation/qemu-riscv/clint.c @@ -14,6 +14,7 @@ */ #include <mcall.h> +#include <device/mmio.h> #include <mainboard/addressmap.h> /* This function is used to initialize HLS()->time/HLS()->timecmp */ @@ -23,3 +24,8 @@ HLS()->time = (uint64_t *)(QEMU_VIRT_CLINT + 0xbff8); HLS()->timecmp = (uint64_t *)(QEMU_VIRT_CLINT + 0x4000 + 8 * hart_id); } + +void set_msip(int hartid, int val) +{ + write32((void *)(QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index 38977b6..bfeaf58 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -18,6 +18,7 @@ romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c +romstage-y += clint.c ramstage-y += uart.c ramstage-y += rom_media.c ramstage-y += clint.c diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c index 7ad3f5a..c39e058 100644 --- a/src/mainboard/emulation/spike-riscv/clint.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -14,6 +14,7 @@ */ #include <mcall.h> +#include <device/mmio.h> #define SPIKE_CLINT_BASE 0x02000000 @@ -24,3 +25,8 @@ HLS()->time = (uint64_t *)(SPIKE_CLINT_BASE + 0xbff8); HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id); } + +void set_msip(int hartid, int val) +{ + write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index ef03642..80899d57 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -1,11 +1,7 @@ ifeq ($(CONFIG_SOC_UCB_RISCV),y) -bootblock-y += ipi.c - romstage-y += cbmem.c -romstage-y += ipi.c ramstage-y += cbmem.c -ramstage-y += ipi.c endif diff --git a/src/soc/ucb/riscv/ipi.c b/src/soc/ucb/riscv/ipi.c deleted file mode 100644 index 80307a8..0000000 --- a/src/soc/ucb/riscv/ipi.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mcall.h> - -/* TODO: Please implement this function */ -void set_msip(int hartid, int val) -{ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/35246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae Gerrit-Change-Number: 35246 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

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