coreboot-gerrit December 2019

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Change in coreboot[master]: nb/i945: Fix typo
by HAOUAS Elyes (Code Review) 06 Dec '19

06 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37518 ) Change subject: nb/i945: Fix typo ...................................................................... nb/i945: Fix typo Change-Id: I082ac2c1c13cbe6835a02d703f8651e837a43f37 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/memmap.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/37518/1 diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 000ac7e..5414120 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -55,7 +55,7 @@ else tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24; - /* subsctract TSEG size */ + /* subtract TSEG size */ tom -= decode_tseg_size(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC)); return tom; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I082ac2c1c13cbe6835a02d703f8651e837a43f37 Gerrit-Change-Number: 37518 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: endian: Replace explicit byte swapping with compiler builtin
by Julius Werner (Code Review) 06 Dec '19

06 Dec '19

Hello Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37343 to review the following change. Change subject: endian: Replace explicit byte swapping with compiler builtin ...................................................................... endian: Replace explicit byte swapping with compiler builtin gcc seems to have some stupid problem with deciding when to inline byte swapping functions (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92716). Using the compiler builtin instead seems to solve the problem. (This doesn't yet solve the issue for the read_be32()-family of functions, which we should maybe just get rid of at some point?) Change-Id: Ia2a6d8ea98987266ccc32ffaa0a7f78965fca1cd Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/include/endian.h D payloads/libpayload/include/swab.h M src/include/endian.h D src/include/swab.h M src/vendorcode/eltan/security/mboot/mboot.c M src/vendorcode/eltan/security/mboot/mboot.h 6 files changed, 20 insertions(+), 130 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/37343/1 diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index b387e66..7f8b93a 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -34,23 +34,6 @@ #include <arch/types.h> #include <libpayload-config.h> -static inline uint16_t swap_bytes16(uint16_t in) -{ - return ((in & 0xFF) << 8) | ((in & 0xFF00) >> 8); -} - -static inline uint32_t swap_bytes32(uint32_t in) -{ - return ((in & 0xFF) << 24) | ((in & 0xFF00) << 8) | - ((in & 0xFF0000) >> 8) | ((in & 0xFF000000) >> 24); -} - -static inline uint64_t swap_bytes64(uint64_t in) -{ - return ((uint64_t)swap_bytes32((uint32_t)in) << 32) | - ((uint64_t)swap_bytes32((uint32_t)(in >> 32))); -} - /* Endian functions from glibc 2.9 / BSD "endian.h" */ #if CONFIG(LP_BIG_ENDIAN) @@ -59,15 +42,15 @@ #define htobe32(in) (in) #define htobe64(in) (in) -#define htole16(in) swap_bytes16(in) -#define htole32(in) swap_bytes32(in) -#define htole64(in) swap_bytes64(in) +#define htole16(in) __builtin_bswap16(in) +#define htole32(in) __builtin_bswap32(in) +#define htole64(in) __builtin_bswap64(in) #elif CONFIG(LP_LITTLE_ENDIAN) -#define htobe16(in) swap_bytes16(in) -#define htobe32(in) swap_bytes32(in) -#define htobe64(in) swap_bytes64(in) +#define htobe16(in) __builtin_bswap16(in) +#define htobe32(in) __builtin_bswap32(in) +#define htobe64(in) __builtin_bswap64(in) #define htole16(in) (in) #define htole32(in) (in) diff --git a/payloads/libpayload/include/swab.h b/payloads/libpayload/include/swab.h deleted file mode 100644 index 2198077..0000000 --- a/payloads/libpayload/include/swab.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef _SWAB_H -#define _SWAB_H - -/* - * linux/byteorder/swab.h - * Byte-swapping, independently from CPU endianness - * swabXX[ps]?(foo) - * - * Francois-Rene Rideau <fare(a)tunes.org> 19971205 - * separated swab functions from cpu_to_XX, - * to clean up support for bizarre-endian architectures. - * - * See asm-i386/byteorder.h and suches for examples of how to provide - * architecture-dependent optimized versions - * - */ - -/* casts are necessary for constants, because we never know for sure - * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. - */ -#define swab16(x) \ - ((unsigned short)( \ - (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \ - (((unsigned short)(x) & (unsigned short)0xff00U) >> 8))) - -#define swab32(x) \ - ((unsigned int)( \ - (((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \ - (((unsigned int)(x) & (unsigned int)0x0000ff00UL) << 8) | \ - (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \ - (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24))) - -#define swab64(x) \ - ((uint64_t)( \ - (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ - (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ - (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ - (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ - (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ - (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ - (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ - (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) - -#endif /* _SWAB_H */ diff --git a/src/include/endian.h b/src/include/endian.h index 8dc1854..d4b1707 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -17,7 +17,6 @@ #include <arch/byteorder.h> #include <stdint.h> -#include <swab.h> #if defined(__LITTLE_ENDIAN) #define cpu_to_le64(x) ((uint64_t)(x)) @@ -26,19 +25,19 @@ #define le32_to_cpu(x) ((uint32_t)(x)) #define cpu_to_le16(x) ((uint16_t)(x)) #define le16_to_cpu(x) ((uint16_t)(x)) - #define cpu_to_be64(x) swab64(x) - #define be64_to_cpu(x) swab64(x) - #define cpu_to_be32(x) swab32(x) - #define be32_to_cpu(x) swab32(x) - #define cpu_to_be16(x) swab16(x) - #define be16_to_cpu(x) swab16(x) + #define cpu_to_be64(x) __builtin_bswap64(x) + #define be64_to_cpu(x) __builtin_bswap64(x) + #define cpu_to_be32(x) __builtin_bswap32(x) + #define be32_to_cpu(x) __builtin_bswap32(x) + #define cpu_to_be16(x) __builtin_bswap16(x) + #define be16_to_cpu(x) __builtin_bswap16(x) #elif defined(__BIG_ENDIAN) - #define cpu_to_le64(x) swab64(x) - #define le64_to_cpu(x) swab64(x) - #define cpu_to_le32(x) swab32(x) - #define le32_to_cpu(x) swab32(x) - #define cpu_to_le16(x) swab16(x) - #define le16_to_cpu(x) swab16(x) + #define cpu_to_le64(x) __builtin_bswap64(x) + #define le64_to_cpu(x) __builtin_bswap64(x) + #define cpu_to_le32(x) __builtin_bswap32(x) + #define le32_to_cpu(x) __builtin_bswap32(x) + #define cpu_to_le16(x) __builtin_bswap16(x) + #define le16_to_cpu(x) __builtin_bswap16(x) #define cpu_to_be64(x) ((uint64_t)(x)) #define be64_to_cpu(x) ((uint64_t)(x)) #define cpu_to_be32(x) ((uint32_t)(x)) diff --git a/src/include/swab.h b/src/include/swab.h deleted file mode 100644 index 956cfa5..0000000 --- a/src/include/swab.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * linux/byteorder/swab.h - * Byte-swapping, independently from CPU endianness - * swabXX[ps]?(foo) - * - * Francois-Rene Rideau <fare(a)tunes.org> 19971205 - * separated swab functions from cpu_to_XX, - * to clean up support for bizarre-endian architectures. - * - * See asm-i386/byteorder.h and such for examples of how to provide - * architecture-dependent optimized versions - * - */ - -/* casts are necessary for constants, because we never know how for sure - * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. - */ - -#ifndef _SWAB_H -#define _SWAB_H - -#include <stdint.h> - -#define swab16(x) \ - ((unsigned short)( \ - (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \ - (((unsigned short)(x) & (unsigned short)0xff00U) >> 8))) - -#define swab32(x) \ - ((unsigned int)( \ - (((unsigned int)(x) & 0x000000ffUL) << 24) | \ - (((unsigned int)(x) & 0x0000ff00UL) << 8) | \ - (((unsigned int)(x) & 0x00ff0000UL) >> 8) | \ - (((unsigned int)(x) & 0xff000000UL) >> 24))) - -#define swab64(x) \ - ((uint64_t)( \ - (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ - (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ - (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ - (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ - (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ - (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ - (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ - (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) - -#endif /* _SWAB_H */ diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index c5523a5..f47d74b 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -100,8 +100,8 @@ Pcrs->count = TpmCap.data.assignedPCR.count; printk(BIOS_DEBUG, "Pcrs->count = %d\n", Pcrs->count); for (index = 0; index < Pcrs->count; index++) { - Pcrs->pcrSelections[index].hash = - swab16(TpmCap.data.assignedPCR.pcrSelections[index].hash); + Pcrs->pcrSelections[index].hash = __builtin_bswap16( + TpmCap.data.assignedPCR.pcrSelections[index].hash); printk(BIOS_DEBUG, "Pcrs->pcrSelections[%d].hash = 0x%x\n", index, Pcrs->pcrSelections[index].hash); Pcrs->pcrSelections[index].sizeofSelect = diff --git a/src/vendorcode/eltan/security/mboot/mboot.h b/src/vendorcode/eltan/security/mboot/mboot.h index 79f2308..3b08924 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.h +++ b/src/vendorcode/eltan/security/mboot/mboot.h @@ -27,7 +27,6 @@ #include <boot/coreboot_tables.h> #include <security/tpm/tss/tcg-2.0/tss_structures.h> #include <security/tpm/tss.h> -#include <swab.h> /* TPM2 interface */ #define EFI_TPM2_ACPI_TABLE_START_METHOD_TIS 6 -- To view, visit https://review.coreboot.org/c/coreboot/+/37343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2a6d8ea98987266ccc32ffaa0a7f78965fca1cd Gerrit-Change-Number: 37343 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/smsc/lpc47n207: Remove unused <stdint.h>
by HAOUAS Elyes (Code Review) 06 Dec '19

06 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37509 ) Change subject: superio/smsc/lpc47n207: Remove unused <stdint.h> ...................................................................... superio/smsc/lpc47n207: Remove unused <stdint.h> Change-Id: I9e6b2548ff7eb7224b15ffa2541922790816c947 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/smsc/lpc47n207/lpc47n207.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/37509/1 diff --git a/src/superio/smsc/lpc47n207/lpc47n207.h b/src/superio/smsc/lpc47n207/lpc47n207.h index e13d10a..f8e06c8 100644 --- a/src/superio/smsc/lpc47n207/lpc47n207.h +++ b/src/superio/smsc/lpc47n207/lpc47n207.h @@ -16,8 +16,6 @@ #ifndef SUPERIO_SMSC_LPC47N207_H #define SUPERIO_SMSC_LPC47N207_H -#include <stdint.h> - void try_enabling_LPC47N207_uart(void); #endif /* SUPERIO_SMSC_LPC47N207_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6b2548ff7eb7224b15ffa2541922790816c947 Gerrit-Change-Number: 37509 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/nsc/pc87417: Remove unused <stdint.h>
by HAOUAS Elyes (Code Review) 06 Dec '19

06 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37507 ) Change subject: superio/nsc/pc87417: Remove unused <stdint.h> ...................................................................... superio/nsc/pc87417: Remove unused <stdint.h> Change-Id: Icacf2806702a868a807080e1e2d14b1ee4ed4f90 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/nsc/pc87417/pc87417.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/37507/1 diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index 25401e4..c3fc5ef 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -111,7 +111,6 @@ #define PC87417_XWBCNF 0x16 #include <device/pnp_type.h> -#include <stdint.h> void pc87417_disable_dev(pnp_devfn_t dev); void pc87417_enable_dev(pnp_devfn_t dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/37507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icacf2806702a868a807080e1e2d14b1ee4ed4f90 Gerrit-Change-Number: 37507 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/superio/via: Remove unused superio chips
by HAOUAS Elyes (Code Review) 06 Dec '19

06 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37511 ) Change subject: src/superio/via: Remove unused superio chips ...................................................................... src/superio/via: Remove unused superio chips Change-Id: I248608361fcdc51ff435222d37c5bbc736b1947e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/superio/via/Makefile.inc 1 file changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37511/1 diff --git a/src/superio/via/Makefile.inc b/src/superio/via/Makefile.inc deleted file mode 100644 index 890ed00..0000000 --- a/src/superio/via/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += vt1211 -- To view, visit https://review.coreboot.org/c/coreboot/+/37511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I248608361fcdc51ff435222d37c5bbc736b1947e Gerrit-Change-Number: 37511 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/fintek: Fix typo
by HAOUAS Elyes (Code Review) 06 Dec '19

06 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37503 ) Change subject: superio/fintek: Fix typo ...................................................................... superio/fintek: Fix typo Change-Id: If5c0921e20b26ce558f542f405cf62ae8d4a8101 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/fintek/common/fan_control.h M src/superio/fintek/f81803a/fan_control.c 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/37503/1 diff --git a/src/superio/fintek/common/fan_control.h b/src/superio/fintek/common/fan_control.h index c316778..80f17dd 100644 --- a/src/superio/fintek/common/fan_control.h +++ b/src/superio/fintek/common/fan_control.h @@ -115,7 +115,7 @@ #define HWM_STATUS_INVALID_SECTION_VALUE -9 #define HWM_STATUS_BOUNDARY_WRONG_ORDER -10 #define HWM_STATUS_SECTIONS_WRONG_ORDER -11 -#define HWM_STATUS_WARNING_SENSOR_DISCONECTED 1 +#define HWM_STATUS_WARNING_SENSOR_DISCONNECTED 1 #define HWM_STATUS_WARNING_FAN_NOT_PWM 2 #define CPU_DAMAGE_TEMP 110 diff --git a/src/superio/fintek/f81803a/fan_control.c b/src/superio/fintek/f81803a/fan_control.c index 41fd0d3..a08180a 100644 --- a/src/superio/fintek/f81803a/fan_control.c +++ b/src/superio/fintek/f81803a/fan_control.c @@ -159,16 +159,16 @@ switch (sensor) { case EXTERNAL_SENSOR1: if (sensor_status & TP_EXTERNAL_SENSOR1_OPEN) { - printk(BIOS_WARNING, "Sensor 1 disconected!\n"); - return HWM_STATUS_WARNING_SENSOR_DISCONECTED; + printk(BIOS_WARNING, "Sensor 1 disconnected!\n"); + return HWM_STATUS_WARNING_SENSOR_DISCONNECTED; } hwm_reg_modify(base_address, TP_SENSOR_TYPE, TP_SENSOR1_TYPE_SHIFT, TP_SENSOR_TYPE_MASK, type); break; case EXTERNAL_SENSOR2: if (sensor_status & TP_EXTERNAL_SENSOR2_OPEN) { - printk(BIOS_WARNING, "Sensor 2 disconected!\n"); - return HWM_STATUS_WARNING_SENSOR_DISCONECTED; + printk(BIOS_WARNING, "Sensor 2 disconnected!\n"); + return HWM_STATUS_WARNING_SENSOR_DISCONNECTED; } hwm_reg_modify(base_address, TP_SENSOR_TYPE, TP_SENSOR2_TYPE_SHIFT, TP_SENSOR_TYPE_MASK, type); -- To view, visit https://review.coreboot.org/c/coreboot/+/37503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5c0921e20b26ce558f542f405cf62ae8d4a8101 Gerrit-Change-Number: 37503 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: usb: Deep search for endpoint descriptors
by Paul Menzel (Code Review) 06 Dec '19

06 Dec '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/3467 ) Change subject: libpayload: usb: Deep search for endpoint descriptors ...................................................................... Patch Set 5: (4 comments) https://review.coreboot.org/c/coreboot/+/3467/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/3467/1//COMMIT_MSG@9 PS1, Line 9: This improving searching for endpoint descriptors This improv*es* … https://review.coreboot.org/c/coreboot/+/3467/1//COMMIT_MSG@10 PS1, Line 10: and skipping non-endpoint interface descriptors. skipping → skips? Do these have ID 4? https://review.coreboot.org/c/coreboot/+/3467/1/payloads/libpayload/drivers… File payloads/libpayload/drivers/usb/usb.c: https://review.coreboot.org/c/coreboot/+/3467/1/payloads/libpayload/drivers… PS1, Line 395: while ((endp->bDescriptorType != 0x05) && (endp->bDescriptorType != 0x04) && (endp->bLength !=0)) { Add spaces around the `!=`. https://review.coreboot.org/c/coreboot/+/3467/1/payloads/libpayload/drivers… PS1, Line 396: endp = (endpoint_descriptor_t *)((char *)endp + endp->bLength); Trailing whitespace. Did you run `make gitconfig`? -- To view, visit https://review.coreboot.org/c/coreboot/+/3467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I063c096ab886f9753a9ee59f570fd81ce6f618cb Gerrit-Change-Number: 3467 Gerrit-PatchSet: 5 Gerrit-Owner: Anton Kochkov <anton.kochkov(a)gmail.com> Gerrit-Reviewer: Anton Kochkov <anton.kochkov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Dec 2019 13:15:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: rc/soc/intel/fsp_broadwell_de/acpi: Support Linux GPIO driver for Mon...
by Morgan Jang (Code Review) 06 Dec '19

06 Dec '19

Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37545 ) Change subject: rc/soc/intel/fsp_broadwell_de/acpi: Support Linux GPIO driver for Monolake platform ...................................................................... rc/soc/intel/fsp_broadwell_de/acpi: Support Linux GPIO driver for Monolake platform TEST=Test with the Linux Kernel that enables GPIO sysfs interface, Intel ICH GPIO and Intel Lynxpoint GPIO support in kernel config. Change-Id: I6387faed4dc97c9efc130aa3ade4754118edc8b8 Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> --- M src/soc/intel/fsp_broadwell_de/acpi.c A src/soc/intel/fsp_broadwell_de/acpi/gpio.asl M src/soc/intel/fsp_broadwell_de/acpi/lpc.asl 3 files changed, 162 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37545/1 diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index 5349c30..0ba9159 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -117,7 +117,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, 255); + MCFG_BASE_ADDRESS, 0, 0, 255); return current; } @@ -532,7 +532,7 @@ irqovr = (void *)current; current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, - sci_flags); + sci_flags); return current; } diff --git a/src/soc/intel/fsp_broadwell_de/acpi/gpio.asl b/src/soc/intel/fsp_broadwell_de/acpi/gpio.asl new file mode 100644 index 0000000..d1132d4 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/acpi/gpio.asl @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (GPIO) +{ + // GPIO Controller + Method (_HID) + { + // LynxPoint-LP + Return ("INT33C7") + } + Name (_UID, 1) + + Name (RBUF, ResourceTemplate() + { + DWordIo (ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + EntireRange, // ISARanges + 0x00000000, // AddressGranularity + 0x00000000, // AddressMinimum + 0x00000000, // AddressMaximum + 0x00000000, // AddressTranslation + 0x00000000, // RangeLength + , // ResourceSourceIndex + , // ResourceSource + BAR0) + // Disabled due to IRQ storm: http://crosbug.com/p/29548 + //Interrupt (ResourceConsumer, + // Level, ActiveHigh, Shared, , , ) {14} + }) + + Method (_CRS, 0, NotSerialized) + { + CreateDwordField (^RBUF, ^BAR0._MIN, BMIN) + CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) + CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) + + Store (GPIO_BASE_SIZE, BLEN) + Store (GPIO_BASE_ADDRESS, BMIN) + Store (Subtract (Add (GPIO_BASE_ADDRESS, + GPIO_BASE_SIZE), 1), BMAX) + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } + + // GWAK: Setup GPIO as ACPI GPE for Wake + // Arg0: GPIO Number + Method (GWAK, 1, Serialized) + { + // Local0 = GPIO Base Address + Store (And (GPBS, Not(0x1)), Local0) + + // Local1 = BANK, Local2 = OFFSET + Divide (Arg0, 32, Local2, Local1) + + // + // Set OWNER to ACPI + // + + // Local3 = GPIOBASE + GPIO_OWN(BANK) + Store (Add (Local0, Multiply (Local1, 0x4)), Local3) + + // GPIO_OWN(BANK) + OperationRegion (IOWN, SystemIO, Local3, 4) + Field (IOWN, AnyAcc, NoLock, Preserve) { + GOWN, 32, + } + + // GPIO_OWN[GPIO] = 0 (ACPI) + Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN) + + // + // Set ROUTE to SCI + // + + // Local3 = GPIOBASE + GPIO_ROUTE(BANK) + Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3) + + // GPIO_ROUTE(BANK) + OperationRegion (IROU, SystemIO, Local3, 4) + Field (IROU, AnyAcc, NoLock, Preserve) { + GROU, 32, + } + + // GPIO_ROUTE[GPIO] = 0 (SCI) + Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU) + + // + // Set GPnCONFIG to GPIO|INPUT|INVERT + // + + // Local3 = GPIOBASE + GPnCONFIG0(GPIO) + Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3) + + // GPnCONFIG(GPIO) + OperationRegion (GPNC, SystemIO, Local3, 8) + Field (GPNC, AnyAcc, NoLock, Preserve) { + GMOD, 1, // MODE: 0=NATIVE 1=GPIO + , 1, + GIOS, 1, // IO_SEL: 0=OUTPUT 1=INPUT + GINV, 1, // INVERT: 0=NORMAL 1=INVERT + GLES, 1, // LxEB: 0=EDGE 1=LEVEL + , 24, + ILVL, 1, // INPUT: 0=LOW 1=HIGH + OLVL, 1, // OUTPUT: 0=LOW 1=HIGH + GPWP, 2, // PULLUP: 00=NONE 01=DOWN 10=UP 11=INVALID + ISEN, 1, // SENSE: 0=ENABLE 1=DISABLE + } + + Store (0x1, GMOD) // GPIO + Store (0x1, GIOS) // INPUT + Store (0x1, GINV) // INVERT + } +} diff --git a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl index ef1e655..24da73e 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl +++ b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl @@ -23,6 +23,31 @@ #include "irqlinks.asl" + OperationRegion(LPC0, PCI_Config, 0x00, 0x100) + Field (LPC0, AnyAcc, NoLock, Preserve) + { + Offset (0x02), + PDID, 16, // Device ID + Offset (0x40), + PMBS, 16, // PMBASE + Offset (0x48), + GPBS, 16, // GPIOBASE + Offset (0x60), // Interrupt Routing Registers + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + Offset (0x68), + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + + Offset (0x80), // IO Decode Ranges + IOD0, 8, + IOD1, 8, + } + Device (FWH) // Firmware Hub { Name (_HID, EISAID("INT0800")) @@ -89,4 +114,6 @@ IRQNoFlags() {0} }) } + + #include "gpio.asl" } -- To view, visit https://review.coreboot.org/c/coreboot/+/37545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I6387faed4dc97c9efc130aa3ade4754118edc8b8 Gerrit-Change-Number: 37545 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang Gerrit-MessageType: newchange

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Change in coreboot[master]: vboot: Clear secdata change flags after factory init
by Julius Werner (Code Review) 06 Dec '19

06 Dec '19

Hello Joel Kitching, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37471 to review the following change. Change subject: vboot: Clear secdata change flags after factory init ...................................................................... vboot: Clear secdata change flags after factory init factory_initialize_tpm() calls secdata_xxx_create() (for both firmware and kernel space) and then immediately writes those spaces out to the TPM. The create() functions make vboot think it just changed the secdata (because it reinitialized the byte arrays in the context), so we also need to clear the VB2_CONTEXT_SECDATA_xxx_CHANGED flags again, otherwise vboot thinks it still needs to flush the spaces out to the TPM even though we already did that. Change-Id: I231fadcf7b35a1aec3b39254e7e41c3d456d4911 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_logic.c 2 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/37471/1 diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 0afd00d..e4d49f7 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -188,7 +188,7 @@ if (rv != TPM_SUCCESS) return rv; - return safe_write(index, data, length); + return write_secdata(index, data, length); } static uint32_t set_firmware_space(const void *firmware_blob) @@ -398,6 +398,9 @@ if (result != TPM_SUCCESS) return result; + ctx->flags &= ~(VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED | + VB2_CONTEXT_SECDATA_KERNEL_CHANGED); + VBDEBUG("TPM: factory initialization successful\n"); return TPM_SUCCESS; diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index ccce148..6c4f8fd 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -265,10 +265,10 @@ void vboot_save_data(struct vb2_context *ctx) { - if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) { + if (ctx->flags & VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED) { printk(BIOS_INFO, "Saving secdata\n"); antirollback_write_space_firmware(ctx); - ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED; + ctx->flags &= ~VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED; } vboot_save_nvdata_only(ctx); -- To view, visit https://review.coreboot.org/c/coreboot/+/37471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I231fadcf7b35a1aec3b39254e7e41c3d456d4911 Gerrit-Change-Number: 37471 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: vboot: update VbExNvStorageWrite function
by Joel Kitching (Code Review) 06 Dec '19

06 Dec '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37315 ) Change subject: vboot: update VbExNvStorageWrite function ...................................................................... vboot: update VbExNvStorageWrite function Going forwards, vb2ex_commit_data will be used to flush both nvdata and secdata. BUG=b:124141368, chromium:1006689 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ia2612da0df101cd3c46151dbce728633a39fada1 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/ec_sync.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/37315/1 diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index c2a6b25..8a3ba71 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -399,9 +399,9 @@ /* * Write opaque data into NV storage region. */ -vb2_error_t VbExNvStorageWrite(const uint8_t *buf) +vb2_error_t vb2ex_commit_data(struct vb2_context *ctx) { - save_vbnv(buf); + save_vbnv(ctx->nvdata); return VB2_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2612da0df101cd3c46151dbce728633a39fada1 Gerrit-Change-Number: 37315 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019