coreboot-gerrit December 2019

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Change in coreboot[master]: mb/asus/am1i-a: Remove defined and not used ITE_CONFIG_REG_CC
by HAOUAS Elyes (Code Review) 08 Dec '19

08 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37569 ) Change subject: mb/asus/am1i-a: Remove defined and not used ITE_CONFIG_REG_CC ...................................................................... mb/asus/am1i-a: Remove defined and not used ITE_CONFIG_REG_CC Change-Id: I934830c09f7996e8f5aae5d5abe9fb6014fb478d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/am1i-a/romstage.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/37569/1 diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c index 5e1218a..c0f5c04 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/romstage.c @@ -24,8 +24,6 @@ #include <superio/ite/common/ite.h> #include <superio/ite/it8623e/it8623e.h> -#define ITE_CONFIG_REG_CC 0x02 - #if CONFIG_UART_FOR_CONSOLE == 0 #define SERIAL_DEV PNP_DEV(0x2e, IT8623E_SP1) #elif CONFIG_UART_FOR_CONSOLE == 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I934830c09f7996e8f5aae5d5abe9fb6014fb478d Gerrit-Change-Number: 37569 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 08 Dec '19

08 Dec '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#29). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow This is the core patch that implement CSE FW update flow. To enable the FW update flow the following are required: * Descriptor change to accommodate a larger CSME region The CSME size is 6MB for the POC. * FMAP changes to accommodate ME update binary in RW CBFSes. Due to the increased CSME binary size and to accommodate the extra CSME RW binaries (which are ~2.5 MB) in RW CBFSes, the board FMAP has to be modified. * The new CSE binary with new partitions and respective RW area binaries. The following changes have been done in this patch: * Implement Update flow Get the partition info containing version of ME RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. Send global reset command to reset only the CSME Wait for CSME to enter SOFT_TEMP_DISABLE operation mode (indicated by HFSTS1 register bit 19:16) Enable HMRFPO (Host ME Region Flash Protection Override) using the HMRFPO_ENABLE HECI command Erase and Copy the CBFS ME RW to ME RW partition Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command Trigger global reset The system should boot with the Updated ME Verified that the basic update flows are working on Cometlake RVP and hatch. BUG=b:111330995 Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/cse_update.c A src/soc/intel/common/basecode/include/intelbasecode/cse_update.h 4 files changed, 451 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 29 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 08 Dec '19

08 Dec '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#37). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- ------------------ -------------------------- |CSE REGION | => | RO | RW | => | BP1 | BP2 + BP3 + DATA | ------------- ------------------ -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows the coreboot to set CSE to boot from required boot partition(either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. BUG=b:145809764 Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 501 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 37 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by build bot (Jenkins) (Code Review) 08 Dec '19

08 Dec '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 36: (42 comments) https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse_bp.c: https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 304: if (!cse_init_bp_info(false)) code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 304: if (!cse_init_bp_info(false)) please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 305: return false; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 305: return false; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 307: printk(BIOS_DEBUG, " No of partitions = %d\n", cse_bp_info.total_number_of_bp); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 307: printk(BIOS_DEBUG, " No of partitions = %d\n", cse_bp_info.total_number_of_bp); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 308: printk(BIOS_DEBUG, " current partition = %d\n", GET_BP(cse_bp_info.current_bp)); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 308: printk(BIOS_DEBUG, " current partition = %d\n", GET_BP(cse_bp_info.current_bp)); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 309: printk(BIOS_DEBUG, " Next partition = %d\n", GET_BP(cse_bp_info.next_bp)); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 309: printk(BIOS_DEBUG, " Next partition = %d\n", GET_BP(cse_bp_info.next_bp)); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 310: printk(BIOS_DEBUG, " Flags =0x%x\n", cse_bp_info.flags); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 310: printk(BIOS_DEBUG, " Flags =0x%x\n", cse_bp_info.flags); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 312: uint8_t bp_index; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 312: uint8_t bp_index; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 313: for (bp_index = 0; bp_index < cse_bp_info.total_number_of_bp; bp_index++) { code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 313: for (bp_index = 0; bp_index < cse_bp_info.total_number_of_bp; bp_index++) { please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 314: printk(BIOS_DEBUG, " BP%d version = %d.%d.%d.%d\n", GET_BP(bp_index), code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 314: printk(BIOS_DEBUG, " BP%d version = %d.%d.%d.%d\n", GET_BP(bp_index), please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 315: cse_bp_info.bp_entries[bp_index].fw_version.major, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 315: cse_bp_info.bp_entries[bp_index].fw_version.major, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 316: cse_bp_info.bp_entries[bp_index].fw_version.minor, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 316: cse_bp_info.bp_entries[bp_index].fw_version.minor, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 317: cse_bp_info.bp_entries[bp_index].fw_version.hotfix, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 317: cse_bp_info.bp_entries[bp_index].fw_version.hotfix, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 318: cse_bp_info.bp_entries[bp_index].fw_version.build); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 318: cse_bp_info.bp_entries[bp_index].fw_version.build); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 319: printk(BIOS_DEBUG, " BP%d start offset = 0x%x\n", GET_BP(bp_index), code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 319: printk(BIOS_DEBUG, " BP%d start offset = 0x%x\n", GET_BP(bp_index), please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 320: cse_bp_info.bp_entries[bp_index].bp_start_offset); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 320: cse_bp_info.bp_entries[bp_index].bp_start_offset); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 321: printk(BIOS_DEBUG, " BP%d end offset = 0x%x\n", GET_BP(bp_index), code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 321: printk(BIOS_DEBUG, " BP%d end offset = 0x%x\n", GET_BP(bp_index), please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 322: cse_bp_info.bp_entries[bp_index].bp_end_offset); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 322: cse_bp_info.bp_entries[bp_index].bp_end_offset); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 323: printk(BIOS_DEBUG, " BP%d boot partition status = 0x%x\n", GET_BP(bp_index), code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 323: printk(BIOS_DEBUG, " BP%d boot partition status = 0x%x\n", GET_BP(bp_index), please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 324: cse_bp_info.bp_entries[bp_index].bp_status); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 324: cse_bp_info.bp_entries[bp_index].bp_status); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 325: } code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 325: } please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 326: return true; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35402/36/src/soc/intel/common/bloc… PS36, Line 326: return true; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 36 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Sun, 08 Dec 2019 17:36:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 08 Dec '19

08 Dec '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#28). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow This is the core patch that implement CSE FW update flow. To enable the FW update flow the following are required: * Descriptor change to accommodate a larger CSME region The CSME size is 6MB for the POC. * FMAP changes to accommodate ME update binary in RW CBFSes. Due to the increased CSME binary size and to accommodate the extra CSME RW binaries (which are ~2.5 MB) in RW CBFSes, the board FMAP has to be modified. * The new CSE binary with new partitions and respective RW area binaries. The following changes have been done in this patch: * Implement Update flow Get the partition info containing version of ME RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. Send global reset command to reset only the CSME Wait for CSME to enter SOFT_TEMP_DISABLE operation mode (indicated by HFSTS1 register bit 19:16) Enable HMRFPO (Host ME Region Flash Protection Override) using the HMRFPO_ENABLE HECI command Erase and Copy the CBFS ME RW to ME RW partition Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command Trigger global reset The system should boot with the Updated ME Verified that the basic update flows are working on Cometlake RVP and hatch. BUG=P:111330995 Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/cse_update.c A src/soc/intel/common/basecode/include/intelbasecode/cse_update.h 4 files changed, 451 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 28 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 08 Dec '19

08 Dec '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#36). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- ------------------ -------------------------- |CSE REGION | => | RO | RW | => | BP1 | BP2 + BP3 + DATA | ------------- ------------------ -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows the coreboot to set CSE to boot from required boot partition(either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. BUG=P:145809764 Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 501 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/36 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 36 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Minor clean up some late comments
by Sridhar Siricilla (Code Review) 08 Dec '19

08 Dec '19

Sridhar Siricilla has uploaded a new patch set (#13) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/common/block/cse: Minor clean up some late comments ...................................................................... soc/intel/common/block/cse: Minor clean up some late comments Made some changes based on comments received on merged patches. * Consistent HECI command/group ID naming * Add description for structure members. * Fix up HFSTS1 inconsistency between APL/GKL and rest of the platforms. * Correct comment mentioned for wrapper #ifndef TEST=Build and Boot hatch board. Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 23 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35546/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 13 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendorcode/intel: Remove Ice Lake, Commet Lake and Denverton FSP Bind...
by Mimoja (Code Review) 08 Dec '19

08 Dec '19

Hello Patrick Rudolph, Vanessa Eusebio, Angel Pons, build bot (Jenkins), Nico Huber, David Guckian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37579 to look at the new patch set (#6). Change subject: vendorcode/intel: Remove Ice Lake, Commet Lake and Denverton FSP Bindings ...................................................................... vendorcode/intel: Remove Ice Lake, Commet Lake and Denverton FSP Bindings By updating the fsp submodule we now got all FSP headers from within that repo. This commit changes the default paths to use these and fixes some include paths to allow the usage of vendorcode/intel/edk2/UDK2017 together with the official Intel distribution. We are also adding back the CHANNEL_PRESENT enum, that has been removed by Intel. Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/tigerlake/romstage/romstage.c D src/vendorcode/intel/fsp/fsp2_0/cometlake/FirmwareVersionInfoHob.h D src/vendorcode/intel/fsp/fsp2_0/cometlake/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h D src/vendorcode/intel/fsp/fsp2_0/cometlake/MemInfoHob.h D src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FsptUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FirmwareVersionInfoHob.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FsptUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/MemInfoHob.h 21 files changed, 25 insertions(+), 15,556 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/37579/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/37579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Gerrit-Change-Number: 37579 Gerrit-PatchSet: 6 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: test
by HAOUAS Elyes (Code Review) 08 Dec '19

08 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37583 ) Change subject: test ...................................................................... test Change-Id: I00e5fe7686072be77cacf754be0d13e5f458d058 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/kahlee/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37583/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 86325532..f1b4ef2 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +#test + config BOARD_GOOGLE_BASEBOARD_KAHLEE bool select SOC_AMD_STONEYRIDGE_FT4 -- To view, visit https://review.coreboot.org/c/coreboot/+/37583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00e5fe7686072be77cacf754be0d13e5f458d058 Gerrit-Change-Number: 37583 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel: Remove {Ice,Commet}Lake and Denverton FSB Bindings
by Mimoja (Code Review) 08 Dec '19

08 Dec '19

Hello Patrick Rudolph, Angel Pons, build bot (Jenkins), Nico Huber, David Guckian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37579 to look at the new patch set (#5). Change subject: vendorcode/intel: Remove {Ice,Commet}Lake and Denverton FSB Bindings ...................................................................... vendorcode/intel: Remove {Ice,Commet}Lake and Denverton FSB Bindings By updating the fsp submodule we now got all FSP headers from within that repo. This commit changes the default paths to use these and fixes some include paths to allow the usage of vendorcode/intel/edk2/UDK2017 together with the official Intel distribution. We are also adding back the CHANNEL_PRESENT enum, that has been removed by Intel. Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/tigerlake/romstage/romstage.c D src/vendorcode/intel/fsp/fsp2_0/cometlake/FirmwareVersionInfoHob.h D src/vendorcode/intel/fsp/fsp2_0/cometlake/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h D src/vendorcode/intel/fsp/fsp2_0/cometlake/MemInfoHob.h D src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FsptUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FirmwareVersionInfoHob.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FsptUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/MemInfoHob.h 21 files changed, 25 insertions(+), 15,556 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/37579/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/37579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Gerrit-Change-Number: 37579 Gerrit-PatchSet: 5 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2019