coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init
by Frans Hendriks (Code Review) 09 Dec '19

09 Dec '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 ) Change subject: drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/28464/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/28464/1//COMMIT_MSG@9 PS1, Line 9: FSP code will default enable the onboard serial port. : When external serial port is used, this onboard port needs to be : disabled. : Add function mainboard_after_memory_init() function to perform : required actions to re-enabled output to external serial port. > Please add a blank line between paragraphs. Done https://review.coreboot.org/c/coreboot/+/28464/3/src/drivers/intel/fsp1_1/r… File src/drivers/intel/fsp1_1/raminit.c: https://review.coreboot.org/c/coreboot/+/28464/3/src/drivers/intel/fsp1_1/r… PS3, Line 128: mainboard_after_memory_init > This function is used with update of Facebook FBG-1701 ( https://review.coreboot. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Mon, 09 Dec 2019 12:54:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T
by Subrata Banik (Code Review) 09 Dec '19

09 Dec '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37187 ) Change subject: soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T ...................................................................... soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T It is a requirement for Firmware to have Firmware Interface Table (FIT), which contains pointers to each microcode update. The microcode update is loaded for all logical processors before reset vector. FSPT_UPD.MicrocodeRegionBase∗∗ and FSPT_UPD.MicrocodeRegionLength are input parameters to TempRamInit API. If these values are 0, FSP will not attempt to update microcode. Since Gen-6 all IA-SoC has FIT loading ucode even before cpu reset in place hence skipping FSP-T loading ucode after CPU reset options. Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/fspcar.c M src/soc/intel/cannonlake/bootblock/bootblock.c M src/soc/intel/denverton_ns/bootblock/bootblock.c M src/soc/intel/skylake/fspcar.c 4 files changed, 50 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/37187/1 diff --git a/src/soc/intel/apollolake/fspcar.c b/src/soc/intel/apollolake/fspcar.c index 8b1089f..129ff55 100644 --- a/src/soc/intel/apollolake/fspcar.c +++ b/src/soc/intel/apollolake/fspcar.c @@ -25,6 +25,17 @@ .FsptCommonUpd = { .Revision = 0, .Reserved = {0}, + /* + * It is a requirement for firmware to have Firmware Interface Table + * (FIT), whioch contains pointers to each microcode update. + * The microcode update is loaded for all logical processors before + * cpu reset vector. + * + * All SoC since Gen-6 has above mechanism in place to load microcode + * even before hitting CPU reset vector. Hence skipping FSP-T loading + * microcode after CPU reset by passing '0' value to + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + */ .MicrocodeRegionBase = 0, .MicrocodeRegionLength = 0, .CodeRegionBase = diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 653ba30..9826748 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -30,10 +30,19 @@ .Reserved = {0}, }, .FsptCoreUpd = { - .MicrocodeRegionBase = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, - .MicrocodeRegionSize = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, + /* + * It is a requirement for firmware to have Firmware Interface Table + * (FIT), whioch contains pointers to each microcode update. + * The microcode update is loaded for all logical processors before + * cpu reset vector. + * + * All SoC since Gen-6 has above mechanism in place to load microcode + * even before hitting CPU reset vector. Hence skipping FSP-T loading + * microcode after CPU reset by passing '0' value to + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + */ + .MicrocodeRegionBase = 0, + .MicrocodeRegionLength = 0, .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index f75de1f..58ce3de 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -31,10 +31,19 @@ .Reserved = {0}, }, .FsptCoreUpd = { - .MicrocodeRegionBase = - (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC, - .MicrocodeRegionLength = - (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN, + /* + * It is a requirement for firmware to have Firmware Interface Table + * (FIT), whioch contains pointers to each microcode update. + * The microcode update is loaded for all logical processors before + * cpu reset vector. + * + * All SoC since Gen-6 has above mechanism in place to load microcode + * even before hitting CPU reset vector. Hence skipping FSP-T loading + * microcode after CPU reset by passing '0' value to + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + */ + .MicrocodeRegionBase = 0, + .MicrocodeRegionLength = 0, .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE, diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c index a4c3726..fff240a 100644 --- a/src/soc/intel/skylake/fspcar.c +++ b/src/soc/intel/skylake/fspcar.c @@ -23,10 +23,19 @@ .Reserved = {0}, }, .FsptCoreUpd = { - .MicrocodeRegionBase = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, - .MicrocodeRegionSize = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, + /* + * It is a requirement for firmware to have Firmware Interface Table + * (FIT), whioch contains pointers to each microcode update. + * The microcode update is loaded for all logical processors before + * cpu reset vector. + * + * All SoC since Gen-6 has above mechanism in place to load microcode + * even before hitting CPU reset vector. Hence skipping FSP-T loading + * microcode after CPU reset by passing '0' value to + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + */ + .MicrocodeRegionBase = 0, + .MicrocodeRegionLength = 0, .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, -- To view, visit https://review.coreboot.org/c/coreboot/+/37187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455 Gerrit-Change-Number: 37187 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: FIX Supermicro
by Christian Walter (Code Review) 09 Dec '19

09 Dec '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37606 ) Change subject: FIX Supermicro ...................................................................... FIX Supermicro Change-Id: I5450d133e2ef1cc090a5746c260917394420511a Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/mainboard/supermicro/x11sch/Kconfig M src/mainboard/supermicro/x11sch/variants/x11sch-f/gpio.c M src/mainboard/supermicro/x11sch/variants/x11sch-f/overridetree.cb 3 files changed, 30 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/37606/1 diff --git a/src/mainboard/supermicro/x11sch/Kconfig b/src/mainboard/supermicro/x11sch/Kconfig index c658c8a..4c7e6fb 100644 --- a/src/mainboard/supermicro/x11sch/Kconfig +++ b/src/mainboard/supermicro/x11sch/Kconfig @@ -7,8 +7,10 @@ select HAVE_ACPI_TABLES select SOC_INTEL_CANNONLAKE_PCH_H select SUPERIO_ASPEED_COMMON_PRE_RAM + select SUPERIO_ASPEED_AST2400 select DRIVERS_ASPEED_AST_COMMON select DRIVERS_ASPEED_AST2050 + select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE config MAINBOARD_FAMILY string diff --git a/src/mainboard/supermicro/x11sch/variants/x11sch-f/gpio.c b/src/mainboard/supermicro/x11sch/variants/x11sch-f/gpio.c index 7ba738a..f30e8b4 100644 --- a/src/mainboard/supermicro/x11sch/variants/x11sch-f/gpio.c +++ b/src/mainboard/supermicro/x11sch/variants/x11sch-f/gpio.c @@ -19,21 +19,21 @@ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { - /* ESPI_ALERT1# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000f02, 0x00000000), -/* ESPI_IO0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000f00, 0x00000000), -/* ESPI_IO1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000f02, 0x00000000), -/* ESPI_IO2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000f00, 0x00000000), -/* ESPI_IO3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000f00, 0x00000000), -/* ESPI_CS0# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000f00, 0x00000000), + /* ESPI_ALERT1# */ //_PAD_CFG_STRUCT(GPP_A0, 0x44000f02, 0x00000000), +/* ESPI_IO0 */ //_PAD_CFG_STRUCT(GPP_A1, 0x44000f00, 0x00000000), +/* ESPI_IO1 */ //_PAD_CFG_STRUCT(GPP_A2, 0x44000f02, 0x00000000), +/* ESPI_IO2 */ //_PAD_CFG_STRUCT(GPP_A3, 0x44000f00, 0x00000000), +/* ESPI_IO3 */ //_PAD_CFG_STRUCT(GPP_A4, 0x44000f00, 0x00000000), +/* ESPI_CS0# */ //_PAD_CFG_STRUCT(GPP_A5, 0x44000f00, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_A6, 0x44000102, 0x00000000), -/* ESPI_ALERT0# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000f02, 0x00000000), +/* ESPI_ALERT0# */ //_PAD_CFG_STRUCT(GPP_A7, 0x44000f02, 0x00000000), /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000502, 0x00000000), -/* ESPI_CLK */ _PAD_CFG_STRUCT(GPP_A9, 0x44000f00, 0x00000000), +/* ESPI_CLK */ //_PAD_CFG_STRUCT(GPP_A9, 0x44000f00, 0x00000000), /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000600, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80880102, 0x00000000), /* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000600, 0x00000000), -/* ESPI_RESET# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000f00, 0x00000000), +/* ESPI_RESET# */ //_PAD_CFG_STRUCT(GPP_A14, 0x44000f00, 0x00000000), /* SUSACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_A16, 0x44000200, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000200, 0x00000000), diff --git a/src/mainboard/supermicro/x11sch/variants/x11sch-f/overridetree.cb b/src/mainboard/supermicro/x11sch/variants/x11sch-f/overridetree.cb index 7e0197c..3904b30 100644 --- a/src/mainboard/supermicro/x11sch/variants/x11sch-f/overridetree.cb +++ b/src/mainboard/supermicro/x11sch/variants/x11sch-f/overridetree.cb @@ -18,7 +18,7 @@ register "SataPortsEnable[6]" = "1" register "SataPortsEnable[7]" = "1" - register "PchHdaDspEnable" = "0" + register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" register "PcieRpEnable[1]" = "1" @@ -97,10 +97,11 @@ register "speed_shift_enable" = "1" # HECI - register "HeciEnabled" = "1" + register "Heci1Disabled" = "0" + register "Heci3Enabled" = "1" # Internal GFX - register "InternalGfx" = "0" + register "InternalGfx" = "1" # Enable S0ix register "s0ix_enable" = "1" @@ -117,40 +118,37 @@ device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end - device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 on end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 on end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 + device pci 16.0 on end # Management Engine Interface + device pci 16.1 on end # Management Engine Interface + device pci 16.4 on end # Management Engine Interface device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1b.0 on end - device pci 1b.4 on end # Ethernet - device pci 1b.5 on end # Ethernet - device pci 1c.0 on end # LPC Interface - device pci 1c.1 on end # Aspeed Graphics - device pci 1c.4 on end # NVMe PCIE x4 - device pci 1d.0 on end # PCIE x4 + device pci 1a.0 on end # eMMC + device pci 1b.0 on end + device pci 1b.4 on end # onboard Ethernet + device pci 1b.5 on end # onboard Ethernet + device pci 1c.0 on end # LPC Interface + device pci 1c.1 on end # Aspeed Graphics + device pci 1c.4 on end # NVMe PCIE x4 + device pci 1d.0 on end # PCIE x4 device pci 1e.0 on end # UART #0 - device pci 1f.0 on end # LPC Interface + device pci 1f.0 on # LPC Interface chip superio/common device pnp 4e.0 on chip superio/aspeed/ast2400 device pnp 4e.2 on # SUART1 io 0x60 = 0x3f8 irq 0x70 = 4 + irq 0x71 = 0 end device pnp 4e.3 on # SUART2 io 0x60 = 0x2f8 irq 0x70 = 3 + irq 0x71 = 0 end device pnp 4e.4 off end # SWC device pnp 4e.5 off end # KBC @@ -162,6 +160,7 @@ end end end + end device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI end -- To view, visit https://review.coreboot.org/c/coreboot/+/37606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5450d133e2ef1cc090a5746c260917394420511a Gerrit-Change-Number: 37606 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile: Write .xcompile to $(obj)
by Patrick Georgi (Code Review) 09 Dec '19

09 Dec '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28101 ) Change subject: Makefile: Write .xcompile to $(obj) ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/28101/10/util/abuild/abuild File util/abuild/abuild: https://review.coreboot.org/c/coreboot/+/28101/10/util/abuild/abuild@475 PS10, Line 475: $(xcompile) this is an immediate execution of make (see line 473), so who sets that variable? -- To view, visit https://review.coreboot.org/c/coreboot/+/28101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Gerrit-Change-Number: 28101 Gerrit-PatchSet: 10 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Mon, 09 Dec 2019 12:02:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init
by Frans Hendriks (Code Review) 09 Dec '19

09 Dec '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 ) Change subject: drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... Patch Set 4: > Patch Set 4: > > Heads up - Somebody from Intel commented on https://github.com/IntelFsp/FSP/issues/15 and says it has something to do with coreboot setting the UARTs to ACPI mode. The suggested fix is to conditionally set PcdEnableHsuart0 and PcdEnableHsuart1 (see the issue on Github for details). Intel provided fix in routine, which is not available in coreboot (Intel fix is based on soc\intel\fsp_braswell where coreboot uses soc\intel\braswell). The problem is not the configuration of the HSUART, but the internal UART is enabled. Having this internal UART enabled, causes external UART (0x3F8) can not be used/accessed. FSP enables the internal using 'SerialPortEnable' which is a build option and can not be configured external. Imo this issue has not a coreboot cause, but still an Intel FSP bug. -- To view, visit https://review.coreboot.org/c/coreboot/+/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Mon, 09 Dec 2019 11:05:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/w530/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 09 Dec '19

09 Dec '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37385 ) Change subject: mb/lenovo/w530/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/w530/devicetree: Use subsystemid inheritance Change-Id: I0646b18e823c52109e0fb62c85726622156172b9 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t530/variants/w530/devicetree.cb 1 file changed, 32 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/37385/1 diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 0844124..f197f17 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -37,6 +37,8 @@ register "pci_mmio_size" = "2048" device domain 0x0 on + subsystemid 0x17aa 0x21f6 inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) @@ -60,67 +62,39 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x04000201" register "xhci_switchable_ports" = "0x0000000f" - device pci 14.0 on # USB 3.0 Controller - subsystemid 0x17aa 0x21f6 - end - device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x17aa 0x21f6 - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 on # Management Engine KT - subsystemid 0x17aa 0x21f6 - end + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 on end # Management Engine KT device pci 19.0 on # Intel Gigabit Ethernet subsystemid 0x17aa 0x21f3 end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x17aa 0x21f6 - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x17aa 0x21f6 - end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller device pci 1c.0 on # PCIe Port #1 - subsystemid 0x17aa 0x21f6 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x83" register "sdwppol" = "1" - device pci 00.0 on # Ricoh SD card reader - subsystemid 0x17aa 0x21f6 - end + device pci 00.0 on end # Ricoh SD card reader end end - device pci 1c.1 on # PCIe Port #2 - subsystemid 0x17aa 0x21f6 - end + device pci 1c.1 on end # PCIe Port #2 device pci 1c.2 on # PCIe Port #3 - subsystemid 0x17aa 0x21f6 smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end - device pci 1c.3 off # PCIe Port #4 - end - device pci 1c.4 off # PCIe Port #5 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x17aa 0x21f6 - end - device pci 1e.0 off # PCI bridge - end + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x17aa 0x21f6 chip ec/lenovo/pmh7 register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy end chip drivers/pc80/tpm @@ -178,41 +152,25 @@ register "has_thinker1" = "1" end end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x17aa 0x21f6 + device pci 1f.2 on end # SATA Controller 1 end device pci 1f.3 on # SMBus - subsystemid 0x17aa 0x21f6 chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip - device i2c 54 on - end - device i2c 55 on - end - device i2c 56 on - end - device i2c 57 on - end - device i2c 5c on - end - device i2c 5d on - end - device i2c 5e on - end - device i2c 5f on - end + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end end end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x17aa 0x21f6 - end - device pci 01.0 on # PCIe Bridge for discrete graphics - subsystemid 0x17aa 0x21f6 - end + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on # Internal graphics VGA controller subsystemid 0x17aa 0x21f5 end -- To view, visit https://review.coreboot.org/c/coreboot/+/37385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0646b18e823c52109e0fb62c85726622156172b9 Gerrit-Change-Number: 37385 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/lenovo/s230u/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 09 Dec '19

09 Dec '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37302 ) Change subject: mb/lenovo/s230u/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/s230u/devicetree: Use subsystemid inheritance Change-Id: I70eabc0b03709409d997ccbe8b8e257d68aec338 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/s230u/devicetree.cb 1 file changed, 35 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/37302/1 diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 15d323d..8d1ec4a 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -27,14 +27,12 @@ end end device domain 0x0 on - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x17aa 0x2205 - end - device pci 01.0 off # PCIe Bridge for discrete graphics - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x17aa 0x2205 - end + subsystemid 0x17aa 0x2205 inherit + + device pci 00.0 on end Host bridge Host bridge + device pci 01.0 off end PCIe Bridge for discrete graphics + device pci 02.0 on end Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "1" @@ -55,83 +53,44 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on # USB 3.0 Controller - subsystemid 0x17aa 0x2205 - end - device pci 16.0 off # Management Engine Interface 1 - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 off # Management Engine KT - end - device pci 19.0 off # Intel Gigabit Ethernet - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x17aa 0x2205 - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x17aa 0x2205 - end - device pci 1c.0 on # PCIe Port #1 - subsystemid 0x17aa 0x2205 - end - device pci 1c.1 on # PCIe Port #2 - subsystemid 0x17aa 0x2205 - end - device pci 1c.2 off # PCIe Port #3 - end - device pci 1c.3 on # PCIe Port #4 - subsystemid 0x17aa 0x2205 - end - device pci 1c.4 off # PCIe Port #5 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x17aa 0x2205 - end - device pci 1e.0 off # PCI bridge - end + device pci 14.0 on end USB 3.0 Controller + device pci 16.0 off end Management Engine Interface 1 + device pci 16.1 off end Management Engine Interface 2 + device pci 16.2 off end Management Engine IDE-R + device pci 16.3 off end Management Engine KT + device pci 19.0 off end Intel Gigabit Ethernet + device pci 1a.0 on end USB2 EHCI #2 + device pci 1b.0 on end High Definition Audio Audio controller + device pci 1c.0 on end PCIe Port #1 + device pci 1c.1 on end PCIe Port #2 + device pci 1c.2 off end PCIe Port #3 + device pci 1c.3 on end PCIe Port #4 + device pci 1c.4 off end PCIe Port #5 + device pci 1c.5 off end PCIe Port #6 + device pci 1c.6 off end PCIe Port #7 + device pci 1c.7 off end PCIe Port #8 + device pci 1d.0 on end USB2 EHCI #1 + device pci 1e.0 off end PCI bridge device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x17aa 0x2205 chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x17aa 0x2205 - end + device pci 1f.2 on end SATA Controller 1 device pci 1f.3 on # SMBus - subsystemid 0x17aa 0x2205 chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip - device i2c 54 on - end - device i2c 55 on - end - device i2c 56 on - end - device i2c 57 on - end - device i2c 5c on - end - device i2c 5d on - end - device i2c 5e on - end - device i2c 5f on - end + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end end end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.5 off end SATA Controller 2 + device pci 1f.6 off end Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70eabc0b03709409d997ccbe8b8e257d68aec338 Gerrit-Change-Number: 37302 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/lenovo/t430s/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 09 Dec '19

09 Dec '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37300 ) Change subject: mb/lenovo/t430s/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/t430s/devicetree: Use subsystemid inheritance Change-Id: Ifde5d382eb223bd996b9bb909c751e9d5f0a11e5 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb 2 files changed, 13 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37300/1 diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 0c2f668..8be7cba 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -36,13 +36,11 @@ register "pci_mmio_size" = "2048" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21fb - end # host bridge + subsystemid 0x17aa 0x21fb inherit + + device pci 00.0 on end # host bridge device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x21fb - end # Integrated Graphics Controller + device pci 02.0 on end # Integrated Graphics Controller chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # GPI routing @@ -76,9 +74,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on - subsystemid 0x17aa 0x21fb - end # USB 3.0 Controller + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -86,18 +82,11 @@ device pci 19.0 on subsystemid 0x17aa 0x21f3 end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21fb - end # USB Enhanced Host Controller #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21fb - end # High Definition Audio Controller + device pci 1a.0 on end # USB Enhanced Host Controller #2 + device pci 1b.0 on end # High Definition Audio Controller device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21fb - end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 on - subsystemid 0x17aa 0x21fb smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #3 ExpressCard device pci 1c.3 off end # PCIe Port #4 @@ -105,14 +94,11 @@ device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21fb - end # USB Enhanced Host Controller #1 + device pci 1d.0 on end # USB Enhanced Host Controller #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on - subsystemid 0x17aa 0x21fb chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy + device pnp ff.1 on end # dummy end register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" @@ -155,11 +141,8 @@ register "evente_enable" = "0x0d" end end # LPC Controller - device pci 1f.2 on - subsystemid 0x17aa 0x21fb - end # 6 port SATA AHCI Controller + device pci 1f.2 on end # 6 port SATA AHCI Controller device pci 1f.3 on - subsystemid 0x17aa 0x21fb # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -173,9 +156,7 @@ end end # SMBus Controller device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21fb - end # Thermal + device pci 1f.6 on end # Thermal end end end diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index ee94979..abbe4a8 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -3,9 +3,7 @@ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # Enable hotplug on Port 5 for Thunderbolt controller register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }" - device pci 1c.4 on - subsystemid 0x17aa 0x21fb - end # PCIe Port #5 Thunderbolt controller + device pci 1c.4 on end # PCIe Port #5 Thunderbolt controller device pci 1f.0 on chip ec/lenovo/h8 register "has_bdc_detection" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/37300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifde5d382eb223bd996b9bb909c751e9d5f0a11e5 Gerrit-Change-Number: 37300 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/lenovo/t430/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 09 Dec '19

09 Dec '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37299 ) Change subject: mb/lenovo/t430/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/t430/devicetree: Use subsystemid inheritance Change-Id: I53e9e1a8381ca51200dc5306eef32442668607a3 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t430/devicetree.cb 1 file changed, 35 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37299/1 diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index f7e0436..cfdc3a4 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -31,6 +31,8 @@ end device domain 0x0 on + subsystemid 0x17aa 0x21f3 inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "1" @@ -51,66 +53,37 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on # USB 3.0 Controller - subsystemid 0x17aa 0x21f3 - end - device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x17aa 0x21f3 - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 off # Management Engine KT - end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x17aa 0x21f3 - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x17aa 0x21f3 - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x17aa 0x21f3 - end + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller device pci 1c.0 on # PCIe Port #1 - subsystemid 0x17aa 0x21f3 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" register "sdwppol" = "1" - device pci 00.0 on # Ricoh SD card reader - subsystemid 0x17aa 0x21f3 - end + device pci 00.0 on end # Ricoh SD card reader end end - device pci 1c.1 on # PCIe Port #2 - subsystemid 0x17aa 0x21f3 - end + device pci 1c.1 on end # PCIe Port #2 device pci 1c.2 on # PCIe Port #3 - subsystemid 0x17aa 0x21f3 smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end - device pci 1c.3 off # PCIe Port #4 - end - device pci 1c.4 off # PCIe Port #5 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x17aa 0x21f3 - end - device pci 1e.0 off # PCI bridge - end + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x17aa 0x21f3 chip ec/lenovo/pmh7 register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy end chip ec/lenovo/h8 device pnp ff.2 on # dummy @@ -169,44 +142,25 @@ device pnp 0c31.0 on end end end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x17aa 0x21f3 - end + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBus - subsystemid 0x17aa 0x21f3 chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip - device i2c 54 on - end - device i2c 55 on - end - device i2c 56 on - end - device i2c 57 on - end - device i2c 5c on - end - device i2c 5d on - end - device i2c 5e on - end - device i2c 5f on - end + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end end end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x17aa 0x21f3 - end - device pci 01.0 on # PCIe Bridge for discrete graphics - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x17aa 0x21f3 - end - device pci 04.0 off # Signal processing controller - end + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + device pci 04.0 off end # Signal processing controller end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53e9e1a8381ca51200dc5306eef32442668607a3 Gerrit-Change-Number: 37299 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/lenovo/x230/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 09 Dec '19

09 Dec '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37298 ) Change subject: mb/lenovo/x230/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/x230/devicetree: Use subsystemid inheritance Change-Id: I95dbf55b74deca1e035ee1d042f1549d2583e346 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x230/devicetree.cb 1 file changed, 14 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/37298/1 diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 61a5468..9a0bef9 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -37,13 +37,11 @@ register "pci_mmio_size" = "1024" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21fa - end # host bridge + subsystemid 0x17aa 0x21fa inherit + + device pci 00.0 on end # host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x21fa - end # vga controller + device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -76,39 +74,25 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on - subsystemid 0x17aa 0x21fa - end # USB 3.0 Controller - device pci 16.0 on - subsystemid 0x17aa 0x21fa - end # Management Engine Interface 1 + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT device pci 19.0 on subsystemid 0x17aa 0x21f3 end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21fa - end # USB2 EHCI #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21fa - end # High Definition Audio + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio device pci 1c.0 on - subsystemid 0x17aa 0x21fa chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" - device pci 00.0 on - subsystemid 0x17aa 0x21fa - end + device pci 00.0 on end end end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21fa - end # PCIe Port #2 + device pci 1c.1 on end # PCIe Port #2 device pci 1c.2 on - subsystemid 0x17aa 0x21fa smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #3 (expresscard) device pci 1c.3 off end # PCIe Port #4 @@ -116,15 +100,11 @@ device pci 1c.5 off end # PCIe Port #6 device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21fa - end # USB2 EHCI #1 + device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on #LPC bridge - subsystemid 0x17aa 0x21fa chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on dummy # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -176,11 +156,8 @@ register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on - subsystemid 0x17aa 0x21fa - end # SATA Controller 1 + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on - subsystemid 0x17aa 0x21fa # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -194,9 +171,7 @@ end end # SMBus device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21fa - end # Thermal + device pci 1f.6 on end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95dbf55b74deca1e035ee1d042f1549d2583e346 Gerrit-Change-Number: 37298 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019