coreboot-gerrit December 2019

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Change in coreboot[4.11_branch]: drivers/ipmi: Add IPMI Read FRU function
by Johnny Lin (Code Review) 05 Dec '19

05 Dec '19

Hello Andrey Petrov, Jingle Hsu, Morgan Jang, Patrick Rudolph, Jonathan Zhang, David Hendricks, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37444 to look at the new patch set (#6). Change subject: drivers/ipmi: Add IPMI Read FRU function ...................................................................... drivers/ipmi: Add IPMI Read FRU function Implemented according to IPMI "Platform Management FRU Information Storage Definition" specification v1.0 for reading FRU data Product Info Area and Board Info Area. SMBIOS data can be updated with the FRU data. Tested on OCP Mono Lake. Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/ipmi/Kconfig M src/drivers/ipmi/Makefile.inc A src/drivers/ipmi/ipmi_fru.c M src/drivers/ipmi/ipmi_kcs.h M src/drivers/ipmi/ipmi_ops.h 5 files changed, 491 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/37444/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/37444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8 Gerrit-Change-Number: 37444 Gerrit-PatchSet: 6 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[4.11_branch]: mb/ocp/monolake: Override SMBIOS data with IPMI read FRU data
by Johnny Lin (Code Review) 05 Dec '19

05 Dec '19

Hello Andrey Petrov, Jingle Hsu, Morgan Jang, Patrick Rudolph, Jonathan Zhang, David Hendricks, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37445 to look at the new patch set (#6). Change subject: mb/ocp/monolake: Override SMBIOS data with IPMI read FRU data ...................................................................... mb/ocp/monolake: Override SMBIOS data with IPMI read FRU data SMBIOS type 1 data fields are overwritten by FRU product info area data, SMBIOS type 2 fields are overwritten by FRU board info area data. Tested on OCP Mono Lake. Change-Id: I58cbe95055dea053b115e99f354f40d5902c6a35 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/mainboard.c 2 files changed, 82 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37445/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/37445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I58cbe95055dea053b115e99f354f40d5902c6a35 Gerrit-Change-Number: 37445 Gerrit-PatchSet: 6 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7180: Add clock driver
by mturney mturney (Code Review) 05 Dec '19

05 Dec '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35496 ) Change subject: sc7180: Add clock driver ...................................................................... sc7180: Add clock driver Add support for clock driver for SC7180 Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/31083/6 Change-Id: I3f39252c887c36e8af43bc49289795000e4638d8 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Signed-off-by: srimuc <srimuc(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/clock.h 5 files changed, 468 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/35496/1 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index a973724..60ad516 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -7,12 +7,14 @@ bootblock-y += timer.c bootblock-y += gpio.c bootblock-y += spi.c +bootblock-y += clock.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ verstage-y += timer.c verstage-y += gpio.c verstage-y += spi.c +verstage-y += clock.c verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ @@ -23,6 +25,7 @@ romstage-y += ../common/mmu.c romstage-y += mmu.c romstage-y += spi.c +romstage-y += clock.c romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ @@ -31,6 +34,7 @@ ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += spi.c +ramstage-y += clock.c ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index b9b8660..f073449 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -14,9 +14,12 @@ */ #include <bootblock_common.h> +#include <soc/clock.h> #include <soc/mmu.h> +#include <soc/clock.h> void bootblock_soc_init(void) { sc7180_mmu_init(); + clock_init(); } diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c new file mode 100644 index 0000000..0ccbaa6 --- /dev/null +++ b/src/soc/qualcomm/sc7180/clock.c @@ -0,0 +1,251 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <commonlib/helpers.h> +#include <device/mmio.h> +#include <soc/clock.h> +#include <types.h> + +#define DIV(div) (2 * div - 1) + +struct clock_config qup_cfg[] = { + { + .hz = 7372800, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 384, + .n = 15625, + .d_2 = 15625, + }, + { + .hz = 19200 * KHz, + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + } +}; + +struct clock_config qspi_core_cfg[] = { + { + .hz = 19200 * KHz, + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(3), + }, + { + .hz = 150 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(2), + }, + { + .hz = 300 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + } +}; + +static int clock_configure_gpll0(void) +{ + write32(&gcc->gpll0.user_ctl_u, 0x00004805); + + /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ + setbits_le32(&gcc->gpll0.user_ctl, + 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); + + return 0; +} + +static int clock_configure_mnd(struct sc7180_clock *clk, uint32_t m, uint32_t n, + uint32_t d_2) +{ + setbits_le32(&clk->rcg.cfg, + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + + write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK); + write32(&clk->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); + write32(&clk->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); + + return 0; +} + +static int clock_configure_rcg(struct sc7180_rcg *clk, + struct clock_config *clk_cfg, + uint32_t hz, uint32_t num_perfs) +{ + uint32_t reg_val; + uint32_t idx; + + for (idx = 0; idx < num_perfs; idx++) + if (hz <= clk_cfg[idx].hz) + break; + + assert(hz == clk_cfg[idx].hz); + + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + /* Set clock config */ + write32(&clk->cfg, reg_val); + + /* Commit config to RCG */ + setbits_le32(&clk->cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return 0; +} + +static int clock_configure(struct sc7180_clock *clk, + struct clock_config *clk_cfg, + uint32_t hz, uint32_t num_perfs) +{ + uint32_t reg_val; + uint32_t idx; + + for (idx = 0; idx < num_perfs; idx++) + if (hz <= clk_cfg[idx].hz) + break; + + assert(hz == clk_cfg[idx].hz); + + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + /* Set clock config */ + write32(&clk->rcg.cfg, reg_val); + + if (clk_cfg[idx].m != 0) + clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, + clk_cfg[idx].d_2); + + /* Commit config to RCG*/ + setbits_le32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return 0; +} + +static bool clock_is_off(u32 *cbcr_addr) +{ + return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK); +} + +static int clock_enable_vote(void *cbcr_addr, void *vote_addr, + uint32_t vote_bit) +{ + /* Set clock vote bit */ + setbits_le32(vote_addr, BIT(vote_bit)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)) + ; + + return 0; +} + +static int clock_enable(void *cbcr_addr) +{ + /* Set clock enable bit */ + setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)) + ; + + return 0; +} + +void clock_reset_aop(void) +{ + /* Bring AOP out of RESET */ + clrbits_le32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); +} + +void clock_configure_qspi(uint32_t hz) +{ + clock_configure_rcg(&gcc->qspi_core, + qspi_core_cfg, hz, + ARRAY_SIZE(qspi_core_cfg)); + clock_enable(&gcc->qspi_cnoc_ahb_cbcr); + clock_enable(&gcc->qspi_core_cbcr); +} + +int clock_reset_bcr(void *bcr_addr, bool reset) +{ + struct sc7180_bcr *bcr = bcr_addr; + + if (reset) + setbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + else + clrbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + + return 0; +} + +void clock_configure_qup(int qup, uint32_t hz) +{ + int s = qup % QUP_WRAP1_S0; + struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + (struct sc7180_qupv3_clock *)&gcc->qup_wrap0_s[s] : + (struct sc7180_qupv3_clock *)&gcc->qup_wrap1_s[s]; + + clock_configure(&qup_clk->clk, qup_cfg, hz, ARRAY_SIZE(qup_cfg)); +} + +void clock_enable_qup(int qup) +{ + int s = qup % QUP_WRAP1_S0; + int clk_en_off = qup < QUP_WRAP1_S0 ? + QUPV3_WRAP0_CLK_ENA_S(s) : QUPV3_WRAP1_CLK_ENA_S(s); + struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + clock_enable_vote(&qup_clk->clk, &gcc->apcs_clk_br_en1, + clk_en_off); +} + +void clock_init(void) +{ + clock_configure_gpll0(); + + clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_S_AHB_CLK_ENA); + + clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_S_AHB_CLK_ENA); +} diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index 93f0481..308b2fb 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2018-2019 Qualcomm Technologies + * Copyright (c) 2019 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,4 +18,8 @@ #include <stdint.h> -#endif /* _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ */ +#define AOSS_CC_BASE 0x0C2A0000 +#define GCC_BASE 0x00100000 +#define QSPI_BASE 0x088DC000 + +#endif /* __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h new file mode 100644 index 0000000..d90779b --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/addressmap.h> +#include <types.h> + +#ifndef __SOC_QUALCOMM_SC7180_CLOCK_H__ +#define __SOC_QUALCOMM_SC7180_CLOCK_H__ + +#define QUPV3_WRAP_0_M_AHB_CLK_ENA 6 +#define QUPV3_WRAP_0_S_AHB_CLK_ENA 7 +#define QUPV3_WRAP0_CORE_2X_CLK_ENA 9 +#define QUPV3_WRAP0_CORE_CLK_ENA 8 +#define QUPV3_WRAP1_CORE_2X_CLK_ENA 18 +#define QUPV3_WRAP1_CORE_CLK_ENA 19 +#define QUPV3_WRAP_1_M_AHB_CLK_ENA 20 +#define QUPV3_WRAP_1_S_AHB_CLK_ENA 21 +#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) +#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) + +#define GPLL0_EVEN_HZ (300 * MHz) +#define GPLL0_MAIN_HZ (600 * MHz) +#define QUP_WRAP_CORE_2X_19_2MHZ (19200 * KHz) + +#define SRC_XO_19_2MHZ 0 +#define SRC_GPLL0_MAIN_600MHZ 1 +#define SRC_GPLL0_EVEN_300MHZ 6 + +#define AOP_RESET_SHFT 0 +#define RCG_MODE_DUAL_EDGE 2 + +struct sc7180_rcg { + u32 cmd; + u32 cfg; +}; + +struct sc7180_clock { + u32 cbcr; + struct sc7180_rcg rcg; + u32 m; + u32 n; + u32 d_2; +}; + +struct sc7180_qupv3_clock { + struct sc7180_clock clk; + u8 _res[0x130 - 0x18]; +}; + +struct sc7180_gpll { + u32 mode; + u32 l_val; + u32 cal_l_val; + u32 user_ctl; + u32 user_ctl_u; + u32 config_ctl; + u32 config_ctl_u; + u32 test_ctl; + u32 test_ctl_u; + u8 _res[0x1000 - 0x24]; +}; + +struct sc7180_gcc { + struct sc7180_gpll gpll0; + u8 _res0[0xf000 - 0x1000]; + u32 usb30_prim_bcr; + u8 _res3[0x17000 - 0xf004]; + u32 qup_wrap0_bcr; + u32 qup_wrap0_m_ahb_cbcr; + u32 qup_wrap0_s_ahb_cbcr; + u32 qup_wrap0_core_cbcr; + u32 qup_wrap0_core_cdivr; + u32 qup_wrap0_core_2x_cbcr; + struct sc7180_rcg qup_wrap0_core_2x; + u8 _res4[0x17030 - 0x17020]; + struct sc7180_qupv3_clock qup_wrap0_s[6]; + u8 _res5[0x18000 - 0x17750]; + u32 qup_wrap1_bcr; + u32 qup_wrap1_core_2x_cbcr; + u32 qup_wrap1_core_cbcr; + u32 qup_wrap1_m_ahb_cbcr; + u32 qup_wrap1_s_ahb_cbcr; + struct sc7180_qupv3_clock qup_wrap1_s[6]; + u8 _res6[0x18994 - 0x18734]; + u32 qup_wrap1_core_cdivr; + u8 _res7[0x4b000 - 0x18998]; + u32 qspi_bcr; + u32 qspi_cnoc_ahb_cbcr; + u32 qspi_core_cbcr; + struct sc7180_rcg qspi_core; + u8 _res8[0x50000 - 0x4b014]; + u32 usb3_phy_prim_bcr; + u32 usb3phy_phy_prim_bcr; + u32 usb3_dp_phy_prim_bcr; + u32 usb3_phy_sec_bcr; + u32 usb3phy_phy_sec_bcr; + u32 usb3_dp_phy_sec_bcr; + u8 _res9[0x52008 - 0x50018]; + u32 apcs_clk_br_en1; + u8 _res10[0x1000000 - 0x5200c]; +}; + +struct sc7180_aoss { + u8 _res[0x5002c]; + u32 aoss_cc_apcs_misc; +}; + +enum clk_ctl_gpll_user_ctl { + CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, + CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0, + CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1, + CLK_CTL_GPLL_PLLOUT_ODD_SHFT = 2 +}; + +enum clk_ctl_cfg_rcgr { + CLK_CTL_CFG_HW_CTL_BMSK = 0x100000, + CLK_CTL_CFG_HW_CTL_SHFT = 20, + CLK_CTL_CFG_MODE_BMSK = 0x3000, + CLK_CTL_CFG_MODE_SHFT = 12, + CLK_CTL_CFG_SRC_SEL_BMSK = 0x700, + CLK_CTL_CFG_SRC_SEL_SHFT = 8, + CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F, + CLK_CTL_CFG_SRC_DIV_SHFT = 0 +}; + +enum clk_ctl_cmd_rcgr { + CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000, + CLK_CTL_CMD_ROOT_OFF_SHFT = 31, + CLK_CTL_CMD_ROOT_EN_BMSK = 0x2, + CLK_CTL_CMD_ROOT_EN_SHFT = 1, + CLK_CTL_CMD_UPDATE_BMSK = 0x1, + CLK_CTL_CMD_UPDATE_SHFT = 0 +}; + +enum clk_ctl_cbcr { + CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000, + CLK_CTL_CBC_CLK_OFF_SHFT = 31, + CLK_CTL_CBC_CLK_EN_BMSK = 0x1, + CLK_CTL_CBC_CLK_EN_SHFT = 0 +}; + +enum clk_ctl_rcg_mnd { + CLK_CTL_RCG_MND_BMSK = 0xFFFF, + CLK_CTL_RCG_MND_SHFT = 0, +}; + +enum clk_ctl_bcr { + CLK_CTL_BCR_BLK_ARES_BMSK = 0x1, + CLK_CTL_BCR_BLK_ARES_SHFT = 0, +}; + +enum clk_qup { + QUP_WRAP0_S0, + QUP_WRAP0_S1, + QUP_WRAP0_S2, + QUP_WRAP0_S3, + QUP_WRAP0_S4, + QUP_WRAP0_S5, + QUP_WRAP1_S0, + QUP_WRAP1_S1, + QUP_WRAP1_S2, + QUP_WRAP1_S3, + QUP_WRAP1_S4, + QUP_WRAP1_S5, +}; + +struct clock_config { + uint32_t hz; + uint8_t src; + uint8_t div; + uint16_t m; + uint16_t n; + uint16_t d_2; +}; + +struct mdss_clock_config { + const char *clk_name; + uintptr_t rcgr; + uintptr_t cbcr; +}; + +static struct sc7180_gcc *const gcc = (void *)GCC_BASE; +static struct sc7180_aoss *const aoss = (void *)AOSS_CC_BASE; + +void clock_init(void); +void clock_reset_aop(void); +void clock_configure_qspi(uint32_t hz); +int clock_reset_bcr(void *bcr_addr, bool reset); +void clock_configure_qup(int qup, uint32_t hz); +void clock_enable_qup(int qup); + +#endif // __SOC_QUALCOMM_SC7180_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/35496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f39252c887c36e8af43bc49289795000e4638d8 Gerrit-Change-Number: 35496 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: drivers/ipmi: Add IPMI Read FRU function
by build bot (Jenkins) (Code Review) 05 Dec '19

05 Dec '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37444 ) Change subject: drivers/ipmi: Add IPMI Read FRU function ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/37444/5/src/drivers/ipmi/ipmi_fru.c File src/drivers/ipmi/ipmi_fru.c: https://review.coreboot.org/c/coreboot/+/37444/5/src/drivers/ipmi/ipmi_fru.… PS5, Line 63: } else else is not generally useful after a break or return -- To view, visit https://review.coreboot.org/c/coreboot/+/37444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8 Gerrit-Change-Number: 37444 Gerrit-PatchSet: 5 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Dec 2019 01:39:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: drivers/ipmi: Add IPMI Read FRU function
by Johnny Lin (Code Review) 05 Dec '19

05 Dec '19

Hello Andrey Petrov, Jingle Hsu, Morgan Jang, Patrick Rudolph, Jonathan Zhang, David Hendricks, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37444 to look at the new patch set (#5). Change subject: drivers/ipmi: Add IPMI Read FRU function ...................................................................... drivers/ipmi: Add IPMI Read FRU function Implemented according to IPMI "Platform Management FRU Information Storage Definition" specification v1.0 for reading FRU data Product Info Area and Board Info Area. SMBIOS data can be updated with the FRU data. Tested on OCP Mono Lake. Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/ipmi/Kconfig M src/drivers/ipmi/Makefile.inc A src/drivers/ipmi/ipmi_fru.c M src/drivers/ipmi/ipmi_kcs.h M src/drivers/ipmi/ipmi_ops.h 5 files changed, 491 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/37444/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/37444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8 Gerrit-Change-Number: 37444 Gerrit-PatchSet: 5 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Support reset vector in romstage
by Marshall Dawson (Code Review) 05 Dec '19

05 Dec '19

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33759 ) Change subject: soc/amd/picasso: Support reset vector in romstage ...................................................................... Patch Set 17: (5 comments) https://review.coreboot.org/c/coreboot/+/33759/13//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/33759/13//COMMIT_MSG@22 PS13, Line 22: Remove all postcar support. > > At first appearance >50% of code line changes is about MTRRs and not about the entry to romstage l […] Ack https://review.coreboot.org/c/coreboot/+/33759/16/src/soc/amd/picasso/inclu… File src/soc/amd/picasso/include/soc/romstage.h: https://review.coreboot.org/c/coreboot/+/33759/16/src/soc/amd/picasso/inclu… PS16, Line 21: #include <arch/cpu.h> > Is this needed here for the function definitions? Done. Looks like PS12 used asmlinkage but it's no longer necessary. https://review.coreboot.org/c/coreboot/+/33759/16/src/soc/amd/picasso/romst… File src/soc/amd/picasso/romstage.c: https://review.coreboot.org/c/coreboot/+/33759/16/src/soc/amd/picasso/romst… PS16, Line 53: : static void romstage_soc_init(int s3_resume) : { : fch_early_init(); : } > Call it directly? Is the intention to make the first_stage_entry() an architectural default with cal […] Redone https://review.coreboot.org/c/coreboot/+/33759/16/src/soc/amd/picasso/romst… PS16, Line 100: BIT(23) > 8 * MiB would be more readable Done. It was primarily to reflect that only 47:23 are valid, and not a relevant size. 22:0 are supposed to be RAZ, but the align_down is simply to be safe about it. https://review.coreboot.org/c/coreboot/+/33759/16/src/soc/amd/picasso/romst… PS16, Line 101: backup_top_of_low_cacheable(top_of_mem); > Is using this API really necessary if it's fetched from just one MSR? Note CB:36144 where you only n […] This is only a temporary solution to demonstrate a somewhat simple romstage implementation. The real one relies on AGESA's reporting (due to UMA memory may fall below TOM), and is implemented in CB:34423. -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 17 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 05 Dec 2019 00:39:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Support reset vector in romstage
by Marshall Dawson (Code Review) 05 Dec '19

05 Dec '19

Hello Edward O'Callaghan, Julius Werner, Arthur Heymans, Richard Spiegel, build bot (Jenkins), Martin Roth, Furquan Shaikh, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33759 to look at the new patch set (#17). Change subject: soc/amd/picasso: Support reset vector in romstage ...................................................................... soc/amd/picasso: Support reset vector in romstage Given that: * Picasso comes out of reset with DRAM already functioning * The traditional requirements of bootblock and romstage are now somewhat minimized * The Google vboot solution will run on the PSP and not in a separate verstage after bootblock Add support for a hybrid romstage combining a handful of features typically in bootblock with the memory discovery in romstage. Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/include/soc/romstage.h M src/soc/amd/picasso/romstage.c 4 files changed, 48 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/33759/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 17 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/tglrvp: Do initial mainboard commit
by Wonkyu Kim (Code Review) 05 Dec '19

05 Dec '19

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36091 ) Change subject: mb/intel/tglrvp: Do initial mainboard commit ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/36091/10/src/mainboard/intel/tglrv… File src/mainboard/intel/tglrvp/Kconfig.name: https://review.coreboot.org/c/coreboot/+/36091/10/src/mainboard/intel/tglrv… PS10, Line 3: BOARD_INTEL_TGLRVP Can we have more specific board name for supporting other board? It's better have UP3 in config name -- To view, visit https://review.coreboot.org/c/coreboot/+/36091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a05881d2ea50ff4113243bf5ae26207db63322 Gerrit-Change-Number: 36091 Gerrit-PatchSet: 10 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 04 Dec 2019 23:38:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mmio: Add clrsetbitsXX() API in place of updateX()
by Julius Werner (Code Review) 04 Dec '19

04 Dec '19

Hello Hung-Te Lin, Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37432 to review the following change. Change subject: mmio: Add clrsetbitsXX() API in place of updateX() ...................................................................... mmio: Add clrsetbitsXX() API in place of updateX() This patch removes the recently added update8/16/32/64() API and replaces it with clrsetbits8/16/32/64(). This is more in line with the existing endian-specific clrsetbits_le16/32/64() functions that have been used for this task on some platforms already. Rename clrsetbits_8() to clrsetbits8() to be in line with the new naming. Keep this stuff in <device/mmio.h> and get rid of <mmio.h> again because having both is confusing and we seem to have been standardizing on <device/mmio.h> as the standard arch-independent header that all platforms should include already. Also sync libpayload back up with what we have in coreboot. (I'm the original author of the clrsetbits_le32-definitions so I'm relicensing them to BSD here.) Change-Id: Ie4f7b9fdbdf9e8c0174427b4288f79006d56978b Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/include/endian.h M src/drivers/maxim/max77686/max77686.c M src/include/device/mmio.h M src/include/endian.h D src/include/mmio.h 5 files changed, 62 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37432/1 diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index b387e66..ec0825d 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -181,18 +181,47 @@ /* Handy bit manipulation macros */ -#define clrsetbits_le32(addr, clear, set) writel(htole32((le32toh(readl(addr)) \ - & ~(clear)) | (set)), (addr)) -#define setbits_le32(addr, set) writel(htole32(le32toh(readl(addr)) \ - | (set)), (addr)) -#define clrbits_le32(addr, clear) writel(htole32(le32toh(readl(addr)) \ - & ~(clear)), (addr)) +#define __clrsetbits(endian, bits, addr, clear, set) \ + write##bits(addr, hto##endian##bits((endian##bits##toh( \ + read##bits(addr)) & ~((uint##bits##_t)(clear))) | (set))) -#define clrsetbits_be32(addr, clear, set) writel(htobe32((be32toh(readl(addr)) \ - & ~(clear)) | (set)), (addr)) -#define setbits_be32(addr, set) writel(htobe32(be32toh(readl(addr)) \ - | (set)), (addr)) -#define clrbits_be32(addr, clear) writel(htobe32(be32toh(readl(addr)) \ - & ~(clear)), (addr)) +#define clrbits_le64(addr, clear) __clrsetbits(le, 64, addr, clear, 0) +#define clrbits_be64(addr, clear) __clrsetbits(be, 64, addr, clear, 0) +#define clrbits_le32(addr, clear) __clrsetbits(le, 32, addr, clear, 0) +#define clrbits_be32(addr, clear) __clrsetbits(be, 32, addr, clear, 0) +#define clrbits_le16(addr, clear) __clrsetbits(le, 16, addr, clear, 0) +#define clrbits_be16(addr, clear) __clrsetbits(be, 16, addr, clear, 0) + +#define setbits_le64(addr, set) __clrsetbits(le, 64, addr, 0, set) +#define setbits_be64(addr, set) __clrsetbits(be, 64, addr, 0, set) +#define setbits_le32(addr, set) __clrsetbits(le, 32, addr, 0, set) +#define setbits_be32(addr, set) __clrsetbits(be, 32, addr, 0, set) +#define setbits_le16(addr, set) __clrsetbits(le, 16, addr, 0, set) +#define setbits_be16(addr, set) __clrsetbits(be, 16, addr, 0, set) + +#define clrsetbits_le64(addr, clear, set) __clrsetbits(le, 64, addr, clear, set) +#define clrsetbits_be64(addr, clear, set) __clrsetbits(be, 64, addr, clear, set) +#define clrsetbits_le32(addr, clear, set) __clrsetbits(le, 32, addr, clear, set) +#define clrsetbits_be32(addr, clear, set) __clrsetbits(be, 32, addr, clear, set) +#define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set) +#define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set) + +#define __clrsetbits_impl(bits, addr, clear, set) write##bits(addr, \ + (read##bits(addr) & ~((uint##bits##_t)(clear))) | (set)) + +#define clrsetbits8(addr, clear, set) __clrsetbits_impl(8, addr, clear, set) +#define clrsetbits16(addr, clear, set) __clrsetbits_impl(16, addr, clear, set) +#define clrsetbits32(addr, clear, set) __clrsetbits_impl(32, addr, clear, set) +#define clrsetbits64(addr, clear, set) __clrsetbits_impl(64, addr, clear, set) + +#define setbits8(addr, set) clrsetbits8(addr, 0, set) +#define setbits16(addr, set) clrsetbits16(addr, 0, set) +#define setbits32(addr, set) clrsetbits32(addr, 0, set) +#define setbits64(addr, set) clrsetbits64(addr, 0, set) + +#define clrbits8(addr, clear) clrsetbits8(addr, clear, 0) +#define clrbits16(addr, clear) clrsetbits16(addr, clear, 0) +#define clrbits32(addr, clear) clrsetbits32(addr, clear, 0) +#define clrbits64(addr, clear) clrsetbits64(addr, clear, 0) #endif /* _ENDIAN_H_ */ diff --git a/src/drivers/maxim/max77686/max77686.c b/src/drivers/maxim/max77686/max77686.c index 54e3a6c..cfbf912 100644 --- a/src/drivers/maxim/max77686/max77686.c +++ b/src/drivers/maxim/max77686/max77686.c @@ -127,10 +127,10 @@ } if (enable == REG_DISABLE) { - clrbits_8(&read_data, + clrbits8(&read_data, pmic->reg_enbitmask << pmic->reg_enbitpos); } else { - clrsetbits_8(&read_data, + clrsetbits8(&read_data, pmic->reg_enbitmask << pmic->reg_enbitpos, pmic->reg_enbiton << pmic->reg_enbitpos); } @@ -177,7 +177,7 @@ } vol_level /= (u32)pmic->vol_div; - clrsetbits_8(&read_data, pmic->vol_bitmask << pmic->vol_bitpos, + clrsetbits8(&read_data, pmic->vol_bitmask << pmic->vol_bitpos, vol_level << pmic->vol_bitpos); ret = max77686_i2c_write(bus, MAX77686_I2C_ADDR, pmic->vol_addr, read_data); diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index 6596cf8..9c5e27c 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -19,6 +19,24 @@ #include <endian.h> #include <types.h> +#define __clrsetbits_impl(bits, addr, clear, set) write##bits(addr, \ + (read##bits(addr) & ~((uint##bits##_t)(clear))) | (set)) + +#define clrsetbits8(addr, clear, set) __clrsetbits_impl(8, addr, clear, set) +#define clrsetbits16(addr, clear, set) __clrsetbits_impl(16, addr, clear, set) +#define clrsetbits32(addr, clear, set) __clrsetbits_impl(32, addr, clear, set) +#define clrsetbits64(addr, clear, set) __clrsetbits_impl(64, addr, clear, set) + +#define setbits8(addr, set) clrsetbits8(addr, 0, set) +#define setbits16(addr, set) clrsetbits16(addr, 0, set) +#define setbits32(addr, set) clrsetbits32(addr, 0, set) +#define setbits64(addr, set) clrsetbits64(addr, 0, set) + +#define clrbits8(addr, clear) clrsetbits8(addr, clear, 0) +#define clrbits16(addr, clear) clrsetbits16(addr, clear, 0) +#define clrbits32(addr, clear) clrsetbits32(addr, clear, 0) +#define clrbits64(addr, clear) clrsetbits64(addr, clear, 0) + #ifndef __ROMCC__ /* * Reads a transfer buffer from 32-bit FIFO registers. fifo_stride is the diff --git a/src/include/endian.h b/src/include/endian.h index 8dc1854..f16f668 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -79,11 +79,6 @@ #define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set) #define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set) -#define clrsetbits_8(addr, clear, set) \ - write8(addr, (read8(addr) & ~(clear)) | (set)) -#define clrbits_8(addr, clear) clrsetbits_8(addr, clear, 0) -#define setbits_8(addr, set) setbits_8(addr, 0, set) - #ifndef __ROMCC__ /* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */ #define DEFINE_ENDIAN_DEC(endian, width) \ diff --git a/src/include/mmio.h b/src/include/mmio.h deleted file mode 100644 index 4f2c806..0000000 --- a/src/include/mmio.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * mmio.h provides update*() as well as read/write*() from arch/mmio.h - */ - -#ifndef __MMIO_H__ -#define __MMIO_H__ - -#include <arch/mmio.h> -#include <stdint.h> - -static __always_inline void update8(volatile void *addr, uint8_t mask, uint8_t or) -{ - uint8_t reg = read8(addr); - reg = (reg & mask) | or; - write8(addr, reg); -} - -static __always_inline void update16(volatile void *addr, uint16_t mask, uint16_t or) -{ - uint16_t reg = read16(addr); - reg = (reg & mask) | or; - write16(addr, reg); -} - -static __always_inline void update32(volatile void *addr, uint32_t mask, uint32_t or) -{ - uint32_t reg = read32(addr); - reg = (reg & mask) | or; - write32(addr, reg); -} - -#endif /* __MMIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4f7b9fdbdf9e8c0174427b4288f79006d56978b Gerrit-Change-Number: 37432 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: facebook/fbg1701: Increase bootblock size
by Julius Werner (Code Review) 04 Dec '19

04 Dec '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37475 ) Change subject: facebook/fbg1701: Increase bootblock size ...................................................................... facebook/fbg1701: Increase bootblock size New vboot updates make the bootblock no longer fit on this board. Increasing the size should fix the issue. Change-Id: Ic18d682a8370ebf7e27e1e6bcfcf019643fc31f3 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M configs/config.facebook_fbg1701 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/37475/1 diff --git a/configs/config.facebook_fbg1701 b/configs/config.facebook_fbg1701 index b372bbe..e0a7271 100644 --- a/configs/config.facebook_fbg1701 +++ b/configs/config.facebook_fbg1701 @@ -1,5 +1,5 @@ CONFIG_VENDOR_FACEBOOK=y -CONFIG_C_ENV_BOOTBLOCK_SIZE=0x6000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x7000 CONFIG_ONBOARD_SAMSUNG_MEM=y CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y -- To view, visit https://review.coreboot.org/c/coreboot/+/37475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic18d682a8370ebf7e27e1e6bcfcf019643fc31f3 Gerrit-Change-Number: 37475 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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