coreboot-gerrit December 2019

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Change in coreboot[4.11_branch]: mainboard/facebook/watson: Reclaim unused flash space
by Andrey Petrov (Code Review) 04 Dec '19

04 Dec '19

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37474 ) Change subject: mainboard/facebook/watson: Reclaim unused flash space ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/37474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I5f407c11031822d58f11f1a4684845d57653b190 Gerrit-Change-Number: 37474 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 04 Dec 2019 21:42:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: [BACKPORT] arch/x86: SMBIOS: Improve core count reporting
by build bot (Jenkins) (Code Review) 04 Dec '19

04 Dec '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37089 ) Change subject: [BACKPORT] arch/x86: SMBIOS: Improve core count reporting ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/37089/1/src/arch/x86/smbios.c File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/37089/1/src/arch/x86/smbios.c@673 PS1, Line 673: if (leaf_b_threads == 0) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/37089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Gerrit-Change-Number: 37089 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Dec 2019 21:37:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Patrick Georgi (Code Review) 04 Dec '19

04 Dec '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: > Patch Set 4: > > btw. this is open since one month. All that Intel people were able to come up with was "no, this must stay. it's needed." \o/ Calm down, please :-) I started looking at the other changes and they're looking reasonable. If they don't regress the non-BG case, they should be a good starting point at least for BG enablement, so we can hold onto the end-of-december deadline. -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Vincent Zimmer <vincent.zimmer(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Dec 2019 20:55:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: WIP: disable gpio gating
by Mathew King (Code Review) 04 Dec '19

04 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37253 ) Change subject: WIP: disable gpio gating ...................................................................... WIP: disable gpio gating Change-Id: I08be8e9db0e4c0c70e5adaf99e48bd76664150e0 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 5 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37253/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index ed44f4f..1ecd3f5 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -207,15 +207,11 @@ register "gpio_override_pm" = "1" # GPIO community PM configuration - register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | - MISCCFG_GPRTCDLCGEN | - MISCCFG_GSXSLCGEN | - MISCCFG_GPDPCGEN | - MISCCFG_GPDLCGEN" - register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" device cpu_cluster 0 on device lapic 0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/37253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08be8e9db0e4c0c70e5adaf99e48bd76664150e0 Gerrit-Change-Number: 37253 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron/986lcd-m: Fix unresolved inclusion
by HAOUAS Elyes (Code Review) 04 Dec '19

04 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37469 ) Change subject: mb/kontron/986lcd-m: Fix unresolved inclusion ...................................................................... mb/kontron/986lcd-m: Fix unresolved inclusion Change-Id: I633a5d8c50eb5b2b96524d8ea8fcae77e11cd418 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/kontron/986lcd-m/early_init.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/37469/1 diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index 31cb209..fdfcc4b 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -23,8 +23,6 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> -#include "option_table.h" - #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) /* Override the default lpc decode ranges */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I633a5d8c50eb5b2b96524d8ea8fcae77e11cd418 Gerrit-Change-Number: 37469 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Michael Niewöhner (Code Review) 04 Dec '19

04 Dec '19

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Michael Niewöhner (Code Review) 04 Dec '19

04 Dec '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: > So, I think that getting CB:36682 boot-tested and merged in will be good for everyone. If so, what are we waiting for? Even though I'm sure this is meant rhetorical, let me answer that question: We are waiting for Intel to a) test the CB or b) provide a way for us to test it. > Since Bootguard requires firmware to be signed, and the signing key is kept secret, running a random coreboot image on a commercially available board with Bootguard is just not possible. It's not impossible, as there are unfused boards available. I have one for example. The problem is, there is no way for non-Intel-NDAed people to get access to the required manifest generation tool.... Nico mentioned this discussion came up a year ago. Some people complained (just like this time) but could not bring up valid arguments to keep FSP-T. My feeling is they try to sit that out. My suggestion? Let's agree on a deadline (like Arthur already suggested). Then merge it. When there was no BG testing and nor reaction? Bad luck. They had a chance. -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Dec 2019 19:07:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: soc/intel/broadwell_de: Re-read SPD on CRC error
by Andrey Petrov (Code Review) 04 Dec '19

04 Dec '19

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37303 ) Change subject: soc/intel/broadwell_de: Re-read SPD on CRC error ...................................................................... Patch Set 3: (5 comments) https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/romstage/memory.c: https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… PS2, Line 58: = SPD_STATUS_OK > This is not strictly needed here because res will be assigned a value in line 65 and noone needs it […] Ack https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… PS2, Line 68: "SPD CRC error, channel %u slot %u\n", > Please add the iteration. Ack https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… PS2, Line 72: } while (tries-- && res == SPD_STATUS_CRC_ERROR); > How much time does each try add to the boot time? Could you time it using the stopwatch frame work […] the re-read seem to take around 60ms. But since it is a relatively rare occurrence we should be ok https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… PS2, Line 74: if (res == SPD_STATUS_OK) { > braces {} are not necessary for single statement blocks Ack https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… PS2, Line 76: } > Please print an error with error string, stating that the SMBIOS data is not added, but it should st […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/37303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Gerrit-Change-Number: 37303 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 04 Dec 2019 18:50:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: soc/intel/broadwell_de: Re-read SPD on CRC error
by build bot (Jenkins) (Code Review) 04 Dec '19

04 Dec '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37303 ) Change subject: soc/intel/broadwell_de: Re-read SPD on CRC error ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/37303/3/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/romstage/memory.c: https://review.coreboot.org/c/coreboot/+/37303/3/src/soc/intel/fsp_broadwel… PS3, Line 82: if (res == SPD_STATUS_OK) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/37303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Gerrit-Change-Number: 37303 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 04 Dec 2019 18:49:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: soc/intel/broadwell_de: Re-read SPD on CRC error
by Andrey Petrov (Code Review) 04 Dec '19

04 Dec '19

Hello Werner Zeh, Patrick Rudolph, David Hendricks, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37303 to look at the new patch set (#3). Change subject: soc/intel/broadwell_de: Re-read SPD on CRC error ...................................................................... soc/intel/broadwell_de: Re-read SPD on CRC error I2C bus does not guarantee data integrity. As result, sometimes we end up detecting CRC errors and not adding DIMMs to SMBIOS tables. This change adds re-tries on such errors. TEST=let OCP monolake run without fan and try reading SPD data in tight loop. CRC errors were reported but subsequent retries were error free. Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/soc/intel/fsp_broadwell_de/romstage/memory.c 1 file changed, 29 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/37303/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/37303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Gerrit-Change-Number: 37303 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2019