coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

1 participants
1761 discussions

Change in coreboot[master]: mb/google/kohaku: Adjust I2C clock frequency
by shkim (Code Review) 04 Dec '19

04 Dec '19

Hello Seunghwan Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37313 to review the following change. Change subject: mb/google/kohaku: Adjust I2C clock frequency ...................................................................... mb/google/kohaku: Adjust I2C clock frequency This change adjusts I2C speed settings to limit frequency to 400KHz. The new setting values have been from other projects using same I2C components. BUG=b:144885961 BRANCH=firmware-hatch-12672.B TEST=Verified I2C1 and I2C4 frequency not over 400KHz Change-Id: I9614fb39b6e55cb2ce1b0879a9f5204e55002f8d Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37313/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 55ac071..d515ecc 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -60,6 +60,8 @@ }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, }, .i2c[2] = { .speed = I2C_SPEED_FAST, @@ -68,8 +70,8 @@ }, .i2c[4] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 100, - .fall_time_ns = 20, + .rise_time_ns = 104, + .fall_time_ns = 52, }, .gspi[0] = { .speed_mhz = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/37313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9614fb39b6e55cb2ce1b0879a9f5204e55002f8d Gerrit-Change-Number: 37313 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb/google/hatch/var/akemi: tune DPTF for Akemi
by Peichao Li (Code Review) 04 Dec '19

04 Dec '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36716 ) Change subject: mb/google/hatch/var/akemi: tune DPTF for Akemi ...................................................................... mb/google/hatch/var/akemi: tune DPTF for Akemi Need tune DPTF insure it meets Lenovo DPTF Spec BUG=b:144195069 TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Change-Id: Ie0e6d93e1fc0c684e067d1450eb119a53cfefaed --- M src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/36716/1 diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl index bb46fe9..3b5f2aa 100644 --- a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl @@ -44,7 +44,7 @@ #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - CPU" #define DPTF_TSR2_PASSIVE 60 -#define DPTF_TSR2_CRITICAL 75 +#define DPTF_TSR2_CRITICAL 105 #define DPTF_TSR2_ACTIVE_AC0 51 #define DPTF_TSR2_ACTIVE_AC1 48 #define DPTF_TSR2_ACTIVE_AC2 45 @@ -129,7 +129,7 @@ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 3000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ + 12000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 32000, /* TimeWindowMaximum */ 200 /* StepSize */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0e6d93e1fc0c684e067d1450eb119a53cfefaed Gerrit-Change-Number: 36716 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

7 31

Change in coreboot[master]: soc/intel/common: Add Jasperlake Device IDs
by Paul Menzel (Code Review) 04 Dec '19

04 Dec '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37434 ) Change subject: soc/intel/common: Add Jasperlake Device IDs ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/37434/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37434/5//COMMIT_MSG@7 PS5, Line 7: Jasperlake The typo was reintroduced. Jasper Lake -- To view, visit https://review.coreboot.org/c/coreboot/+/37434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117 Gerrit-Change-Number: 37434 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 04 Dec 2019 12:44:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: AGESA: Reduce S3_DATA_SIZE
by Kyösti Mälkki (Code Review) 04 Dec '19

04 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37439 ) Change subject: AGESA: Reduce S3_DATA_SIZE ...................................................................... AGESA: Reduce S3_DATA_SIZE Make some room for C environment bootblock. The S3 resume feature needs less than 2 KiB. Change-Id: Ic49c313d492f1d18f59d61e84f81f106e3b41fb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/37439/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index e97f147..9bd4bf1 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -63,7 +63,7 @@ config S3_DATA_SIZE int - default 32768 + default 8192 config C_ENV_BOOTBLOCK_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/37439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic49c313d492f1d18f59d61e84f81f106e3b41fb1 Gerrit-Change-Number: 37439 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: amdblocks/acpimmio: add common functions for AP entry
by Michał Żygowski (Code Review) 04 Dec '19

04 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37416 ) Change subject: amdblocks/acpimmio: add common functions for AP entry ...................................................................... amdblocks/acpimmio: add common functions for AP entry Move the stoneyridge implementation of get/set AP entry to the common block. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I9c73940ffe5f735dcd844911361355c384f617b1 --- M src/soc/amd/common/block/acpimmio/biosram.c M src/soc/amd/common/block/include/amdblocks/biosram.h M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/include/soc/northbridge.h D src/soc/amd/stoneyridge/nb_util.c M src/soc/amd/stoneyridge/romstage.c 7 files changed, 18 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/37416/1 diff --git a/src/soc/amd/common/block/acpimmio/biosram.c b/src/soc/amd/common/block/acpimmio/biosram.c index f0a1257..e33f02d 100644 --- a/src/soc/amd/common/block/acpimmio/biosram.c +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -15,6 +15,17 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/biosram.h> +void *get_ap_entry_ptr(void) +{ + return (void *)biosram_read32(BIOSRAM_AP_ENTRY); +} + +void set_ap_entry_ptr(void *entry) +{ + biosram_write32(BIOSRAM_AP_ENTRY, (uintptr_t)entry); +} + + void backup_top_of_low_cacheable(uintptr_t ramtop) { biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index e2c1eb3..db28310 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -17,10 +17,15 @@ #include <stdint.h> /* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_AP_ENTRY 0xe8 /* 8 bytes */ #define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ +/* Returns the bootblock C entry point for APs */ +void *get_ap_entry_ptr(void); +/* Used by BSP to store the bootblock entry point for APs */ +void set_ap_entry_ptr(void *entry); /* Saves the UMA size returned by AGESA */ void save_uma_size(uint32_t size); /* Saves the UMA base address returned by AGESA */ diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index f697fc2..1879e31 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -48,7 +48,6 @@ bootblock-y += reset.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c -bootblock-y += nb_util.c bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += BiosCallOuts.c @@ -65,7 +64,6 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c -romstage-y += nb_util.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c verstage-y += gpio.c @@ -75,12 +73,10 @@ verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c -verstage-y += nb_util.c postcar-y += monotonic_timer.c postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c postcar-y += memmap.c -postcar-y += nb_util.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c @@ -107,14 +103,12 @@ ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c -ramstage-y += nb_util.c smm-y += monotonic_timer.c smm-y += smihandler.c smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c -smm-y += nb_util.c smm-y += gpio.c CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index a079ec2..d92535a 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -24,9 +24,9 @@ #include <bootblock_common.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> +#include <amdblocks/biosram.h> #include <soc/pci_devs.h> #include <soc/cpu.h> -#include <soc/northbridge.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> #include <timestamp.h> diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index a0d7ce8..5694779 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -40,8 +40,6 @@ #define NB_IOAPIC_SCRATCH0 0x3e #define NB_IOAPIC_SCRATCH1 0x3f -#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0 - /* D1F1 - HDA Configuration Registers */ #define HDA_DEV_CTRL_STATUS 0x60 #define HDA_NO_SNOOP_EN BIT(11) @@ -102,10 +100,6 @@ void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); -uint32_t nb_ioapic_read(unsigned int index); -void nb_ioapic_write(unsigned int index, uint32_t value); -void *get_ap_entry_ptr(void); -void set_ap_entry_ptr(void *entry); void set_warm_reset_flag(void); int is_warm_reset(void); diff --git a/src/soc/amd/stoneyridge/nb_util.c b/src/soc/amd/stoneyridge/nb_util.c deleted file mode 100644 index d5de067..0000000 --- a/src/soc/amd/stoneyridge/nb_util.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Advanced Micro Devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/northbridge.h> -#include <soc/pci_devs.h> -#include <device/pci_ops.h> - -uint32_t nb_ioapic_read(unsigned int index) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA); -} - -void nb_ioapic_write(unsigned int index, uint32_t value) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value); -} - -void *get_ap_entry_ptr(void) -{ - return (void *)nb_ioapic_read(AP_SCRATCH_REG); -} - -void set_ap_entry_ptr(void *entry) -{ - nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry); -} diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 2228c1a..25eb4a1 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <amdblocks/biosram.h> #include <device/pci_ops.h> #include <arch/cpu.h> #include <arch/romstage.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c73940ffe5f735dcd844911361355c384f617b1 Gerrit-Change-Number: 37416 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/amd/common/blocks: introduce two new BIOSRAM based common blocks
by Michał Żygowski (Code Review) 04 Dec '19

04 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37402 ) Change subject: soc/amd/common/blocks: introduce two new BIOSRAM based common blocks ...................................................................... soc/amd/common/blocks: introduce two new BIOSRAM based common blocks All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size. Create unified BIOSRAM layout, AMD UMA block and AMD RAMTOP block. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da --- A src/soc/amd/common/block/include/amdblocks/biosram_layout.h A src/soc/amd/common/block/include/amdblocks/uma.h A src/soc/amd/common/block/ramtop/Kconfig A src/soc/amd/common/block/ramtop/Makefile.inc A src/soc/amd/common/block/ramtop/ramtop.c A src/soc/amd/common/block/uma/Kconfig A src/soc/amd/common/block/uma/Makefile.inc A src/soc/amd/common/block/uma/uma.c 8 files changed, 136 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/37402/1 diff --git a/src/soc/amd/common/block/include/amdblocks/biosram_layout.h b/src/soc/amd/common/block/include/amdblocks/biosram_layout.h new file mode 100644 index 0000000..2ca4f74 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/biosram_layout.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_BIOSRAM_H__ +#define __AMDBLOCKS_BIOSRAM_H__ + +/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ +#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ +#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ + +#endif diff --git a/src/soc/amd/common/block/include/amdblocks/uma.h b/src/soc/amd/common/block/include/amdblocks/uma.h new file mode 100644 index 0000000..939713d --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/uma.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_UMA_H__ +#define __AMDBLOCKS_UMA_H__ + +/* Saves the UMA size returned by AGESA */ +void save_uma_size(uint32_t size); +/* Saves the UMA base address returned by AGESA */ +void save_uma_base(uint64_t base); +/* Returns the saved UMA size */ +uint32_t get_uma_size(void); +/* Returns the saved UMA base */ +uint64_t get_uma_base(void); + +#endif diff --git a/src/soc/amd/common/block/ramtop/Kconfig b/src/soc/amd/common/block/ramtop/Kconfig new file mode 100644 index 0000000..36bf074 --- /dev/null +++ b/src/soc/amd/common/block/ramtop/Kconfig @@ -0,0 +1,7 @@ +config SOC_AMD_COMMON_BLOCK_RAMTOP + bool + default n + depends on SOC_AMD_COMMON_BLOCK_ACPIMMIO + help + Select this option to enable common cbmem top save and restore + functions usign BIOSRAM. diff --git a/src/soc/amd/common/block/ramtop/Makefile.inc b/src/soc/amd/common/block/ramtop/Makefile.inc new file mode 100644 index 0000000..bb2d290 --- /dev/null +++ b/src/soc/amd/common/block/ramtop/Makefile.inc @@ -0,0 +1,3 @@ +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RAMTOP) += ramtop.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_RAMTOP) += ramtop.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RAMTOP) += ramtop.c diff --git a/src/soc/amd/common/block/ramtop/ramtop.c b/src/soc/amd/common/block/ramtop/ramtop.c new file mode 100644 index 0000000..ae93537 --- /dev/null +++ b/src/soc/amd/common/block/ramtop/ramtop.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <cbmem.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/biosram_layout.h> + +void backup_top_of_low_cacheable(uintptr_t ramtop) +{ + biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); +} + +uintptr_t restore_top_of_low_cacheable(void) +{ + return biosram_read32(BIOSRAM_CBMEM_TOP); +} diff --git a/src/soc/amd/common/block/uma/Kconfig b/src/soc/amd/common/block/uma/Kconfig new file mode 100644 index 0000000..8b0e18a --- /dev/null +++ b/src/soc/amd/common/block/uma/Kconfig @@ -0,0 +1,7 @@ +config SOC_AMD_COMMON_BLOCK_UMA + bool + default n + depends on SOC_AMD_COMMON_BLOCK_ACPIMMIO + help + Select this option to enable common UMA parameters save and + restore functions using BIOSRAM. diff --git a/src/soc/amd/common/block/uma/Makefile.inc b/src/soc/amd/common/block/uma/Makefile.inc new file mode 100644 index 0000000..b3bb8c6 --- /dev/null +++ b/src/soc/amd/common/block/uma/Makefile.inc @@ -0,0 +1,3 @@ +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UMA) += uma.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_UMA) += uma.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UMA) += uma.c diff --git a/src/soc/amd/common/block/uma/uma.c b/src/soc/amd/common/block/uma/uma.c new file mode 100644 index 0000000..00b4642 --- /dev/null +++ b/src/soc/amd/common/block/uma/uma.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/biosram_layout.h> +#include <amdblocks/uma.h> + +void save_uma_size(uint32_t size) +{ + biosram_write32(BIOSRAM_UMA_SIZE, size); +} + +void save_uma_base(uint64_t base) +{ + biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); + biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); +} + +uint32_t get_uma_size(void) +{ + return biosram_read32(BIOSRAM_UMA_SIZE); +} + +uint64_t get_uma_base(void) +{ + uint64_t base; + base = biosram_read32(BIOSRAM_UMA_BASE); + base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); + return base; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da Gerrit-Change-Number: 37402 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: soc/amd/common/block/acpimmio: fix the ACPIMMIO decode enable function
by Michał Żygowski (Code Review) 04 Dec '19

04 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37178 ) Change subject: soc/amd/common/block/acpimmio: fix the ACPIMMIO decode enable function ...................................................................... soc/amd/common/block/acpimmio: fix the ACPIMMIO decode enable function According to BKDG's for families 15h and 16h the ACPI MMIO decode enable bit is the second LSB not the first LSB. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Iaa31abc3dbdf77d8513fa83c7415b9a1b7fd266f --- M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/37178/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 755af52..d636432 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -28,7 +28,8 @@ * newer method. */ #define ACPIMMIO_DECODE_REGISTER 0x4 -#define ACPIMMIO_DECODE_EN BIT(0) +#define BIOSRAM_DECODE_EN BIT(0) +#define ACPIMMIO_DECODE_EN BIT(1) /* MMIO register blocks are at fixed offsets from 0xfed80000 and are enabled * in PMx24[1] (older implementations) and PMx04[1] (newer implementations). -- To view, visit https://review.coreboot.org/c/coreboot/+/37178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa31abc3dbdf77d8513fa83c7415b9a1b7fd266f Gerrit-Change-Number: 37178 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: binaryPI: Fix failing AP startup
by Kyösti Mälkki (Code Review) 04 Dec '19

04 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37438 ) Change subject: binaryPI: Fix failing AP startup ...................................................................... binaryPI: Fix failing AP startup Fix regression with commit 5639736 binaryPI: Drop CAR teardown without POSTCAR_STAGE Occassionally (maybe 1 boot in 10) SMP lapic_cpu_init() fails with following errors in the logs of pcengines/apu2: CPU 0x03 would not start! CPU 0x03 did not initialize! The CPU number is sometimes 0x02, never seen 0x01. Work-around also suggests something to do with cache coherency and MTRRs that is really at fault. As a work-around return the BSP CAR teardown to use wbinvd instead of invd. These platforms do not support S3 resume so this is the easy work-around for the time being. Change-Id: I3dac8785aaf4af5c7c105ec9dd0b95156b7cca21 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc M src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc M src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/37438/1 diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc index 4d903e6..cecf5ca 100644 --- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc @@ -904,7 +904,8 @@ btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - invd + # An invd here sometimes breaks AP CPU startup ? + wbinvd #.if (bh == 01h) || (bh == 03h) ; Is this TN or KV? cmp $01, %bh diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc index b208cc1..88e1a7d 100644 --- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc @@ -639,7 +639,8 @@ btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - invd + # An invd here sometimes breaks AP CPU startup ? + wbinvd # #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM? # cmp $01, %bh diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc index 7d86a31..c246b99 100644 --- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc @@ -603,7 +603,8 @@ btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - invd + # An invd here sometimes breaks AP CPU startup + wbinvd #Do Standard Family 16 work mov $HWCR, %ecx # MSR:C001_0015h -- To view, visit https://review.coreboot.org/c/coreboot/+/37438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3dac8785aaf4af5c7c105ec9dd0b95156b7cca21 Gerrit-Change-Number: 37438 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/common: Add Jasperlake Device IDs
by Ronak Kanabar (Code Review) 04 Dec '19

04 Dec '19

Hello Patrick Rudolph, Subrata Banik, Lean Sheng Tan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37434 to look at the new patch set (#5). Change subject: soc/intel/common: Add Jasperlake Device IDs ...................................................................... soc/intel/common: Add Jasperlake Device IDs Add Jasperlake SA and PCH IDs Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 18 files changed, 76 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/37434/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/37434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117 Gerrit-Change-Number: 37434 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common: Add Jasperlake Device IDs
by Ronak Kanabar (Code Review) 04 Dec '19

04 Dec '19

Hello Patrick Rudolph, Subrata Banik, Lean Sheng Tan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37434 to look at the new patch set (#4). Change subject: soc/intel/common: Add Jasperlake Device IDs ...................................................................... soc/intel/common: Add Jasperlake Device IDs Jasperlake CPU, SA and PCH IDs Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 20 files changed, 79 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/37434/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/37434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117 Gerrit-Change-Number: 37434 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2019