Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37220 )
Change subject: soc/amd/stoneyidge: Use USE_AMD_BLOBS to remove default paths
......................................................................
soc/amd/stoneyidge: Use USE_AMD_BLOBS to remove default paths
Remove default path/to/file strings when USE_AMD_BLOBS is not enabled.
This will result in a buildable, but not runable image, in the default
configuration.
Drop the check for HAVE_MERLINFALCON_BINARIES in the path default.
A later patch will address the poor use of this symbol
All PSP blobs are still assumed to be in the same directory as the AMD
public key. Qualify building the amdfw.rom intermediate image and
including it into coreboot.rom on whether the public key remains "".
This change infers it's OK to skip xHCI and GEC firmware too, although
the images normally reside in a separate directory.
This change only determines whether default paths and names exist.
Paths will be updated in a follow-on patch.
Change-Id: Ic21fbd7a58b340a9bcaaea456e1f38b567215b81
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
---
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/Makefile.inc
2 files changed, 20 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/37220/1
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index b55833d..c477e03 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -176,7 +176,8 @@
config VGA_BIOS_FILE
string
- default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if AMD_APU_MERLINFALCON && HAVE_MERLINFALCON_BINARIES
+ default "" if !USE_AMD_BLOBS
+ default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if AMD_APU_MERLINFALCON
default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin"
config S3_VGA_ROM_RUN
@@ -216,6 +217,7 @@
config STONEYRIDGE_XHCI_FWM_FILE
string "XHCI firmware path and filename"
+ default "" if !USE_AMD_BLOBS
default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin"
depends on STONEYRIDGE_XHCI_FWM
@@ -225,7 +227,8 @@
config AMD_PUBKEY_FILE
string "AMD public Key"
- default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON && HAVE_MERLINFALCON_BINARIES
+ default "" if !USE_AMD_BLOBS
+ default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON
default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin"
config STONEYRIDGE_SATA_MODE
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index f697fc2..d2d64c8 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -137,20 +137,15 @@
### 0
FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)))
+ifneq ($(FIRMWARE_LOCATE),)
ifeq ($(CONFIG_AMD_APU_STONEYRIDGE),y)
FIRMWARE_TYPE=ST
else
-
ifeq ($(CONFIG_AMD_APU_MERLINFALCON),y)
-# If Merlin Falcon, but blobs aren't present, use Stoney Ridge instead
-ifeq ($(CONFIG_HAVE_MERLINFALCON_BINARIES),y)
FIRMWARE_TYPE=CZ
else
-FIRMWARE_TYPE=ST
-endif # CONFIG_HAVE_MERLINFALCON_BINARIES
-else
-$(error stoneyridge: Unknown FIRMWARE_TYPE)
+$(error soc/amd/stoneyridge: Unusable FIRMWARE_TYPE)
endif # CONFIG_AMD_APU_MERLINFALCON
endif # CONFIG_AMD_APU_STONEYRIDGE
@@ -332,4 +327,17 @@
endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y)
+else # ifneq ($(FIRMWARE_LOCATE),)
+
+warn_no_amdfw:
+ printf "\n\t** WARNING **\n"
+ printf "coreboot has been built with no PSP firmware and "
+ printf "a non-booting image has been generated.\n\n"
+
+PHONY+=warn_no_amdfw
+
+files_added:: warn_no_amdfw
+
+endif # ifneq ($(FIRMWARE_LOCATE),)
+
endif # ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
--
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Gerrit-Change-Id: Ic21fbd7a58b340a9bcaaea456e1f38b567215b81
Gerrit-Change-Number: 37220
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37412 )
Change subject: soc/intel/common/cse: Update comment for post-CAR global world
......................................................................
soc/intel/common/cse: Update comment for post-CAR global world
Change-Id: I4ec9d7d3af1c4d7713ec5dfe516b24d110303ff1
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M src/soc/intel/common/block/cse/cse.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/37412/1
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 9921825..011916d 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -146,7 +146,7 @@
static uint32_t read_bar(uint32_t offset)
{
- /* Reach PCI config space to get BAR in case CAR global not available */
+ /* Load and cache BAR */
if (!cse.sec_bar)
cse.sec_bar = get_cse_bar();
return read32((void *)(cse.sec_bar + offset));
@@ -154,7 +154,7 @@
static void write_bar(uint32_t offset, uint32_t val)
{
- /* Reach PCI config space to get BAR in case CAR global not available */
+ /* Load and cache BAR */
if (!cse.sec_bar)
cse.sec_bar = get_cse_bar();
return write32((void *)(cse.sec_bar + offset), val);
--
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Christian Walter has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/34863 )
Change subject: src/mainboard/supermicro/x11sch: Initial Commit
......................................................................
Abandoned
NewCommitForProdrive
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36091 )
Change subject: mb/intel/tglrvp: Do initial mainboard commit
......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36091/10/src/mainboard/intel/tglrv…
File src/mainboard/intel/tglrvp/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/36091/10/src/mainboard/intel/tglrv…
PS10, Line 82: RP1
does it have 16 PCIe ports on PCH?
--
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Gerrit-Comment-Date: Tue, 03 Dec 2019 08:09:42 +0000
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Hello Srinidhi N Kaushik, Raj Astekar, Subrata Banik, Arthur Heymans, Wonkyu Kim, John Zhao, Shaunak Saha, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36091
to look at the new patch set (#10).
Change subject: mb/intel/tglrvp: Do initial mainboard commit
......................................................................
mb/intel/tglrvp: Do initial mainboard commit
1. Add tglrvp baseboard files
2. Add tglrvp UP3 variant board files
3. Add board id support
4. Add SPD memory support
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
Change-Id: I79a05881d2ea50ff4113243bf5ae26207db63322
---
A src/mainboard/intel/tglrvp/Kconfig
A src/mainboard/intel/tglrvp/Kconfig.name
A src/mainboard/intel/tglrvp/Makefile.inc
A src/mainboard/intel/tglrvp/acpi/mainboard.asl
A src/mainboard/intel/tglrvp/acpi/mipi_camera.asl
A src/mainboard/intel/tglrvp/acpi_tables.c
A src/mainboard/intel/tglrvp/board_id.c
A src/mainboard/intel/tglrvp/board_id.h
A src/mainboard/intel/tglrvp/board_info.txt
A src/mainboard/intel/tglrvp/bootblock.c
A src/mainboard/intel/tglrvp/chromeos.c
A src/mainboard/intel/tglrvp/chromeos.fmd
A src/mainboard/intel/tglrvp/dsdt.asl
A src/mainboard/intel/tglrvp/ec.c
A src/mainboard/intel/tglrvp/romstage.c
A src/mainboard/intel/tglrvp/smihandler.c
A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
A src/mainboard/intel/tglrvp/spd/Makefile.inc
A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex
A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex
A src/mainboard/intel/tglrvp/spd/spd.h
A src/mainboard/intel/tglrvp/variants/baseboard/Makefile.inc
A src/mainboard/intel/tglrvp/variants/baseboard/devicetree.cb
A src/mainboard/intel/tglrvp/variants/baseboard/gpio.c
A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h
A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h
A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
A src/mainboard/intel/tglrvp/variants/baseboard/mainboard.c
A src/mainboard/intel/tglrvp/variants/baseboard/memory.c
A src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc
A src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/ec.h
A src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/gpio.h
32 files changed, 2,086 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/36091/10
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