coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

1 participants
1761 discussions

Change in coreboot[master]: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
by Subrata Banik (Code Review) 03 Dec '19

03 Dec '19

Hello Patrick Rudolph, EricR Lai, Selma Bensaid, Bora Guvendik, build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37319 to look at the new patch set (#5). Change subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock ...................................................................... soc/intel/cannonlake: Configure GPIO PM configuration in bootblock This patch performs below operations: 1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration 2. Avoid redundent definitions of soc_fill_gpio_pm_configuration 3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration is updated with devicetree.cb value even with platform reset. BUG=b:144002424 TEST=coreboot disable all MISCCFG.bit 0-5 local clock gating. Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/chip.c A src/soc/intel/cannonlake/gpio_common.c M src/soc/intel/cannonlake/include/soc/gpio.h 5 files changed, 56 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37319/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: ACPI: Add SPCR table
by Name of user not set (Code Review) 03 Dec '19

03 Dec '19

greg(a)unrelenting.technology has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25344 ) Change subject: ACPI: Add SPCR table ...................................................................... Patch Set 6: This is very helpful for Skylake/KabyLake, which has a 32-bit memory-mapped UART: https://mail.coreboot.org/pipermail/coreboot/2016-October/082128.html just got FreeBSD to output kernel messages to the SuzyQable UART on my google/eve using this :) Had to neutralize the ENABLE_UART check though. That variable does not exist in my config. -- To view, visit https://review.coreboot.org/c/coreboot/+/25344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ff31da061c88a6f3e3cf76285f8ab78ee35509c Gerrit-Change-Number: 25344 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: greg(a)unrelenting.technology Gerrit-Comment-Date: Tue, 03 Dec 2019 01:22:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[4.11_branch]: soc/intel/broadwell_de: Re-read SPD on CRC error
by Andrey Petrov (Code Review) 02 Dec '19

02 Dec '19

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37303 ) Change subject: soc/intel/broadwell_de: Re-read SPD on CRC error ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/c/coreboot/+/37303/1/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/romstage/memory.c: https://review.coreboot.org/c/coreboot/+/37303/1/src/soc/intel/fsp_broadwel… PS1, Line 65: "SPD CRC error on channel %d slot %d, retrying..\n", > nit: ellipses usually have 3 dots Done https://review.coreboot.org/c/coreboot/+/37303/1/src/soc/intel/fsp_broadwel… PS1, Line 63: while (res == SPD_STATUS_CRC_ERROR && tries++ < MAX_SPD_READ_TRIES) { : printk(BIOS_ERR, : "SPD CRC error on channel %d slot %d, retrying..\n", : channel, slot); : get_spd_smbus(&blk); : res = spd_decode_ddr4(&dimm, spd_data); : } : if (res == SPD_STATUS_OK) { > How about using a do{}while loop here? […] thanks, I like the less DRY code idea https://review.coreboot.org/c/coreboot/+/37303/1/src/soc/intel/fsp_broadwel… PS1, Line 70: if (res == SPD_STATUS_OK) { > braces {} are not necessary for single statement blocks Done -- To view, visit https://review.coreboot.org/c/coreboot/+/37303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Gerrit-Change-Number: 37303 Gerrit-PatchSet: 2 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Dec 2019 23:53:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

1 0

Change in coreboot[4.11_branch]: soc/intel/broadwell_de: Re-read SPD on CRC error
by build bot (Jenkins) (Code Review) 02 Dec '19

02 Dec '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37303 ) Change subject: soc/intel/broadwell_de: Re-read SPD on CRC error ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/romstage/memory.c: https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… PS2, Line 74: if (res == SPD_STATUS_OK) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/37303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Gerrit-Change-Number: 37303 Gerrit-PatchSet: 2 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Dec 2019 23:52:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[4.11_branch]: soc/intel/broadwell_de: Re-read SPD on CRC error
by Andrey Petrov (Code Review) 02 Dec '19

02 Dec '19

Hello Werner Zeh, Patrick Rudolph, David Hendricks, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37303 to look at the new patch set (#2). Change subject: soc/intel/broadwell_de: Re-read SPD on CRC error ...................................................................... soc/intel/broadwell_de: Re-read SPD on CRC error I2C bus does not guarantee data integrity. As result, sometimes we end up detecting CRC errors and not adding DIMMs to SMBIOS tables. This change adds re-tries on such errors. TEST=let OCP monolake run without fan and try reading SPD data in tight loop. CRC errors were reported but subsequent retries were error free. Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/soc/intel/fsp_broadwell_de/romstage/memory.c 1 file changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/37303/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Gerrit-Change-Number: 37303 Gerrit-PatchSet: 2 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/g/drallion: Enable privacy screen on Drallion variant
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36045 ) Change subject: mb/g/drallion: Enable privacy screen on Drallion variant ...................................................................... mb/g/drallion: Enable privacy screen on Drallion variant Enable ACPI methods to control privacy screen on Drallion devices. Drallion devices may not have a privacy screen and it is up to the EC to determine if the privacy screen is present on the system. BUG=b:142656363 TEST=emerge-drallion coreboot chromeos-bootimage Change-Id: I79d02bb1b25f0deb49ae4bb852b7ed8c21fd31c7 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/include/variant/ec.h 4 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/36045/1 diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 256f8cb..1de5ea5 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_GFX if BOARD_GOOGLE_DRALLION select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_ISH diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 2568800..5c2a5c9 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -39,6 +39,7 @@ { #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> + #include <soc/intel/cannonlake/acpi/gfx.asl> } /* Per board variant mainboard hooks. */ #include <variant/acpi/mainboard.asl> diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 1f628d6..184ab63 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -222,7 +222,19 @@ end device domain 0 on device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device + device pci 02.0 on + chip drivers/generic/gfx + register "device_count" = "1" + register "device[0].name" = ""LCD"" + register "device[0].addr" = "0x0400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.detect_function" = ""\\_SB.PCI0.LPCB.EC0.GPVD"" + register "device[0].privacy.status_function" = ""\\_SB.PCI0.LPCB.EC0.GPVX"" + register "device[0].privacy.enable_function" = ""\\_SB.PCI0.LPCB.EC0.EPVX"" + register "device[0].privacy.disable_function" = ""\\_SB.PCI0.LPCB.EC0.DPVX"" + device generic 0 on end + end + end # Integrated Graphics Device device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h index 01a17b5..9cb8ed0 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h @@ -31,4 +31,7 @@ /* Enable DPTF */ #define EC_ENABLE_DPTF +/* Enable Privacy */ +#define EC_ENABLE_PRIVACY + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79d02bb1b25f0deb49ae4bb852b7ed8c21fd31c7 Gerrit-Change-Number: 36045 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

4 17

Change in coreboot[master]: ec/google/wilco: Add placeholder methods for privacy screen
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36044 ) Change subject: ec/google/wilco: Add placeholder methods for privacy screen ...................................................................... ec/google/wilco: Add placeholder methods for privacy screen Add placeholder ACPI methods to the Wilco EC for controlling a privacy screen on the device. These methods will be updteded when the EC has commands to control the screen. BUG=b:142237145, b:142656363 TEST=none Change-Id: Ic3c136f9d2de90eeb3c9e468e4c7430ccf6dcc42 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/ec/google/wilco/acpi/ec.asl A src/ec/google/wilco/acpi/privacy.asl 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/36044/1 diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 532f421..8fcd0dd 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -178,4 +178,7 @@ #ifdef EC_ENABLE_DPTF #include "dptf.asl" #endif +#ifdef EC_ENABLE_PRIVACY + #include "privacy.asl" +#endif } diff --git a/src/ec/google/wilco/acpi/privacy.asl b/src/ec/google/wilco/acpi/privacy.asl new file mode 100644 index 0000000..2121d23 --- /dev/null +++ b/src/ec/google/wilco/acpi/privacy.asl @@ -0,0 +1,25 @@ +/* Read Privacy Screen Present */ +Method (GPVD, 0, Serialized) +{ + Printf ("Read Privacy Screen Present") + Return (One) +} + +/* Read Privacy Screen Status */ +Method (GPVX, 0, Serialized) +{ + Printf ("Read Privacy Screen Status") + Return (0x0) +} + +/* Enable Privacy Screen */ +Method (EPVX, 0, Serialized) +{ + Printf ("Enable Privacy Screen") +} + +/* Disable Privacy Screen */ +Method (DPVX, 0, Serialized) +{ + Printf ("Disable Privacy Screen") +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/36044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3c136f9d2de90eeb3c9e468e4c7430ccf6dcc42 Gerrit-Change-Number: 36044 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: soc/intel/cannonlake: Add gfx.asl file
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36043 ) Change subject: soc/intel/cannonlake: Add gfx.asl file ...................................................................... soc/intel/cannonlake: Add gfx.asl file Add gfx.asl file for cannonlake SOCs to allow for graphics related ACPI devices and methods on cannonlake devices. BUG=b:142237145 TEST=gfx.asl added to drallion dsdt.asl Change-Id: I38a26f3135d571e2f9b63840d38fd4d3476fc142 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- A src/soc/intel/cannonlake/acpi/gfx.asl 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/36043/1 diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/soc/intel/cannonlake/acpi/gfx.asl new file mode 100644 index 0000000..fef28f0 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/gfx.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/36043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38a26f3135d571e2f9b63840d38fd4d3476fc142 Gerrit-Change-Number: 36043 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: soc/intel: Intel graphics driver scans generic bus
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36042 ) Change subject: soc/intel: Intel graphics driver scans generic bus ...................................................................... soc/intel: Intel graphics driver scans generic bus This change allows for Intel graphics devices to use drivers/generic/gfx driver to populate ACPI SSDT table for common graphics related devices and methods. BUG=b:142237145 TEST=On sarien_cml add generic/gfx to the devicetree and device is enumerated and correct SSDT ASL is observed. Change-Id: Ibc86a88687ac860ebef19a4b68af64fd50d12b8e Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/soc/intel/common/block/graphics/graphics.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/36042/1 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 8e79eab..82133ff 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -118,6 +118,7 @@ .init = graphics_soc_init, .ops_pci = &pci_dev_ops_pci, .write_acpi_tables = graphics_soc_write_acpi_opregion, + .scan_bus = scan_generic_bus, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/36042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc86a88687ac860ebef19a4b68af64fd50d12b8e Gerrit-Change-Number: 36042 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: drivers/gfx: Add generic graphics with SSDT generator
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36041 ) Change subject: drivers/gfx: Add generic graphics with SSDT generator ...................................................................... drivers/gfx: Add generic graphics with SSDT generator This change adds a generic graphics driver that can be added to a devicetree which populates graphics related ACPI table. It will write the _DOD method (Enumerate All Devices Attached to the Display Adapter) and a device object for each device defined. The device may optionally have a connected privacy screen which can be controlled with a _DSM. Example: chip drivers/generic/gfx register "device_count" = "1" register "device[0].name" = ""LCD"" register "device[0].addr" = "0x0400" register "device[0].privacy.enabled" = "1" register "device[0].privacy.detect_function" = ""\\_SB.PCI0.PVSC.GPVD"" register "device[0].privacy.status_function" = ""\\_SB.PCI0.PVSC.GPVX"" register "device[0].privacy.enable_function" = ""\\_SB.PCI0.PVSC.EPVX"" register "device[0].privacy.disable_function" = ""\\_SB.PCI0.LPCB.EC0.DPVX"" device generic 0 on end end ASL Scope (\_SB.PCI0.GFX0) { Method (_DOD, 0, NotSerialized) // _DOD: Display Output Devices { Return (Package (0x01) { 0x00000400 }) } Device (LCD) { Name (_HID, "GOOG0010") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_ADR, 0x0400) // _ADR: Address Name (_STA, 0x0F) // _STA: Status Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("c7033113-8720-4ceb-9090-9d52b3e52d73"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Local2 = \_SB.PCI0.PVSC.GPVD () If ((Local2 == One)) { Return (Buffer (One) { 0x0F }) } } If ((Local1 == One)) { ToBuffer (\_SB.PCI0.PVSC.GPVX (), Local2) Return (Local2) } If ((Local1 == 0x02)) { \_SB.PCI0.PVSC.EPVX () } If ((Local1 == 0x03)) { \_SB.PCI0.PVSC.DPVX () } Return (Buffer (One) { 0x00 }) } Return (Buffer (One) { 0x00 }) } } } BUG=b:142237145 TEST=Added gfx to devicetree on sarien_cml and correct ASL in SSDT Change-Id: Ida520dd7aad81ee7c1e5f2d0d3f5cc1a766d78a0 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- A src/drivers/generic/gfx/Kconfig A src/drivers/generic/gfx/Makefile.inc A src/drivers/generic/gfx/chip.h A src/drivers/generic/gfx/gfx.c 4 files changed, 174 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/36041/1 diff --git a/src/drivers/generic/gfx/Kconfig b/src/drivers/generic/gfx/Kconfig new file mode 100644 index 0000000..f59275a --- /dev/null +++ b/src/drivers/generic/gfx/Kconfig @@ -0,0 +1,4 @@ +config DRIVERS_GENERIC_GFX + bool + default n + depends on HAVE_ACPI_TABLES \ No newline at end of file diff --git a/src/drivers/generic/gfx/Makefile.inc b/src/drivers/generic/gfx/Makefile.inc new file mode 100644 index 0000000..c31986b --- /dev/null +++ b/src/drivers/generic/gfx/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_GFX) += gfx.c diff --git a/src/drivers/generic/gfx/chip.h b/src/drivers/generic/gfx/chip.h new file mode 100644 index 0000000..1d8f909 --- /dev/null +++ b/src/drivers/generic/gfx/chip.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRIVERS_GENERIC_GFX_CHIP_H__ +#define __DRIVERS_GENERIC_GFX_CHIP_H__ + +struct drivers_generic_gfx_privacy_screen_config +{ + int enabled; + const char *detect_function; + const char *status_function; + const char *enable_function; + const char *disable_function; +}; + +struct drivers_generic_gfx_device_config +{ + const char *name; + int addr; + struct drivers_generic_gfx_privacy_screen_config privacy; +}; + + +struct drivers_generic_gfx_config { + int device_count; + struct drivers_generic_gfx_device_config device[5]; +}; + +#endif /* __DRIVERS_GENERIC_GFX_CHIP_H__ */ diff --git a/src/drivers/generic/gfx/gfx.c b/src/drivers/generic/gfx/gfx.c new file mode 100644 index 0000000..40fc871 --- /dev/null +++ b/src/drivers/generic/gfx/gfx.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <device/device.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#define ACPI_DSM_PRIVACY_SCREEN_UUID "C7033113-8720-4CEB-9090-9D52B3E52D73" + +static void privacy_screen_detect_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_write_store(); + acpigen_emit_namestring(config->detect_function); + acpigen_emit_byte(LOCAL2_OP); + acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); + acpigen_write_return_singleton_buffer(0xF); + acpigen_pop_len(); +} +static void privacy_screen_get_status_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_emit_byte(TO_BUFFER_OP); + acpigen_emit_namestring(config->status_function); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(LOCAL2_OP); +} +static void privacy_screen_enable_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_emit_namestring(config->enable_function); +} +static void privacy_screen_disable_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_emit_namestring(config->disable_function); +} + +static void (*privacy_screen_callbacks[])(void *) = { + privacy_screen_detect_cb, + privacy_screen_get_status_cb, + privacy_screen_enable_cb, + privacy_screen_disable_cb, +}; + +static void gfx_fill_ssdt_generator(struct device *dev) +{ + size_t i; + struct drivers_generic_gfx_config *config = dev->chip_info; + + const char *scope = acpi_device_scope(dev); + + acpigen_write_scope(scope); + + /* Method (_DOD, 0) */ + acpigen_write_method("_DOD", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(config->device_count); + for (i = 0; i < config->device_count; i++) { + acpigen_write_dword (config->device[i].addr); + } + acpigen_pop_len(); /* End Package. */ + acpigen_pop_len(); /* End Method. */ + + for (i = 0; i < config->device_count; i++) { + acpigen_write_device(config->device[i].name); + + acpigen_write_name_integer("_ADR", config->device[i].addr); + acpigen_write_name_integer("_STA", 0xF); + + if (config->device[i].privacy.enabled) { + acpigen_write_dsm(ACPI_DSM_PRIVACY_SCREEN_UUID, + privacy_screen_callbacks, + ARRAY_SIZE(privacy_screen_callbacks), + &config->device[i].privacy); + } + + acpigen_pop_len(); /* Device */ + } + acpigen_pop_len(); /* Scope */ +} + +static const char *gfx_acpi_name(const struct device *dev) +{ + return "GFX0"; +} + +static struct device_operations gfx_ops = { + .acpi_name = gfx_acpi_name, + .acpi_fill_ssdt_generator = gfx_fill_ssdt_generator, +}; + +static void gfx_enable(struct device *dev) +{ + struct drivers_generic_gfx_config *config = dev->chip_info; + + if (!config) + return; + + dev->ops = &gfx_ops; +} + +struct chip_operations drivers_generic_gfx_ops = { + CHIP_NAME("Graphics Device") + .enable_dev = gfx_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/36041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida520dd7aad81ee7c1e5f2d0d3f5cc1a766d78a0 Gerrit-Change-Number: 36041 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

6 35

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2019