coreboot-gerrit December 2019

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Change in em100[master]: curl.c: Limit version string length to buffer length
by Stefan Reinauer (Code Review) 02 Dec '19

02 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37423 ) Change subject: curl.c: Limit version string length to buffer length ...................................................................... curl.c: Limit version string length to buffer length To prevent a buffer overflow, specify the maximum length of the version string being parsed. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Id000154d4dd3137408302472b07b476933cc2d56 --- M curl.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/23/37423/1 diff --git a/curl.c b/curl.c index 95bb05e..6895c62 100644 --- a/curl.c +++ b/curl.c @@ -147,7 +147,7 @@ goto download_all; } - if (fscanf(old, "Time: %ld\nVersion: %s\n", + if (fscanf(old, "Time: %ld\nVersion: %255s\n", &old_time, old_version) != 2) printf("Parse error in %s.\n", my_version_name); @@ -164,7 +164,7 @@ free(tmp_version); return 1; } - if (fscanf(new, "Time: %ld\nVersion: %s\n", + if (fscanf(new, "Time: %ld\nVersion: %255s\n", &new_time, new_version) != 2) printf("Parse error in upstream VERSION.\n"); fclose(new); -- To view, visit https://review.coreboot.org/c/em100/+/37423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Id000154d4dd3137408302472b07b476933cc2d56 Gerrit-Change-Number: 37423 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Fix CID 264288 Resource leak
by Stefan Reinauer (Code Review) 02 Dec '19

02 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37422 ) Change subject: Fix CID 264288 Resource leak ...................................................................... Fix CID 264288 Resource leak opendir() needs closedir(). Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I316ee4f83a8b964cd9b0a6a5c3142ee080cab747 --- M em100.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/22/37422/1 diff --git a/em100.c b/em100.c index 301d574..5fa95dd 100644 --- a/em100.c +++ b/em100.c @@ -733,6 +733,7 @@ return NULL; } + closedir(dir); return directory; } -- To view, visit https://review.coreboot.org/c/em100/+/37422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I316ee4f83a8b964cd9b0a6a5c3142ee080cab747 Gerrit-Change-Number: 37422 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Fix CID 264287 Unchecked return value from library
by Stefan Reinauer (Code Review) 02 Dec '19

02 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37421 ) Change subject: Fix CID 264287 Unchecked return value from library ...................................................................... Fix CID 264287 Unchecked return value from library The return code of mkdir() wasn't checked. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I34d2d49d0ea17598f7bcfb56ee5debd9bd352b82 --- M em100.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/21/37421/1 diff --git a/em100.c b/em100.c index aa16e8a..301d574 100644 --- a/em100.c +++ b/em100.c @@ -722,7 +722,11 @@ if (dir) { // success } else if (errno == ENOENT) { - mkdir(directory, S_IRWXU | S_IRGRP | S_IXGRP | S_IROTH | S_IXOTH); + if (mkdir(directory, S_IRWXU | S_IRGRP | S_IXGRP | S_IROTH | S_IXOTH)) { + perror(directory); + directory[0]=0; + return NULL; + } } else { perror("EM100_HOME inaccessible"); directory[0]=0; -- To view, visit https://review.coreboot.org/c/em100/+/37421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I34d2d49d0ea17598f7bcfb56ee5debd9bd352b82 Gerrit-Change-Number: 37421 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Fix CID 264286 Buffer not null terminated
by Stefan Reinauer (Code Review) 02 Dec '19

02 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37420 ) Change subject: Fix CID 264286 Buffer not null terminated ...................................................................... Fix CID 264286 Buffer not null terminated Because get_em100_home() can return 1024 bytes, make sure we have one more byte for strncpy to NULL terminate. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I74ea46bbe60b650331be84588c6ad5a9a9034e91 --- M em100.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/20/37420/1 diff --git a/em100.c b/em100.c index d17b707..aa16e8a 100644 --- a/em100.c +++ b/em100.c @@ -734,7 +734,7 @@ char *get_em100_file(const char *name) { - char file[FILENAME_BUFFER_SIZE]; + char file[FILENAME_BUFFER_SIZE + 1]; strncpy(file, get_em100_home(), FILENAME_BUFFER_SIZE); strncat(file, name, FILENAME_BUFFER_SIZE - strlen(file) - 1); return strdup(file); -- To view, visit https://review.coreboot.org/c/em100/+/37420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I74ea46bbe60b650331be84588c6ad5a9a9034e91 Gerrit-Change-Number: 37420 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Fix CID 264285 Resource leak
by Stefan Reinauer (Code Review) 02 Dec '19

02 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37419 ) Change subject: Fix CID 264285 Resource leak ...................................................................... Fix CID 264285 Resource leak get_em100_file() allocates memory for the file name, so we have to free it again. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I59b7eafc828fd1a2e48e4b8a84708bfeff05c8f1 --- M em100.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/19/37419/1 diff --git a/em100.c b/em100.c index ad341e8..d17b707 100644 --- a/em100.c +++ b/em100.c @@ -666,7 +666,9 @@ static chipdesc *setup_chips(const char *desiredchip) { static chipdesc chip; - configs = tar_load_compressed(get_em100_file("configs.tar.xz")); + char *configs_name = get_em100_file("configs.tar.xz"); + configs = tar_load_compressed(configs_name); + free(configs_name); if (!configs) { printf("Can't find chip configs in $EM100_HOME/configs.tar.xz.\n"); return NULL; -- To view, visit https://review.coreboot.org/c/em100/+/37419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I59b7eafc828fd1a2e48e4b8a84708bfeff05c8f1 Gerrit-Change-Number: 37419 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: makechips.sh: Analyse the Windows installer for version
by Stefan Reinauer (Code Review) 02 Dec '19

02 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37410 ) Change subject: makechips.sh: Analyse the Windows installer for version ...................................................................... makechips.sh: Analyse the Windows installer for version Right now, the version we assume for the chips and firmware is whatever the dediprog.com lists as the latest version (as long as the web site formwat does not change). This is inaccurate, because you might be operating on a very different msi archive (e.g. using a beta version, or when operating with an older, cached binary on a builder). Instead, use the ProductVersion string that is encoded in the binary as a trusted source. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I9c7e48d1372bc587014e3af0a0327c70c30d7faa --- M makechips.sh 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/10/37410/1 diff --git a/makechips.sh b/makechips.sh index 849ae57..bd02270 100755 --- a/makechips.sh +++ b/makechips.sh @@ -38,14 +38,13 @@ curl -s $URL -o $FILE || exit fi echo " Unpacking ..." -VERSION="$( curl -s "$VURL" | grep -A2 EM100Pro-G2\ Soft|tail -1| cut -d\< -f1 | tr -d ' ')" -echo " Detected SPI flash database \"$VERSION\"" - if ! msiextract $FILE > /dev/null ; then echo " Could not unpack Windows installer..." rm -rf $TEMP exit 1 fi +VERSION="$( strings -e l Program\ Files/DediProg/EM100/EM100.exe |grep -A1 ProductVersion|grep EM100 )" +echo " Detected SPI flash database \"$VERSION\"" echo " Creating configs..." mkdir -p $TD/configs -- To view, visit https://review.coreboot.org/c/em100/+/37410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I9c7e48d1372bc587014e3af0a0327c70c30d7faa Gerrit-Change-Number: 37410 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: soc/intel/broadwell_de: Re-read SPD on CRC error
by David Hendricks (Code Review) 02 Dec '19

02 Dec '19

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37303 ) Change subject: soc/intel/broadwell_de: Re-read SPD on CRC error ...................................................................... Patch Set 1: -Code-Review Also, add your Signed-off-by line. -- To view, visit https://review.coreboot.org/c/coreboot/+/37303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Gerrit-Change-Number: 37303 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Dec 2019 18:44:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration
by Aaron Durbin (Code Review) 02 Dec '19

02 Dec '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37319 ) Change subject: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/37319/4/src/soc/intel/cannonlake/b… File src/soc/intel/cannonlake/bootblock/pch.c: https://review.coreboot.org/c/coreboot/+/37319/4/src/soc/intel/cannonlake/b… PS4, Line 204: Disable GPIO community PM configuration This is only acting on the devicetree fields. It may no be disabling anything. -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Dec 2019 18:14:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/qemu-x86: Add x86_64 bootblock support
by Patrick Rudolph (Code Review) 02 Dec '19

02 Dec '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35680 ) Change subject: cpu/qemu-x86: Add x86_64 bootblock support ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/35680/8/util/pgtblgen/pgtblgen.c File util/pgtblgen/pgtblgen.c: https://review.coreboot.org/c/coreboot/+/35680/8/util/pgtblgen/pgtblgen.c@31 PS8, Line 31: -b > This is wrong. […] fixed in CB:37369 -- To view, visit https://review.coreboot.org/c/coreboot/+/35680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Gerrit-Change-Number: 35680 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Name of user not set #1002476 Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 02 Dec 2019 16:58:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Move 'static' is at beginning of declaration
by HAOUAS Elyes (Code Review) 02 Dec '19

02 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33673 Change subject: src: Move 'static' is at beginning of declaration ...................................................................... src: Move 'static' is at beginning of declaration Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gizmosphere/gizmo/platform_cfg.h M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_crtm.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/intel/fsp_broadwell_de/gpio.c 7 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33673/1 diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index 57b1aec..c56b537 100644 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -212,7 +212,7 @@ */ #define GEC_CONFIG 0 -const static CODECENTRY gizmo_codec_alc272[] = +static const CODECENTRY gizmo_codec_alc272[] = { /* NID, PinConfig */ {0x11, 0x411111F0}, /* S/PDIF-OUT2 unused */ diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index ed372b5..a1ba310 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -88,7 +88,7 @@ } } -const static u8 max_tap[3] = {12, 10, 13}; +static const u8 max_tap[3] = {12, 10, 13}; static int increment_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting) @@ -540,7 +540,7 @@ u32 emrs1; /* Is shifted by bits 2 later so u8 can be used to reduce size */ - const static u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */ + static const u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */ { /* Config 0: 2R2R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x11, 0x91, 0x00}, diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 32618e8..8ca6ec1 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -437,7 +437,7 @@ 5200 }; - const static u8 ddr3_turnaround_tab[3][6][4] = { + static const u8 ddr3_turnaround_tab[3][6][4] = { { /* DDR3 800 */ {0x9, 0x7, 0x7, 0x9}, /* CL = 5 */ {0x9, 0x7, 0x8, 0x8}, /* CL = 6 */ @@ -459,7 +459,7 @@ }; /* [DDR freq][0x26F & 1][pagemod] */ - const static u8 ddr2_x252_tab[2][2][2] = { + static const u8 ddr2_x252_tab[2][2][2] = { { /* DDR2 667 */ {12, 16}, {14, 18} @@ -470,7 +470,7 @@ } }; - const static u8 ddr3_x252_tab[3][2][2] = { + static const u8 ddr3_x252_tab[3][2][2] = { { /* DDR3 800 */ {16, 20}, {18, 22} diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 39cd614..50da155 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -173,7 +173,7 @@ * i.e. those which should not be possible to delete or modify once * the RO exits, and the rest of the NVRAM spaces. */ -const static TPMA_NV ro_space_attributes = { +static const TPMA_NV ro_space_attributes = { .TPMA_NV_PPWRITE = 1, .TPMA_NV_AUTHREAD = 1, .TPMA_NV_PPREAD = 1, @@ -182,7 +182,7 @@ .TPMA_NV_POLICY_DELETE = 1, }; -const static TPMA_NV rw_space_attributes = { +static const TPMA_NV rw_space_attributes = { .TPMA_NV_PPWRITE = 1, .TPMA_NV_AUTHREAD = 1, .TPMA_NV_PPREAD = 1, @@ -193,7 +193,7 @@ * This policy digest was obtained using TPM2_PolicyPCR * selecting only PCR_0 with a value of all zeros. */ -const static uint8_t pcr0_unchanged_policy[] = { +static const uint8_t pcr0_unchanged_policy[] = { 0x09, 0x93, 0x3C, 0xCE, 0xEB, 0xB4, 0x41, 0x11, 0x18, 0x81, 0x1D, 0xD4, 0x47, 0x78, 0x80, 0x08, 0x88, 0x86, 0x62, 0x2D, 0xD7, 0x79, 0x94, 0x46, 0x62, 0x26, 0x68, 0x8E, 0xEE, 0xE6, 0x6A, 0xA1}; diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index e4266b2..f68ab0a4 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -29,7 +29,7 @@ { int i; struct region_device fmap; - const static char *fmap_cbfs_names[] = { + static const char *fmap_cbfs_names[] = { "COREBOOT", "FW_MAIN_A", "FW_MAIN_B", diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 45408ea..e1df91f 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -44,7 +44,7 @@ * waiting for each device to become available, a single delay will be * executed. */ -const static struct stoneyridge_aoac aoac_devs[] = { +static const struct stoneyridge_aoac aoac_devs[] = { { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, @@ -116,7 +116,7 @@ * amd_pci_int_defs.h, just add the pair at the end of this table. * Order is not important. */ -const static struct irq_idx_name irq_association[] = { +static const struct irq_idx_name irq_association[] = { { PIRQ_A, "INTA#" }, { PIRQ_B, "INTB#" }, { PIRQ_C, "INTC#" }, diff --git a/src/soc/intel/fsp_broadwell_de/gpio.c b/src/soc/intel/fsp_broadwell_de/gpio.c index 41100e9..01c4d9e 100644 --- a/src/soc/intel/fsp_broadwell_de/gpio.c +++ b/src/soc/intel/fsp_broadwell_de/gpio.c @@ -24,7 +24,7 @@ #include <soc/gpio.h> /* Use a wrapper for register addresses for different banks. */ -const static struct gpio_config_regs regs[GPIO_NUM_BANKS] = { +static const struct gpio_config_regs regs[GPIO_NUM_BANKS] = { [0] = { .use_sel = GPIO_1_USE_SEL, .io_sel = GPIO_1_IO_SEL, .level = GPIO_1_LVL, .nmi_en = GPIO_1_NMI_EN, .blink_en = GPIO_1_BLINK, .invert_input = GPIO_1_INVERT }, -- To view, visit https://review.coreboot.org/c/coreboot/+/33673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Gerrit-Change-Number: 33673 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019