coreboot-gerrit December 2019

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Change in coreboot[master]: mb/intel/tglrvp: Do initial mainboard commit
by build bot (Jenkins) (Code Review) 03 Dec '19

03 Dec '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36091 ) Change subject: mb/intel/tglrvp: Do initial mainboard commit ...................................................................... Patch Set 9: (10 comments) https://review.coreboot.org/c/coreboot/+/36091/9/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/36091/9/src/mainboard/intel/tglrvp… PS9, Line 1: config BOARD_INTEL_BASEBOARD_TGLRVP trailing whitespace https://review.coreboot.org/c/coreboot/+/36091/9/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/chromeos.c: https://review.coreboot.org/c/coreboot/+/36091/9/src/mainboard/intel/tglrvp… PS9, Line 31: {-1, ACTIVE_HIGH, 0,"EC in RW"}, space required after that ',' (ctx:VxV) https://review.coreboot.org/c/coreboot/+/36091/9/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/variants/baseboard/memory.c: https://review.coreboot.org/c/coreboot/+/36091/9/src/mainboard/intel/tglrvp… PS9, Line 32: { 15, 8, 9, 14, 12, 11, 10, 13 }}, // Byte 1 space required after that close brace '}' https://review.coreboot.org/c/coreboot/+/36091/9/src/mainboard/intel/tglrvp… PS9, Line 34: { 3, 4, 7, 0, 6, 1, 5, 2 }}, // Byte 3 space required after that close brace '}' https://review.coreboot.org/c/coreboot/+/36091/9/src/mainboard/intel/tglrvp… PS9, Line 36: { 11, 10, 12, 13, 8, 9, 14, 15 }}, // Byte 5 space required after that close brace '}' https://review.coreboot.org/c/coreboot/+/36091/9/src/mainboard/intel/tglrvp… PS9, Line 38: { 4, 7, 3, 2, 1, 6, 0, 5 }}, // Byte 7 space required after that close brace '}' https://review.coreboot.org/c/coreboot/+/36091/9/src/mainboard/intel/tglrvp… PS9, Line 41: { 4, 5, 6, 7, 3, 2, 0, 1 }}, // Byte 1 ChB! space required after that close brace '}' https://review.coreboot.org/c/coreboot/+/36091/9/src/mainboard/intel/tglrvp… PS9, Line 43: { 9, 8, 10, 11, 14, 15, 13, 12 }}, // Byte 3 space required after that close brace '}' https://review.coreboot.org/c/coreboot/+/36091/9/src/mainboard/intel/tglrvp… PS9, Line 45: { 10, 13, 12, 11, 14, 9, 15, 8 }}, // Byte 5 space required after that close brace '}' https://review.coreboot.org/c/coreboot/+/36091/9/src/mainboard/intel/tglrvp… PS9, Line 47: { 3, 4, 1, 2, 6, 0, 5, 7 }} // Byte 7 space required after that close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/36091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a05881d2ea50ff4113243bf5ae26207db63322 Gerrit-Change-Number: 36091 Gerrit-PatchSet: 9 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Dec 2019 07:11:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Do initial mainboard commit
by Ravishankar Sarawadi (Code Review) 03 Dec '19

03 Dec '19

Hello Raj Astekar, Subrata Banik, Arthur Heymans, John Zhao, Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36091 to look at the new patch set (#9). Change subject: mb/intel/tglrvp: Do initial mainboard commit ...................................................................... mb/intel/tglrvp: Do initial mainboard commit 1. Add tglrvp baseboard files 2. Add tglrvp UP3 variant board files 3. Add board id support 4. Add SPD memory support Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I79a05881d2ea50ff4113243bf5ae26207db63322 --- A src/mainboard/intel/tglrvp/Kconfig A src/mainboard/intel/tglrvp/Kconfig.name A src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/acpi/mainboard.asl A src/mainboard/intel/tglrvp/acpi/mipi_camera.asl A src/mainboard/intel/tglrvp/acpi_tables.c A src/mainboard/intel/tglrvp/board_id.c A src/mainboard/intel/tglrvp/board_id.h A src/mainboard/intel/tglrvp/board_info.txt A src/mainboard/intel/tglrvp/bootblock.c A src/mainboard/intel/tglrvp/chromeos.c A src/mainboard/intel/tglrvp/chromeos.fmd A src/mainboard/intel/tglrvp/dsdt.asl A src/mainboard/intel/tglrvp/ec.c A src/mainboard/intel/tglrvp/romstage.c A src/mainboard/intel/tglrvp/smihandler.c A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex A src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex A src/mainboard/intel/tglrvp/spd/spd.h A src/mainboard/intel/tglrvp/variants/baseboard/Makefile.inc A src/mainboard/intel/tglrvp/variants/baseboard/devicetree.cb A src/mainboard/intel/tglrvp/variants/baseboard/gpio.c A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/tglrvp/variants/baseboard/mainboard.c A src/mainboard/intel/tglrvp/variants/baseboard/memory.c A src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/ec.h A src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/gpio.h 32 files changed, 2,086 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/36091/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/36091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a05881d2ea50ff4113243bf5ae26207db63322 Gerrit-Change-Number: 36091 Gerrit-PatchSet: 9 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/tglrvp: Do initial mainboard commit
by Ravishankar Sarawadi (Code Review) 03 Dec '19

03 Dec '19

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37437 ) Change subject: mb/intel/tglrvp: Do initial mainboard commit ...................................................................... mb/intel/tglrvp: Do initial mainboard commit 1. Add tglrvp baseboard files 2. Add tglrvp UP3 variant board files 3. Add board id support 4. Add SPD memory support Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I1649e80b21a3811841a9c7f14f15d5684f1edc99 --- A src/mainboard/intel/tglrvp/Kconfig A src/mainboard/intel/tglrvp/Kconfig.name A src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/acpi/mainboard.asl A src/mainboard/intel/tglrvp/acpi/mipi_camera.asl A src/mainboard/intel/tglrvp/acpi_tables.c A src/mainboard/intel/tglrvp/board_id.c A src/mainboard/intel/tglrvp/board_id.h A src/mainboard/intel/tglrvp/board_info.txt A src/mainboard/intel/tglrvp/bootblock.c A src/mainboard/intel/tglrvp/chromeos.c A src/mainboard/intel/tglrvp/chromeos.fmd A src/mainboard/intel/tglrvp/dsdt.asl A src/mainboard/intel/tglrvp/ec.c A src/mainboard/intel/tglrvp/romstage.c A src/mainboard/intel/tglrvp/smihandler.c A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex A src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex A src/mainboard/intel/tglrvp/spd/spd.h A src/mainboard/intel/tglrvp/variants/baseboard/Makefile.inc A src/mainboard/intel/tglrvp/variants/baseboard/devicetree.cb A src/mainboard/intel/tglrvp/variants/baseboard/gpio.c A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/tglrvp/variants/baseboard/mainboard.c A src/mainboard/intel/tglrvp/variants/baseboard/memory.c A src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/ec.h A src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/gpio.h 32 files changed, 2,085 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/37437/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig new file mode 100644 index 0000000..5def937 --- /dev/null +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -0,0 +1,104 @@ +config BOARD_INTEL_BASEBOARD_TGLRVP + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_I2C_MAX98373 + select DRIVERS_I2C_RT1308 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_LPC + select GENERATE_SMBIOS_TABLES + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 + select SOC_INTEL_TIGERLAKE + +if BOARD_INTEL_BASEBOARD_TGLRVP + +config DIMM_SPD_SIZE + int + default 512 + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config GBB_HWID + string + depends on CHROMEOS + default "TGLRVP" if BOARD_INTEL_TGLRVP + +config MAINBOARD_DIR + string + default "intel/tglrvp" + +config MAINBOARD_FAMILY + string + default "Intel_tglrvp" if BOARD_INTEL_TGLRVP + +config MAINBOARD_PART_NUMBER + string + default "Tglrvp" if BOARD_INTEL_TGLRVP + +config MAX_CPUS + int + default 8 + +config OEM_BIN_FILE + string "OEM ID table" + default "" + +config UART_FOR_CONSOLE + int + default 2 + +config VARIANT_DIR + string + default "tglrvp_up3" if BOARD_INTEL_TGLRVP + +choice TGL_EC + prompt "ON BOARD EC" + default TGL_CHROME_EC + help + This option allows you to select the on board EC to use. + Select whether the board has Intel EC or Chrome EC + +config TGL_CHROME_EC + bool "Chrome EC" + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select EC_ACPI + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_FORCE_MANUAL_RECOVERY + +config TGL_INTEL_EC + bool "Intel EC" + select EC_ACPI + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC +endchoice + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + +config BOARD_LPDDR4 + bool "Memory Type" + default y + +config LPDDR4_MC0_DISABLE + bool "LPDDR4 WA" + default n + +endif diff --git a/src/mainboard/intel/tglrvp/Kconfig.name b/src/mainboard/intel/tglrvp/Kconfig.name new file mode 100644 index 0000000..1ea0930 --- /dev/null +++ b/src/mainboard/intel/tglrvp/Kconfig.name @@ -0,0 +1,7 @@ +comment "Tglrvp" + +config BOARD_INTEL_TGLRVP + bool "-> Tglrvp" + select BOARD_INTEL_BASEBOARD_TGLRVP + select VARIANT_SPECIFIC_OPTIONS_TGLRVP + diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc new file mode 100644 index 0000000..e75bd94 --- /dev/null +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c +bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-$(CONFIG_CHROMEOS) += romstage.c +romstage-$(CONFIG_CHROMEOS) += board_id.c + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c +ramstage-$(CONFIG_CHROMEOS) += board_id.c + +smm-y += ec.c +smm-y += smihandler.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +subdirs-y += spd diff --git a/src/mainboard/intel/tglrvp/acpi/mainboard.asl b/src/mainboard/intel/tglrvp/acpi/mainboard.asl new file mode 100644 index 0000000..6647ac1 --- /dev/null +++ b/src/mainboard/intel/tglrvp/acpi/mainboard.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if CONFIG(EC_GOOGLE_CHROMEEC) +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} +#endif diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl new file mode 100644 index 0000000..bd2727e --- /dev/null +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -0,0 +1,533 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0) +{ + Device (IPU0) + { + Name (_ADR, 0x00050000) // _ADR: Address + Name (_DDN, "Camera and Imaging Subsystem") // _DDN: DOS Device Name + } +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + One + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} + +Scope (_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM0, + Zero, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C5.CAM1, + Zero, + Zero + } + } + } + }) +} + +Scope (\_SB.PCI0.I2C3) +{ + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) // _ON_: Power On + { + If ((STA == Zero)) + { + // Enable CLK0 + MCCT(0,1,1) // Clock 0, enable, 19.2MHz + // Pull PWREN(GPIO B23) high + STXS(GPP_B23) + Sleep(5) + // Pull RST(GPIO C15) low + CTXS(GPP_C15) + Sleep(5) + // Pull RST high + STXS(GPP_C15) + Sleep(5) + Store(1,STA) + } + } + + Method (_OFF, 0, Serialized) // _OFF: Power Off + { + If ((STA == One)) + { + // Pull RST low + CTXS(GPP_C15) + // Pull PWREN low + CTXS(GPP_B23) + // Disable CLK0 + MCCT(0,0,1) // Clock 0, disable, 19.2MHz + // STA = Zero + Store(0,STA) + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (STA) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI8856") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_DDN, "Ov 8856 Camera") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + RCPR + }) + + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + RCPR + }) + + Name (_DSD, Package (0x04) // _DSD: Device-Specific Data + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x325AA000 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } + + Device (VCM0) + { + Name (_HID, "PRP0001") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_DDN, "DW9714 VCM") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + CAM0 + }) + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + RCPR + }) + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + RCPR + }) + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} + +Scope (\_SB.PCI0.I2C5) +{ + PowerResource (FCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) // _ON_: Power On + { + If ((STA == Zero)) + { + // Enable CLK1 + MCCT(1,1,1) // Clock 1, enable, 19.2MHz + // Pull PWREN(GPIO R6) high + STXS(GPP_R6) + Sleep(5) + // Pull RST(GPIO H12) low + CTXS(GPP_H12) + Sleep(5) + // Pull RST high + STXS(GPP_H12) + Sleep(5) + Store(1,STA) + } + } + + Method (_OFF, 0, Serialized) // _OFF: Power Off + { + If ((STA == One)) + { + // Pull RST low + CTXS(GPP_H12) + // Pull PWREN low + CTXS(GPP_R6) + // Disable CLK0 + MCCT(1,0,1) // Clock 1, disable, 19.2MHz + Store(0,STA) + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (STA) + } + } + + Device (CAM1) + { + Name (_HID, "OVTI8856") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_DDN, "Ov 8856 Camera") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + FCPR + }) + + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + FCPR + }) + + Name (_DSD, Package (0x04) // _DSD: Device-Specific Data + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x325AA000 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/intel/tglrvp/acpi_tables.c b/src/mainboard/intel/tglrvp/acpi_tables.c new file mode 100644 index 0000000..3b44754 --- /dev/null +++ b/src/mainboard/intel/tglrvp/acpi_tables.c @@ -0,0 +1 @@ +/* Nothing here */ diff --git a/src/mainboard/intel/tglrvp/board_id.c b/src/mainboard/intel/tglrvp/board_id.c new file mode 100644 index 0000000..9645810 --- /dev/null +++ b/src/mainboard/intel/tglrvp/board_id.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "board_id.h" +#include <boardid.h> +#include <ec/acpi/ec.h> +#include <stdint.h> +#include <ec/google/chromeec/ec.h> + +static int get_board_id_via_ext_ec(void) +{ + uint32_t id = BOARD_ID_INIT; + + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + + return id; +} + +/* Get Board ID via EC I/O port write/read */ +int get_board_id(void) +{ + MAYBE_STATIC_NONZERO int id = -1; + + if (id < 0) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) + id = get_board_id_via_ext_ec(); + else { + uint8_t buffer[2]; + uint8_t index; + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + for (index = 0; index < sizeof(buffer); index++) + buffer[index] = recv_ec_data(); + id = (buffer[0] << 8) | buffer[1]; + } + } + } + + return id; +} diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h new file mode 100644 index 0000000..01a19e7 --- /dev/null +++ b/src/mainboard/intel/tglrvp/board_id.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_BOARD_ID_H_ +#define _MAINBOARD_BOARD_ID_H_ + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0D + +/* TGL-U Board IDs */ +#define TGL_U_LP4_SAMSUNG 0x3 +#define TGL_U_LP4_HYNIX 0xB +#define TGL_U_LP4_MICRON 0x13 +#define TGL_U_DDR4 0xA + +/* TGL-Y Board IDs */ +#define TGL_Y_LP4_SAMSUNG 0x5 +#define TGL_Y_LP4_HYNIX 0xD +#define TGL_Y_LP4_MICRON 0x15 + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/tglrvp/board_info.txt b/src/mainboard/intel/tglrvp/board_info.txt new file mode 100644 index 0000000..cd2cf11 --- /dev/null +++ b/src/mainboard/intel/tglrvp/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: tglrvp +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/tglrvp/bootblock.c b/src/mainboard/intel/tglrvp/bootblock.c new file mode 100644 index 0000000..3c773e9 --- /dev/null +++ b/src/mainboard/intel/tglrvp/bootblock.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c new file mode 100644 index 0000000..5bd4658 --- /dev/null +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0,"EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd new file mode 100644 index 0000000..bfbd304 --- /dev/null +++ b/src/mainboard/intel/tglrvp/chromeos.fmd @@ -0,0 +1,44 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x1081000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x80000 + SI_ME@0x81000 0x1000000 + } + SI_BIOS@0x1400000 0xC00000 { + RW_SECTION_A@0x0 0x2d0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x2bffc0 + RW_FWID_A@0x2cffc0 0x40 + } + RW_SECTION_B@0x2d0000 0x2d0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x2bffc0 + RW_FWID_B@0x2cffc0 0x40 + } + RW_MISC@0x5a0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 + } + SMMSTORE@0x5d0000 0x40000 + RW_LEGACY(CBFS)@0x610000 0x1c0000 + WP_RO@0x7d0000 0x430000 { + RO_VPD@0x0 0x4000 + RO_SECTION@0x4000 0x42c000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x33c000 + } + } + } +} diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl new file mode 100755 index 0000000..1b9e952 --- /dev/null +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include "variant/ec.h" +#include "variant/gpio.h" + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/tigerlake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/tigerlake/acpi/northbridge.asl> + #include <soc/intel/tigerlake/acpi/southbridge.asl> + } + } + + Scope (\_SB) { + Device (PEPD) + { + Name (_HID, "INT33A1" /* Intel Power Engine */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0D80") /* System Power Management Controller */) // _CID: Compatible ID + Name (_UID, One) // _UID: Unique ID + Name (PPD0, Package (0x03) + { + "\\_SB.PC00.SAT0", + Zero, + Package (0x02) + { + Zero, + Package (0x03) + { + 0xFF, + Zero, + 0x81 + } + } + }) + } + } + +#if CONFIG(CHROMEOS) + // Chrome OS specific + #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + // Chipset specific sleep states + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" + +} diff --git a/src/mainboard/intel/tglrvp/ec.c b/src/mainboard/intel/tglrvp/ec.c new file mode 100644 index 0000000..4699806 --- /dev/null +++ b/src/mainboard/intel/tglrvp/ec.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/lpc_lib.h> +#include <variant/ec.h> + +static void ramstage_ec_init(void) +{ + static const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + printk(BIOS_ERR, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} + +static void bootblock_ec_init(void) +{ + uint16_t ec_ioport_base; + size_t ec_ioport_size; + + /* + * Set up LPC decoding for the ChromeEC I/O port ranges: + * - Ports 62/66, 60/64, and 200->208 + * - ChromeEC specific communication I/O ports. + */ + lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64 + | LPC_IOE_LGE_200); + google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size); + lpc_open_pmio_window(ec_ioport_base, ec_ioport_size); +} + +void mainboard_ec_init(void) +{ + if (ENV_RAMSTAGE) + ramstage_ec_init(); + else if (ENV_BOOTBLOCK) + bootblock_ec_init(); +} diff --git a/src/mainboard/intel/tglrvp/romstage.c b/src/mainboard/intel/tglrvp/romstage.c new file mode 100644 index 0000000..caca186 --- /dev/null +++ b/src/mainboard/intel/tglrvp/romstage.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <string.h> +#include "board_id.h" +#include "spd/spd.h" + +#include <assert.h> +#include <baseboard/variants.h> +#include <cbfs.h> +#include <console/console.h> +#include <soc/romstage.h> + +static uintptr_t mainboard_get_spd_data(void) +{ + char *spd_file; + size_t spd_file_len; + const size_t spd_len = CONFIG_DIMM_SPD_SIZE; + const char *spd_bin = "spd.bin"; + uint8_t board_id = (get_board_id() & 0xFF); + int spd_index; + + printk(BIOS_INFO, "board id is 0x%x\n", board_id); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < spd_len) + die("Missing SPD data."); + + switch (board_id) { + case TGL_U_LP4_MICRON: + case TGL_Y_LP4_MICRON: + spd_index = SPD_ID_MICRON; + break; + + case TGL_U_LP4_SAMSUNG: + case TGL_Y_LP4_SAMSUNG: + spd_index = SPD_ID_SAMSUNG; + break; + + case TGL_U_LP4_HYNIX: + case TGL_Y_LP4_HYNIX: + spd_index = SPD_ID_HYNIX; + break; + + default: + spd_index = SPD_ID_HYNIX; + printk(BIOS_INFO, "Invalid board_id 0x%x\n", board_id); + } + + printk(BIOS_INFO, "SPD index is 0x%x\n", spd_index); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * spd_len)) + die("Invalid SPD index."); + + spd_index *= spd_len; + + return (uintptr_t)(spd_file + spd_index); +} + + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + + struct memory_config mem_params; + uint8_t board_id = (get_board_id() & 0xFF); + uintptr_t spd_ptr; + + + memset(&mem_params, 0, sizeof(mem_params)); + variant_memory_params(&mem_params); + + if (mem_params.dq_map && mem_params.dq_map_size) + memcpy(&mem_cfg->DqMapCpu2DramMc0Ch0, mem_params.dq_map, + mem_params.dq_map_size); + + if (mem_params.dqs_map && mem_params.dqs_map_size) + memcpy(&mem_cfg->DqsMapCpu2DramMc0Ch0, mem_params.dqs_map, + mem_params.dqs_map_size); + + mem_cfg->RcompResistor = mem_params.rcomp_resistor; + + memcpy(&mem_cfg->RcompTarget, mem_params.rcomp_target, + mem_params.rcomp_target_size); + + if (CONFIG(BOARD_LPDDR4)) { + /* Set 0 for SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1 */ + mem_cfg->SpdAddressTable[0] = 0x0; + mem_cfg->SpdAddressTable[1] = 0x0; + mem_cfg->SpdAddressTable[8] = 0x0; + mem_cfg->SpdAddressTable[9] = 0x0; + + /* CH 0-7 Single Rank Config + MC0 - Controls CH 0-3 -> connected to DIMM 0-1 + MC1 - Controls CH 4-7 -> connected to DIMM 2-3 */ + spd_ptr = mainboard_get_spd_data(); + + if (CONFIG(LPDDR4_MC0_DISABLE)) + printk(BIOS_INFO, "MC0 is disabled\n"); + else { + if ((board_id != TGL_U_LP4_SAMSUNG) && + (board_id != TGL_Y_LP4_SAMSUNG)) { + mem_cfg->MemorySpdPtr000 = spd_ptr; + mem_cfg->MemorySpdPtr010 = spd_ptr; + mem_cfg->MemorySpdPtr020 = spd_ptr; + mem_cfg->MemorySpdPtr030 = spd_ptr; + } else { + printk(BIOS_INFO, + "Samsung LP4 WA, MC0 disabled\n"); + } + } + mem_cfg->MemorySpdPtr100 = spd_ptr; + mem_cfg->MemorySpdPtr110 = spd_ptr; + mem_cfg->MemorySpdPtr120 = spd_ptr; + mem_cfg->MemorySpdPtr130 = spd_ptr; + + mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + + } else { + mem_cfg->SpdAddressTable[0] = 0xA0; + mem_cfg->SpdAddressTable[1] = 0xA2; + mem_cfg->SpdAddressTable[8] = 0xA4; + mem_cfg->SpdAddressTable[9] = 0xA6; + } +} diff --git a/src/mainboard/intel/tglrvp/smihandler.c b/src/mainboard/intel/tglrvp/smihandler.c new file mode 100644 index 0000000..4b541f9 --- /dev/null +++ b/src/mainboard/intel/tglrvp/smihandler.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <intelblocks/smihandler.h> +#include <variant/ec.h> + +#if CONFIG(EC_GOOGLE_CHROMEEC) +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} +#endif + diff --git a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex new file mode 100644 index 0000000..324bddc --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 1B 21 F0 08 00 40 00 00 0A 01 00 00 +00 00 05 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 56 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/Makefile.inc b/src/mainboard/intel/tglrvp/spd/Makefile.inc new file mode 100644 index 0000000..a91415d --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Makefile.inc @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = Micron-MT53D1G64D8SQ-046 +SPD_SOURCES += Samsung-K4UBE3D4AA-MGCL +SPD_SOURCES += Hynix-H9HKNNNEBMAV-4267 + +ifeq ($(SPD_SOURCES),) + SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) +else + SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +endif + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex new file mode 100644 index 0000000..d38a515 --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex @@ -0,0 +1,32 @@ +23 10 11 0E 15 19 95 08 00 40 00 00 02 21 00 00 +48 00 05 FF 92 55 00 00 8C 00 90 A8 90 90 06 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex new file mode 100644 index 0000000..95a495e --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 16 21 95 08 00 40 00 00 0A 01 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/spd.h b/src/mainboard/intel/tglrvp/spd/spd.h new file mode 100644 index 0000000..283a5c6 --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/spd.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define RCOMP_TARGET_PARAMS 0x5 + +/* SPD index definition should be matched with the order of SPD_SOURCES */ +#define SPD_ID_MICRON 0x0 +#define SPD_ID_SAMSUNG 0x1 +#define SPD_ID_HYNIX 0x2 + +void mainboard_fill_dq_map_ch0(void *dq_map_ptr); +void mainboard_fill_dq_map_ch1(void *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/Makefile.inc b/src/mainboard/intel/tglrvp/variants/baseboard/Makefile.inc new file mode 100644 index 0000000..7147e31 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Intel, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c +ramstage-y += mainboard.c + +smm-y += gpio.c diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/tglrvp/variants/baseboard/devicetree.cb new file mode 100755 index 0000000..c5cd65d --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/devicetree.cb @@ -0,0 +1,114 @@ +chip soc/intel/tigerlake + + device cpu_cluster 0 on + device lapic 0 on end + end + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoPci, + [PchSerialIoIndexUART3] = PchSerialIoDisabled, + [PchSerialIoIndexUART4] = PchSerialIoDisabled, + [PchSerialIoIndexUART5] = PchSerialIoDisabled, + [PchSerialIoIndexUART6] = PchSerialIoDisabled, + }" + + device domain 0 on + #From EDS(575683) + device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF 0x9A03 + device pci 05.0 on end # IPU 0x9A19 + device pci 06.0 on end # PEG60 0x9A09 + device pci 07.0 on end # TBT_PCIe0 0x9A23 + device pci 07.1 on end # TBT_PCIe1 0x9A25 + device pci 07.2 on end # TBT_PCIe2 0x9A27 + device pci 07.3 on end # TBT_PCIe3 0x9A29 + device pci 08.0 on end # GNA 0x9A11 + device pci 09.0 on end # NPK 0x9A33 + device pci 0a.0 on end # Crash-log SRAM 0x9A0D + device pci 0d.0 on end # USB xHCI 0x9A13 + device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 + device pci 0d.2 on end # TBT DMA0 0x9A1B + device pci 0d.3 on end # TBT DMA1 0x9A1D + device pci 0e.0 on end # VMD 0x9A0B + + # From PCH EDS(576591) + device pci 10.0 on end # I2C6 0xA0D8 + device pci 10.1 on end # I2C7 0xA0D9 + device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.6 off end # THC0 0xA0D0 + device pci 10.7 off end # THC1 0xA0D1 + + device pci 11.0 on end # UART3 0xA0DA + device pci 11.1 on end # UART4 0xA0DB + device pci 11.2 on end # UART5 0xA0DC + device pci 11.3 on end # UART6 0xA0DD + + device pci 12.0 on # SensorHUB 0xA0FC + end + + device pci 12.6 on end # GSPI2 0x34FB + + device pci 13.0 on end # GSPI3 0xA0FD + device pci 13.1 on end # GSPI4 0xA0FE + device pci 13.2 on end # GSPI5 0xA0DE + device pci 13.3 on end # GSPI6 0xA0DF + + device pci 14.0 on end + device pci 14.1 on end # USB3.1 xDCI 0xA0EE + device pci 14.2 on end # Shared RAM 0xA0EF + device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + + device pci 15.0 on # I2C0 0xA0E8 + end # I2C #0 + device pci 15.1 on end # I2C1 0xA0E9 + device pci 15.2 on end # I2C2 0xA0EA + device pci 15.3 on end # I2C3 0xA0EB + + device pci 16.0 on end # HECI1 0xA0E0 + device pci 16.1 off end # HECI2 0xA0E1 + device pci 16.2 off end # CSME 0xA0E2 + device pci 16.3 off end # CSME 0xA0E3 + device pci 16.4 off end # HECI3 0xA0E4 + device pci 16.5 off end # HECI4 0xA0E5 + + device pci 17.0 on end # SATA 0xA0D3 + + device pci 19.0 on end # I2C4 0xA0C5 + device pci 19.1 on end # I2C5 0xA0C6 + device pci 19.2 on end # UART2 0xA0C7 + + device pci 1c.0 on end # RP1 0xA0B8 + device pci 1c.1 on end # RP2 0xA0B9 + device pci 1c.2 on end # RP3 0xA0BA + device pci 1c.3 on end # RP4 0xA0BB + device pci 1c.4 on end # RP5 0xA0BC + device pci 1c.5 on end # RP6 0xA0BD + device pci 1c.6 on end # RP7 0xA0BE + device pci 1c.7 on end # RP8 0xA0BF + + device pci 1d.0 on end # RP9 0xA0B0 + device pci 1d.1 on end # RP10 0xA0B1 + device pci 1d.2 on end # RP11 0xA0B2 + device pci 1d.3 on end # RP12 0xA0B3 + device pci 1d.4 on end # RP13 0xA0B4 + device pci 1d.5 on end # RP14 0xA0B5 + device pci 1d.6 on end # RP15 0xA0B6 + device pci 1d.7 on end # RP16 0xA0B7 + + device pci 1e.0 on end # UART0 0xA0A8 + device pci 1e.1 on end # UART1 0xA0A9 + device pci 1e.2 on end # GSPI0 0xA0AA + device pci 1e.3 on end # GSPI1 0xA0AB + + device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.1 on end # P2SB 0xA0A0 + device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF + device pci 1f.4 on end # SMBus 0xA0A3 + device pci 1f.5 on end # SPI 0xA0A4 + device pci 1f.6 off end # GbE 0x15E1/0x15E2 + device pci 1f.7 on end # TH 0xA0A6 + end +end diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/gpio.c b/src/mainboard/intel/tglrvp/variants/baseboard/gpio.c new file mode 100644 index 0000000..ba44852 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/gpio.c @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + +/* M.2 Key-E - WLAN/BT */ +PAD_CFG_GPO(GPP_A13 , 1, PLTRST), +PAD_CFG_GPO(GPP_B15 , 1, PLTRST), +PAD_CFG_GPO(GPP_C22 , 1, PLTRST), +PAD_CFG_GPI_SCI(GPP_C23 , NONE, DEEP, LEVEL, INVERT), +PAD_CFG_GPI_SCI(GPP_H19 , NONE, DEEP, LEVEL, INVERT), +PAD_CFG_GPI(GPP_A10, NONE, PLTRST), + +/* FSP */ +PAD_CFG_GPO(GPP_B14, 1, PLTRST), +PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), + +/* PCH M.2 SSD */ +PAD_CFG_GPO(GPP_B16, 1, PLTRST), +PAD_CFG_GPO(GPP_H0 , 1, PLTRST), + +/* Camera */ +PAD_CFG_GPO(GPP_B23, 0, PLTRST), +PAD_CFG_GPO(GPP_C15, 0, PLTRST), + +PAD_CFG_GPO(GPP_R6 , 0, PLTRST), +PAD_CFG_GPO(GPP_H12, 0, PLTRST), + +/* Audio */ +PAD_CFG_GPO(GPP_C5 , 1, PLTRST), +PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /*GPP_C12 as AUDIO JACK IRQ*/ +/* Touch Pad */ +PAD_CFG_GPO(GPP_H1 , 1, PLTRST), +PAD_CFG_GPI_APIC(GPP_C8 , NONE, PLTRST, EDGE_SINGLE, INVERT), + +/* EC */ +PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, LEVEL, INVERT), +PAD_CFG_GPO(GPP_E8 , 1, PLTRST), + +/* SPI TPM */ +PAD_CFG_GPI_SCI(GPP_C14 , NONE, DEEP, LEVEL, INVERT), + +/* TypeC BIAS : Not used by default in RVP, derived from ICL */ +PAD_CFG_GPO(GPP_E22 , 0, PLTRST), +PAD_CFG_GPO(GPP_E23 , 1, PLTRST), + +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + +#if defined(WWAN_ON) +PAD_CFG_GPO(GPP_H23, 1, RSMRST), +PAD_CFG_GPO(GPP_C11, 1, RSMRST), +PAD_CFG_GPO(GPP_C10, 1, RSMRST), +PAD_CFG_GPO(GPP_B17, 0, RSMRST), +PAD_CFG_GPI_SCI(GPP_C9 , NONE, DEEP, LEVEL, INVERT), +PAD_CFG_GPO(GPP_D15, 1, RSMRST), +#else +PAD_CFG_GPO(GPP_C10, 0, RSMRST), +PAD_CFG_GPO(GPP_B17, 0, RSMRST), +PAD_CFG_GPO(GPP_C11, 0, RSMRST), +#endif + +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..7e9d99e --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <variant/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid, power button or mode change event */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */ + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..227ec75 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..68dbf84 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ + +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +const struct cros_gpio *variant_cros_gpios(size_t *num); + +struct memory_config { + const void *dq_map; + size_t dq_map_size; + const void *dqs_map; + size_t dqs_map_size; + u16 rcomp_resistor; + const void *rcomp_target; + size_t rcomp_target_size; +}; + +size_t variant_memory_sku(void); +void variant_memory_params(struct memory_config *mem_config); + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/mainboard.c b/src/mainboard/intel/tglrvp/variants/baseboard/mainboard.c new file mode 100644 index 0000000..9b529c6 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/mainboard.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <device/device.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <smbios.h> +#include <variant/gpio.h> + +#define SKU_UNKNOWN 0xFFFFFFFF +#define SKU_MAX 255 +#if 0 +static uint32_t get_board_sku(void) +{ + static uint32_t sku_id = SKU_UNKNOWN; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + sku_id = SKU_UNKNOWN; + + return sku_id; +} +#endif +const char *smbios_system_sku(void) +{ + static char sku_str[7] = ""; /* sku{0..255} */ + +#if CONFIG(BOARD_INTEL_TIGERLAKE_RVPU) + uint32_t sku_id = 255; +#else + uint32_t sku_id = 1; +#endif +#if 0 + if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) { + printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", + __func__, sku_id); + return ""; + } +#endif + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + + return sku_str; +} + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +static unsigned long mainboard_write_acpi_tables(struct device *device, + unsigned long current, + acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + + start_addr = current; + + return start_addr; +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/memory.c b/src/mainboard/intel/tglrvp/variants/baseboard/memory.c new file mode 100644 index 0000000..281d313 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/memory.c @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <intelblocks/mp_init.h> +#include <variant/gpio.h> + +size_t __weak variant_memory_sku(void) +{ + return 0; +} + +#ifdef CONFIG_BOARD_LPDDR4 +/* DQ byte map */ +static const u8 dq_map[8][2][8] = { + //Controller 0 + {{ 0, 1, 6, 7, 3, 2, 5, 4 }, // Byte 0 + { 15, 8, 9, 14, 12, 11, 10, 13 }}, // Byte 1 + {{ 11, 12, 8, 15, 9, 14, 10, 13 }, // Byte 2 + { 3, 4, 7, 0, 6, 1, 5, 2 }}, // Byte 3 + {{ 4, 5, 3, 2, 7, 1, 0, 6 }, // Byte 4 + { 11, 10, 12, 13, 8, 9, 14, 15 }}, // Byte 5 + {{ 12, 11, 8, 13, 14, 15, 9, 10 }, // Byte 6 + { 4, 7, 3, 2, 1, 6, 0, 5 }}, // Byte 7 + //Controller 1 + {{ 11, 10, 9, 8, 12, 13, 15, 14 }, // Byte 0 ChB! + { 4, 5, 6, 7, 3, 2, 0, 1 }}, // Byte 1 ChB! + {{ 0, 7, 1, 6, 3, 5, 2, 4 }, // Byte 2 + { 9, 8, 10, 11, 14, 15, 13, 12 }}, // Byte 3 + {{ 4, 5, 6, 1, 3, 2, 7, 0 }, // Byte 4 + { 10, 13, 12, 11, 14, 9, 15, 8 }}, // Byte 5 + {{ 10, 12, 9, 15, 8, 11, 13, 14 }, // Byte 6 + { 3, 4, 1, 2, 6, 0, 5, 7 }} // Byte 7 + }; + +/* DQS CPU<>DRAM map */ +static const u8 dqs_map[8][2] = { + // Ch 0 1 2 3 + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, // Controller 0 + { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } // Controller 1 + }; +#else +/* DQ byte map */ +static const u8 dq_map[8][2][8] = { + //Controller 0 + {{ 13, 12, 14, 15, 11, 8, 9, 10 }, // Byte 0 + { 2, 3, 1, 0, 7, 4, 5, 6 }}, // Byte 1 + {{ 11, 12, 13, 10, 14, 8, 15, 9 }, // Byte 2 + { 2, 3, 1, 0, 6, 5, 7, 4 }}, // Byte 3 + {{ 15, 14, 12, 13, 11, 10, 8, 9 }, // Byte 4 + { 0, 1, 2, 3, 4, 7, 6, 5 }}, // Byte 5 + {{ 12, 13, 11, 10, 9, 15, 8, 14 }, // Byte 6 + { 2, 3, 0, 1, 5, 4, 7, 6 }}, // Byte 7 + //Controller 1 + {{ 15, 14, 13, 12, 10, 8, 9, 11 }, // Byte 0 + { 0, 1, 2, 3, 7, 4, 5, 6 }}, // Byte 1 + {{ 15, 14, 11, 10, 13, 12, 8, 9 }, // Byte 2 + { 1, 7, 0, 6, 3, 5, 2, 4 }}, // Byte 3 + {{ 15, 14, 13, 12, 9, 10, 11, 8 }, // Byte 4 + { 0, 1, 7, 6, 3, 2, 5, 4 }}, // Byte 5 + {{ 4, 3, 5, 2, 6, 7, 0, 1 }, // Byte 6 + { 15, 14, 10, 11, 12, 9, 8, 13 }} // Byte 7 +}; + +/* DQS CPU<>DRAM map */ +static const u8 dqs_map[8][2] = { + // Ch 0 1 2 3 + { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, //controller 0 + { 1, 0 }, { 1, 0 }, { 1, 0 }, { 0, 1 } //controller 1 +}; +#endif + +/* Rcomp resistor */ +static const u16 rcomp_resistor = 100; + +/* Rcomp target */ +static const u16 RcompTarget[] = { 60, 40, 40, 40, 30 }; + +void __weak variant_memory_params(struct memory_config *mem_config) +{ + + mem_config->dq_map = dq_map; + mem_config->dq_map_size = sizeof(dq_map); + mem_config->dqs_map = dqs_map; + mem_config->dqs_map_size = sizeof(dqs_map); + mem_config->rcomp_resistor = rcomp_resistor; + mem_config->rcomp_target = RcompTarget; + mem_config->rcomp_target_size = sizeof(RcompTarget); +} + diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc new file mode 100644 index 0000000..8ded117 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +## Memory Options +SPD_SOURCES = Micron-MT53D1G64D8SQ-046 +SPD_SOURCES += Samsung-K4UBE3D4AA-MGCL +SPD_SOURCES += Hynix-H9HKNNNEBMAV-4267 + diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/ec.h b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/ec.h new file mode 100644 index 0000000..a6d49aa --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/gpio.h b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/gpio.h new file mode 100644 index 0000000..97c7113 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#endif /* __MAINBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1649e80b21a3811841a9c7f14f15d5684f1edc99 Gerrit-Change-Number: 37437 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
by Furquan Shaikh (Code Review) 03 Dec '19

03 Dec '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37319 ) Change subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Tue, 03 Dec 2019 06:53:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include JasperLake SA IDs
by Ronak Kanabar (Code Review) 03 Dec '19

03 Dec '19

Ronak Kanabar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37246 ) Change subject: soc/intel/common: Include JasperLake SA IDs ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/37246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I207a264e5442c2481e3d53920dd6e40b38abb716 Gerrit-Change-Number: 37246 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/common: Include JasperLake CPU IDs
by Ronak Kanabar (Code Review) 03 Dec '19

03 Dec '19

Ronak Kanabar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37245 ) Change subject: soc/intel/common: Include JasperLake CPU IDs ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/37245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22103aa06b2ea7a0d1006121401c4ca33877677e Gerrit-Change-Number: 37245 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
by Subrata Banik (Code Review) 03 Dec '19

03 Dec '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37319 ) Change subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/c/coreboot/+/37319/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37319/8//COMMIT_MSG@11 PS8, Line 11: 2. Avoid redundent definitions of soc_fill_gpio_pm_configuration > nit: This wasn't really true before the change was made. :). […] Done https://review.coreboot.org/c/coreboot/+/37319/8/src/soc/intel/cannonlake/i… File src/soc/intel/cannonlake/include/soc/gpio.h: https://review.coreboot.org/c/coreboot/+/37319/8/src/soc/intel/cannonlake/i… PS8, Line 33: rotine > nit: routine Done -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Tue, 03 Dec 2019 06:16:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
by Subrata Banik (Code Review) 03 Dec '19

03 Dec '19

Hello Patrick Rudolph, EricR Lai, Selma Bensaid, Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37319 to look at the new patch set (#10). Change subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock ...................................................................... soc/intel/cannonlake: Configure GPIO PM configuration in bootblock This patch performs below operations: 1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration 2. Move soc_gpio_pm_configuration() to gpio_common.c 3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration is updated with devicetree.cb value even with platform reset. BUG=b:144002424 TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/chip.c A src/soc/intel/cannonlake/gpio_common.c M src/soc/intel/cannonlake/include/soc/gpio.h 5 files changed, 53 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37319/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
by Subrata Banik (Code Review) 03 Dec '19

03 Dec '19

Hello Patrick Rudolph, EricR Lai, Selma Bensaid, Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37319 to look at the new patch set (#9). Change subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock ...................................................................... soc/intel/cannonlake: Configure GPIO PM configuration in bootblock This patch performs below operations: 1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration 2. Move soc_gpio_pm_configuration() to gpio_common.c 3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration is updated with devicetree.cb value even with platform reset. BUG=b:144002424 TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/chip.c A src/soc/intel/cannonlake/gpio_common.c M src/soc/intel/cannonlake/include/soc/gpio.h 5 files changed, 53 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37319/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: include: introduce update* for mmio operations
by Julius Werner (Code Review) 03 Dec '19

03 Dec '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36596 ) Change subject: include: introduce update* for mmio operations ...................................................................... Patch Set 5: Uploaded my suggestion as CB:37432 and CB:37433 -- To view, visit https://review.coreboot.org/c/coreboot/+/36596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f188d586c09ee9f1e17290563f68970603204fb Gerrit-Change-Number: 36596 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Dec 2019 06:11:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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