coreboot-gerrit December 2019

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Change in coreboot[master]: lib/imd_cbmem: Rename imd_cbmem into imd, use directly
by Patrick Georgi (Code Review) 03 Dec '19

03 Dec '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37363 ) Change subject: lib/imd_cbmem: Rename imd_cbmem into imd, use directly ...................................................................... lib/imd_cbmem: Rename imd_cbmem into imd, use directly Change-Id: I70e9d9f769831087becbf42dcfb774d8f2638770 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/lib/imd_cbmem.c 1 file changed, 12 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/37363/1 diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index c3204e2..3dc9058 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -27,6 +27,8 @@ has to fill in the _cbmem_top_ptr symbol based on the calling arguments. */ uintptr_t _cbmem_top_ptr; +static struct imd imd; + void *cbmem_top(void) { if (ENV_ROMSTAGE) { @@ -42,9 +44,6 @@ dead_code(); } - -static struct imd imd_cbmem; - static inline const struct cbmem_entry *imd_to_cbmem(const struct imd_entry *e) { return (const struct cbmem_entry *)e; @@ -74,12 +73,11 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size) { - struct imd *imd = &imd_cbmem; const int no_recovery = 0; cbmem_top_init_once(); - imd_handle_init(imd, cbmem_top()); + imd_handle_init(&imd, cbmem_top()); printk(BIOS_DEBUG, "CBMEM:\n"); @@ -104,12 +102,11 @@ int cbmem_initialize_id_size(u32 id, u64 size) { - struct imd *imd = &imd_cbmem; const int recovery = 1; cbmem_top_init_once(); - imd_handle_init(imd, cbmem_top()); + imd_handle_init(&imd, cbmem_top()); if (imd_recover(imd)) return 1; @@ -145,20 +142,18 @@ const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64) { - struct imd *imd = &imd_cbmem; const struct imd_entry *e; - e = imd_entry_find_or_add(imd, id, size64); + e = imd_entry_find_or_add(&imd, id, size64); return imd_to_cbmem(e); } void *cbmem_add(u32 id, u64 size) { - struct imd *imd = &imd_cbmem; const struct imd_entry *e; - e = imd_entry_find_or_add(imd, id, size); + e = imd_entry_find_or_add(&imd, id, size); if (e == NULL) return NULL; @@ -169,20 +164,18 @@ /* Retrieve a region provided a given id. */ const struct cbmem_entry *cbmem_entry_find(u32 id) { - struct imd *imd = &imd_cbmem; const struct imd_entry *e; - e = imd_entry_find(imd, id); + e = imd_entry_find(&imd, id); return imd_to_cbmem(e); } void *cbmem_find(u32 id) { - struct imd *imd = &imd_cbmem; const struct imd_entry *e; - e = imd_entry_find(imd, id); + e = imd_entry_find(&imd, id); if (e == NULL) return NULL; @@ -194,23 +187,17 @@ * cannot be removed unless it was the last one added. */ int cbmem_entry_remove(const struct cbmem_entry *entry) { - struct imd *imd = &imd_cbmem; - - return imd_entry_remove(imd, cbmem_to_imd(entry)); + return imd_entry_remove(&imd, cbmem_to_imd(entry)); } u64 cbmem_entry_size(const struct cbmem_entry *entry) { - struct imd *imd = &imd_cbmem; - - return imd_entry_size(imd, cbmem_to_imd(entry)); + return imd_entry_size(&imd, cbmem_to_imd(entry)); } void *cbmem_entry_start(const struct cbmem_entry *entry) { - struct imd *imd = &imd_cbmem; - - return imd_entry_at(imd, cbmem_to_imd(entry)); + return imd_entry_at(&imd, cbmem_to_imd(entry)); } void cbmem_add_bootmem(void) @@ -237,9 +224,8 @@ void cbmem_list(void) { static const struct imd_lookup lookup[] = { CBMEM_ID_TO_NAME_TABLE }; - struct imd *imd = &imd_cbmem; - imd_print_entries(imd, lookup, ARRAY_SIZE(lookup)); + imd_print_entries(&imd, lookup, ARRAY_SIZE(lookup)); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70e9d9f769831087becbf42dcfb774d8f2638770 Gerrit-Change-Number: 37363 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/imd_cbmem: Remove the indirections that hide imd_cbmem
by Patrick Georgi (Code Review) 03 Dec '19

03 Dec '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37362 ) Change subject: lib/imd_cbmem: Remove the indirections that hide imd_cbmem ...................................................................... lib/imd_cbmem: Remove the indirections that hide imd_cbmem Change-Id: Ie68c6e2ebe56a5902a7665bf62119302146f5928 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/lib/imd_cbmem.c 1 file changed, 10 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/37362/1 diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 4172fa4..c3204e2 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -55,32 +55,6 @@ return (const struct imd_entry *)e; } -/* These are the different situations to handle: - * - * In ramstage cbmem_initialize() attempts a recovery of the - * cbmem region set up by romstage. It uses cbmem_top() as the - * starting point of recovery. - * - * In romstage, similar to ramstage, cbmem_initialize() needs to - * attempt recovery of the cbmem area using cbmem_top() as the limit. - * cbmem_initialize_empty() initializes an empty cbmem area from - * cbmem_top(); - * - */ -static struct imd *imd_init_backing(struct imd *backing) -{ - return &imd_cbmem; -} - -static struct imd *imd_init_backing_with_recover(struct imd *backing) -{ - struct imd *imd; - - imd = imd_init_backing(backing); - - return imd; -} - void cbmem_initialize_empty(void) { cbmem_initialize_empty_id_size(0, 0); @@ -100,13 +74,11 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const int no_recovery = 0; cbmem_top_init_once(); - imd = imd_init_backing(&imd_backing); imd_handle_init(imd, cbmem_top()); printk(BIOS_DEBUG, "CBMEM:\n"); @@ -132,13 +104,11 @@ int cbmem_initialize_id_size(u32 id, u64 size) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const int recovery = 1; cbmem_top_init_once(); - imd = imd_init_backing(&imd_backing); imd_handle_init(imd, cbmem_top()); if (imd_recover(imd)) @@ -175,12 +145,9 @@ const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const struct imd_entry *e; - imd = imd_init_backing_with_recover(&imd_backing); - e = imd_entry_find_or_add(imd, id, size64); return imd_to_cbmem(e); @@ -188,12 +155,9 @@ void *cbmem_add(u32 id, u64 size) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const struct imd_entry *e; - imd = imd_init_backing_with_recover(&imd_backing); - e = imd_entry_find_or_add(imd, id, size); if (e == NULL) @@ -205,12 +169,9 @@ /* Retrieve a region provided a given id. */ const struct cbmem_entry *cbmem_entry_find(u32 id) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const struct imd_entry *e; - imd = imd_init_backing_with_recover(&imd_backing); - e = imd_entry_find(imd, id); return imd_to_cbmem(e); @@ -218,12 +179,9 @@ void *cbmem_find(u32 id) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const struct imd_entry *e; - imd = imd_init_backing_with_recover(&imd_backing); - e = imd_entry_find(imd, id); if (e == NULL) @@ -236,30 +194,21 @@ * cannot be removed unless it was the last one added. */ int cbmem_entry_remove(const struct cbmem_entry *entry) { - struct imd *imd; - struct imd imd_backing; - - imd = imd_init_backing_with_recover(&imd_backing); + struct imd *imd = &imd_cbmem; return imd_entry_remove(imd, cbmem_to_imd(entry)); } u64 cbmem_entry_size(const struct cbmem_entry *entry) { - struct imd *imd; - struct imd imd_backing; - - imd = imd_init_backing_with_recover(&imd_backing); + struct imd *imd = &imd_cbmem; return imd_entry_size(imd, cbmem_to_imd(entry)); } void *cbmem_entry_start(const struct cbmem_entry *entry) { - struct imd *imd; - struct imd imd_backing; - - imd = imd_init_backing_with_recover(&imd_backing); + struct imd *imd = &imd_cbmem; return imd_entry_at(imd, cbmem_to_imd(entry)); } @@ -288,10 +237,8 @@ void cbmem_list(void) { static const struct imd_lookup lookup[] = { CBMEM_ID_TO_NAME_TABLE }; - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; - imd = imd_init_backing_with_recover(&imd_backing); imd_print_entries(imd, lookup, ARRAY_SIZE(lookup)); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie68c6e2ebe56a5902a7665bf62119302146f5928 Gerrit-Change-Number: 37362 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/imd_cbmem: &imd_cbmem is never NULL, so remove that path
by Patrick Georgi (Code Review) 03 Dec '19

03 Dec '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37361 ) Change subject: lib/imd_cbmem: &imd_cbmem is never NULL, so remove that path ...................................................................... lib/imd_cbmem: &imd_cbmem is never NULL, so remove that path Change-Id: Ib9a9c88d6cd4842df447f046bc0abaa7ef5032c7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/lib/imd_cbmem.c 1 file changed, 1 insertion(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/37361/1 diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index d7f7d20..4172fa4 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -69,16 +69,7 @@ */ static struct imd *imd_init_backing(struct imd *backing) { - struct imd *imd; - - imd = &imd_cbmem; - - if (imd != NULL) - return imd; - - imd = backing; - - return imd; + return &imd_cbmem; } static struct imd *imd_init_backing_with_recover(struct imd *backing) -- To view, visit https://review.coreboot.org/c/coreboot/+/37361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a9c88d6cd4842df447f046bc0abaa7ef5032c7 Gerrit-Change-Number: 37361 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add JasperLake Device IDs
by Paul Menzel (Code Review) 03 Dec '19

03 Dec '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37434 ) Change subject: soc/intel/common: Add JasperLake Device IDs ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/c/coreboot/+/37434/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37434/1//COMMIT_MSG@7 PS1, Line 7: JasperLake Jasper Lake https://review.coreboot.org/c/coreboot/+/37434/1//COMMIT_MSG@9 PS1, Line 9: JasperLake Ditto. -- To view, visit https://review.coreboot.org/c/coreboot/+/37434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117 Gerrit-Change-Number: 37434 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Dec 2019 12:21:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: soc/intel/broadwell_de: Re-read SPD on CRC error
by Paul Menzel (Code Review) 03 Dec '19

03 Dec '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37303 ) Change subject: soc/intel/broadwell_de: Re-read SPD on CRC error ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/romstage/memory.c: https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… PS2, Line 68: "SPD CRC error, channel %u slot %u\n", Please add the iteration. https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… PS2, Line 72: } while (tries-- && res == SPD_STATUS_CRC_ERROR); How much time does each try add to the boot time? Could you time it using the stopwatch frame work and add that, if it’s more than 1 ms? https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… PS2, Line 76: } Please print an error with error string, stating that the SMBIOS data is not added, but it should still work. -- To view, visit https://review.coreboot.org/c/coreboot/+/37303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Gerrit-Change-Number: 37303 Gerrit-PatchSet: 2 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Dec 2019 12:04:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/broadwell: Setup gpio in bootblock
by Paul Menzel (Code Review) 03 Dec '19

03 Dec '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36713 ) Change subject: soc/intel/broadwell: Setup gpio in bootblock ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/36713/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/36713/5//COMMIT_MSG@7 PS5, Line 7: Setup Set up -- To view, visit https://review.coreboot.org/c/coreboot/+/36713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8c70f61a7ed208bbf90cfe6244406ef375f4112 Gerrit-Change-Number: 36713 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Dec 2019 11:56:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: hatch: Create stryke variant
by Dtrain Hsu (Code Review) 03 Dec '19

03 Dec '19

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37229 ) Change subject: hatch: Create stryke variant ...................................................................... hatch: Create stryke variant (Auto-Generated by create_coreboot_variant.sh version 1.0.0). BUG=b:145101696 TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_STRYKE Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Iea6f8a1c6c24a1e3545c364551cb623debdc4a1a --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/stryke/Makefile.inc A src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/stryke/include/variant/ec.h A src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h A src/mainboard/google/hatch/variants/stryke/overridetree.cb 7 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/37229/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index d6e6e46..8be340e 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -96,6 +96,7 @@ default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Puff" if BOARD_GOOGLE_PUFF + default "Stryke" if BOARD_GOOGLE_STRYKE config MAINBOARD_VENDOR string @@ -125,6 +126,7 @@ default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "puff" if BOARD_GOOGLE_PUFF + default "stryke" if BOARD_GOOGLE_STRYKE config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 82da883..ed90de6 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -50,3 +50,8 @@ select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 + +config BOARD_GOOGLE_STRYKE + bool "-> Stryke" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 diff --git a/src/mainboard/google/hatch/variants/stryke/Makefile.inc b/src/mainboard/google/hatch/variants/stryke/Makefile.inc new file mode 100644 index 0000000..38cf728 --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/Makefile.inc @@ -0,0 +1,13 @@ +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..496334d --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h b/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h new file mode 100644 index 0000000..2526962 --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h b/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h new file mode 100644 index 0000000..3b07c1b --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + +#endif diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb new file mode 100644 index 0000000..abbcaaa --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/cannonlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/37229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea6f8a1c6c24a1e3545c364551cb623debdc4a1a Gerrit-Change-Number: 37229 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Add missing include <stdlib.h>
by HAOUAS Elyes (Code Review) 03 Dec '19

03 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37366 ) Change subject: src: Add missing include <stdlib.h> ...................................................................... src: Add missing include <stdlib.h> Also use <types.h> when <stdint.h> and <stddef.h> are needed. Also add some missing includes spotted by Jenkins. Change-Id: I17dc2fed6c6518daf5af286788c98c049088911e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/storage/bouncebuf.c M src/commonlib/storage/sdhci.c M src/commonlib/storage/sdhci_adma.c M src/device/oprom/yabel/vbe.c M src/lib/fit_payload.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/soc/amd/common/block/spi/fch_spi_flash.c M src/soc/intel/broadwell/me.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/smbios.c M src/soc/intel/quark/i2c.c M src/soc/intel/skylake/elog.c M src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c M src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c M src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c M src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c 18 files changed, 42 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/37366/1 diff --git a/src/commonlib/storage/bouncebuf.c b/src/commonlib/storage/bouncebuf.c index 99287b6..6244896 100644 --- a/src/commonlib/storage/bouncebuf.c +++ b/src/commonlib/storage/bouncebuf.c @@ -15,10 +15,13 @@ */ #include <arch/cache.h> +#include <commonlib/stdlib.h> +#include <stdlib.h> +#include <string.h> +#include <types.h> + #include "bouncebuf.h" #include "storage.h" -#include <string.h> -#include <commonlib/stdlib.h> static int addr_aligned(struct bounce_buffer *state) { diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 25c0d6f1e..25d0f2f 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -14,17 +14,20 @@ * Secure Digital (SD) Host Controller interface specific code */ -#include "bouncebuf.h" #include <commonlib/sd_mmc_ctrlr.h> #include <commonlib/sdhci.h> #include <commonlib/storage.h> #include <delay.h> #include <endian.h> +#include <timer.h> +#include <commonlib/stdlib.h> +#include <stdlib.h> +#include <types.h> + +#include "bouncebuf.h" #include "sdhci.h" #include "sd_mmc.h" #include "storage.h" -#include <timer.h> -#include <commonlib/stdlib.h> #define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \ || (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_VERSTAGE) \ diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index 2806bde..7738afb 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -19,6 +19,8 @@ #include <console/console.h> #include <delay.h> #include <endian.h> +#include <stdlib.h> +#include <stdint.h> #include <string.h> #include "sdhci.h" diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index a3d736f..7d1ea59 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -34,6 +34,7 @@ #include <boot/coreboot_tables.h> #include <string.h> +#include <stdlib.h> #include <types.h> #include <endian.h> diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 1b6c986..ccb84f4 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -19,12 +19,13 @@ #include <bootmem.h> #include <cbmem.h> #include <device/resource.h> -#include <stdlib.h> #include <commonlib/region.h> #include <fit.h> #include <program_loading.h> #include <timestamp.h> +#include <stdlib.h> #include <string.h> +#include <types.h> #include <commonlib/cbfs_serialized.h> #include <commonlib/compression.h> #include <lib.h> diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 580e09a..50123f9 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -12,6 +12,7 @@ */ #include <endian.h> +#include <stdlib.h> #include <string.h> #include <smbios.h> #include <console/console.h> diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 7f59d91..0deaff6 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -21,10 +21,12 @@ #include <cpu/x86/cache.h> #include <delay.h> #include <lib.h> +#include <spd.h> +#include <stdlib.h> +#include <string.h> + #include "pineview.h" #include "raminit.h" -#include <spd.h> -#include <string.h> /* Debugging macros. */ #if CONFIG(DEBUG_RAM_SETUP) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4974173..26338d6 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -23,6 +23,7 @@ #include <northbridge/intel/sandybridge/chip.h> #include <device/pci_def.h> #include <delay.h> +#include <stdlib.h> #include "raminit_native.h" #include "raminit_common.h" diff --git a/src/soc/amd/common/block/spi/fch_spi_flash.c b/src/soc/amd/common/block/spi/fch_spi_flash.c index 40dd0e2..5942e77 100644 --- a/src/soc/amd/common/block/spi/fch_spi_flash.c +++ b/src/soc/amd/common/block/spi/fch_spi_flash.c @@ -19,6 +19,7 @@ #include <amdblocks/fch_spi.h> #include <drivers/spi/spi_flash_internal.h> #include <timer.h> +#include <stdlib.h> #include <string.h> static void spi_flash_addr(u32 addr, u8 *cmd) diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 0021d2c..774f2bc 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -39,7 +39,7 @@ #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/intel/broadwell/chip.h> - +#include <stdlib.h> #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 0a43442..2f86940 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -19,8 +19,10 @@ #include <intelblocks/fast_spi.h> #include <soc/pci_devs.h> #include <spi_flash.h> +#include <stdlib.h> #include <string.h> #include <timer.h> +#include <types.h> /* Helper to create a FAST_SPI context on API entry. */ #define BOILERPLATE_CREATE_CTX(ctx) \ diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index d315e15..a468abb 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -13,11 +13,14 @@ * GNU General Public License for more details. */ -#include <smbios.h> -#include "smbios.h" -#include <string.h> #include <console/console.h> #include <device/dram/ddr3.h> +#include <smbios.h> +#include <stdlib.h> +#include <string.h> +#include <types.h> + +#include "smbios.h" /* Fill the SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.*/ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index b09852b..ad6418f 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -22,6 +22,8 @@ #include <soc/i2c.h> #include <soc/ramstage.h> #include <soc/reg_access.h> +#include <stdint.h> +#include <stdlib.h> #include <timer.h> static void i2c_disable(I2C_REGS *regs) diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 7951394..7871d7d 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -20,6 +20,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <stdint.h> +#include <stdlib.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <intelblocks/xhci.h> diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c index e078e74..cc6a5dd 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c @@ -12,6 +12,7 @@ #include <bdk.h> #include <libbdk-hal/bdk-config.h> +#include <stdlib.h> #include <string.h> #include <assert.h> #include <lame_string.h> diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c index b9552d4..810a0ed 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c @@ -37,7 +37,9 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include <bdk.h> +#include <stdlib.h> #include <string.h> + #include "libbdk-arch/bdk-csrs-gser.h" #include "libbdk-arch/bdk-csrs-gsern.h" #include "libbdk-hal/if/bdk-if.h" diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c index 0df70eb..ed003dc 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c @@ -36,8 +36,11 @@ * QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ + #include <bdk.h> #include <string.h> +#include <stdlib.h> + #include "libbdk-arch/bdk-csrs-ap.h" #include "libbdk-arch/bdk-csrs-pccpf.h" #include "libbdk-hal/bdk-ecam.h" diff --git a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c index 291fe85..445ada8 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c @@ -40,6 +40,7 @@ #include "dram-internal.h" #include <string.h> +#include <stdlib.h> #include <lame_string.h> /* for strtoul */ #include <libbdk-hal/bdk-atomic.h> #include <libbdk-hal/bdk-clock.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17dc2fed6c6518daf5af286788c98c049088911e Gerrit-Change-Number: 37366 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/google/drallion: Disable GPIO dynamic PM configuration
by Patrick Georgi (Code Review) 03 Dec '19

03 Dec '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37320 ) Change subject: mb/google/drallion: Disable GPIO dynamic PM configuration ...................................................................... mb/google/drallion: Disable GPIO dynamic PM configuration BUG=b:144002424 TEST=Ensured no TPM time out issue and system can boot to OS Change-Id: I7282e6c2d9627846039638bdc0db3ee7ebba5f12 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37320 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb 3 files changed, 21 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb index 5f396fe..11abc87 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb @@ -212,11 +212,13 @@ register "gpio_override_pm" = "1" # GPIO community PM configuration - register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" - register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + # Disable dynamic clock gating; with bits 0-5 set in these registers, + # some short interrupt pulses were missed (esp. cr50 irq) + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 4c5cff2..2fcf191 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -209,15 +209,13 @@ register "gpio_override_pm" = "1" # GPIO community PM configuration - register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | - MISCCFG_GPRTCDLCGEN | - MISCCFG_GSXSLCGEN | - MISCCFG_GPDPCGEN | - MISCCFG_GPDLCGEN" - register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + # Disable dynamic clock gating; with bits 0-5 set in these registers, + # some short interrupt pulses were missed (esp. cr50 irq) + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index 8cb1aa3..c466637 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -215,11 +215,13 @@ register "gpio_override_pm" = "1" # GPIO community PM configuration - register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" - register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + # Disable dynamic clock gating; with bits 0-5 set in these registers, + # some short interrupt pulses were missed (esp. cr50 irq) + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" device cpu_cluster 0 on device lapic 0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/37320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7282e6c2d9627846039638bdc0db3ee7ebba5f12 Gerrit-Change-Number: 37320 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
by Patrick Georgi (Code Review) 03 Dec '19

03 Dec '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37319 ) Change subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock ...................................................................... soc/intel/cannonlake: Configure GPIO PM configuration in bootblock This patch performs below operations: 1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration 2. Move soc_gpio_pm_configuration() to gpio_common.c 3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration is updated with devicetree.cb value even with platform reset. BUG=b:144002424 TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37319 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/chip.c A src/soc/intel/cannonlake/gpio_common.c M src/soc/intel/cannonlake/include/soc/gpio.h 5 files changed, 53 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 0fcbcd1..c744e99 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -89,6 +89,9 @@ verstage-y += gpio.c endif +bootblock-y += gpio_common.c +ramstage-y += gpio_common.c + ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y) # Not yet in intel-microcode repo #cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-66-*) diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 39433a2..9ad7e86 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -28,6 +28,7 @@ #include <intelblocks/smbus.h> #include <intelblocks/tco.h> #include <soc/bootblock.h> +#include <soc/gpio.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/p2sb.h> @@ -198,4 +199,7 @@ pmc_gpe_init(); enable_rtc_upper_bank(); + + /* GPIO community PM configuration */ + soc_gpio_pm_configuration(); } diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0ce2f1a..2bb1c92 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -23,6 +23,7 @@ #include <intelblocks/xdci.h> #include <romstage_handoff.h> #include <soc/intel/common/vbt.h> +#include <soc/gpio.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -166,22 +167,6 @@ gpio_configure_pads(cfg, num_pads); } -/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ -static void soc_fill_gpio_pm_configuration(void) -{ - uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_soc(); - - if (config->gpio_override_pm) - memcpy(value, config->gpio_pm, sizeof(uint8_t) * - TOTAL_GPIO_COMM); - else - memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * - TOTAL_GPIO_COMM); - - gpio_pm_configure(value, TOTAL_GPIO_COMM); -} - void soc_init_pre_device(void *chip_info) { /* Perform silicon specific init. */ @@ -193,7 +178,7 @@ /* TODO(furquan): Get rid of this workaround once FSP is fixed. */ cnl_configure_pads(NULL, 0); - soc_fill_gpio_pm_configuration(); + soc_gpio_pm_configuration(); } static void pci_domain_set_resources(struct device *dev) diff --git a/src/soc/intel/cannonlake/gpio_common.c b/src/soc/intel/cannonlake/gpio_common.c new file mode 100644 index 0000000..360189a --- /dev/null +++ b/src/soc/intel/cannonlake/gpio_common.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/gpio.h> +#include <soc/soc_chip.h> + +/* + * Routine to perform below operations: + * 1. SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register + * 2. Program GPIO PM configuration based on PM mask and value + */ +void soc_gpio_pm_configuration(void) +{ + uint8_t value[TOTAL_GPIO_COMM]; + const config_t *config = config_of_soc(); + + if (config->gpio_override_pm) + memcpy(value, config->gpio_pm, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + else + memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + + gpio_pm_configure(value, TOTAL_GPIO_COMM); +} diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index e7056eb..efed881 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -28,6 +28,12 @@ #ifndef __ACPI__ struct pad_config; void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads); +/* + * Routine to perform below operations: + * 1. SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register + * 2. Program GPIO PM configuration based on PM mask and value + */ +void soc_gpio_pm_configuration(void); #endif #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2019