coreboot-gerrit December 2019

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Change in coreboot[4.11_branch]: soc/intel/broadwell_de: Re-read SPD on CRC error
by Werner Zeh (Code Review) 02 Dec '19

02 Dec '19

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37303 ) Change subject: soc/intel/broadwell_de: Re-read SPD on CRC error ...................................................................... Patch Set 2: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/romstage/memory.c: https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwel… PS2, Line 58: = SPD_STATUS_OK This is not strictly needed here because res will be assigned a value in line 65 and noone needs it before this line. But it's up to you. -- To view, visit https://review.coreboot.org/c/coreboot/+/37303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Gerrit-Change-Number: 37303 Gerrit-PatchSet: 2 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Dec 2019 05:49:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in em100[master]: Add compatibility mode
by Stefan Reinauer (Code Review) 02 Dec '19

02 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37258 ) Change subject: Add compatibility mode ...................................................................... Add compatibility mode Add a compatibility mode to the em100 tool. Right now coreboot and the Chrome OS build system carry a bunch of work-arounds to produce two sets of images, one for "real SPI chips" and one for use with the EM100Pro. Instead, we can (and should) just recognize these images and have the em100 tool handle them correctly during upload. em100 --compatibility ... does exactly that. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Ie02264facb028841d18ed84680ffa40f45987510 --- M Makefile M em100.c M em100.h A ifd.h A image.c 5 files changed, 251 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/58/37258/1 diff --git a/Makefile b/Makefile index 0b7c217..3bdb103 100644 --- a/Makefile +++ b/Makefile @@ -40,7 +40,7 @@ XZ = xz/xz_crc32.c xz/xz_crc64.c xz/xz_dec_bcj.c xz/xz_dec_lzma2.c xz/xz_dec_stream.c SOURCES = em100.c firmware.c fpga.c hexdump.c sdram.c spi.c system.c trace.c usb.c -SOURCES += curl.c chips.c tar.c $(XZ) +SOURCES += image.c curl.c chips.c tar.c $(XZ) OBJECTS = $(SOURCES:.c=.o) all: dep em100 diff --git a/em100.c b/em100.c index e52222b..abd8415 100644 --- a/em100.c +++ b/em100.c @@ -758,7 +758,8 @@ {"device", 1, 0, 'x'}, {"list-devices", 0, 0, 'l'}, {"update-files", 0, 0, 'U'}, - {"terminal",0 ,0, 'T'}, + {"terminal", 0, 0, 'T'}, + {"compatible", 0, 0, 'C'}, {NULL, 0, 0, 0} }; @@ -787,6 +788,7 @@ " -x|--device EMxxxxxx use EM100pro with serial no EMxxxxxx\n" " -l|--list-devices list all connected EM100pro devices\n" " -U|--update-files update device (chip) and firmware database\n" + " -C|--compatible enable compatibility mode (patch image for EM100Pro)\n" " -D|--debug: print debug information.\n" " -h|--help: this help text\n\n", name); @@ -802,7 +804,7 @@ const char *holdpin = NULL; int do_start = 0, do_stop = 0; int verify = 0, trace = 0, terminal=0; - int debug = 0; + int debug = 0, compatibility = 0; int bus = 0, device = 0; int firmware_is_dpfw = 0; unsigned int serial_number = 0; @@ -810,7 +812,7 @@ unsigned int spi_start_address = 0; const char *voltage = NULL; - while ((opt = getopt_long(argc, argv, "c:d:a:u:rsvtO:F:f:g:S:V:p:Dx:lUhT", + while ((opt = getopt_long(argc, argv, "c:d:a:u:rsvtO:F:f:g:S:V:p:DCx:lUhT", longopts, &idx)) != -1) { switch (opt) { case 'c': @@ -881,6 +883,9 @@ case 'U': update_all_files(); return 0; + case 'C': + compatibility = 1; + break; default: case 'h': usage(argv[0]); @@ -1074,6 +1079,9 @@ return 1; } + if (compatibility) + autocorrect_image(&em100, data, length); + if (spi_start_address) { readback = malloc(maxlen); if (readback == NULL) { diff --git a/em100.h b/em100.h index f0bacf2..448e6bb 100644 --- a/em100.h +++ b/em100.h @@ -196,9 +196,13 @@ #define MB * 1024 * 1024 #define FILENAME_BUFFER_SIZE 1024 +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) char *get_em100_file(const char *name); /* Chips */ int parse_dcfg(chipdesc *chip, TFILE *dcfg); +/* Images */ +int autocorrect_image(struct em100 *em100, char *image, size_t size); + #endif diff --git a/ifd.h b/ifd.h new file mode 100644 index 0000000..dac4edb --- /dev/null +++ b/ifd.h @@ -0,0 +1,50 @@ +/* + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +enum ifd_version { + IFD_VERSION_1, + IFD_VERSION_2, +}; + +enum platform { + PLATFORM_APL, + PLATFORM_CNL, + PLATFORM_GLK, + PLATFORM_ICL, + PLATFORM_SKLKBL, + PLATFORM_TGL, +}; + +enum spi_frequency { + SPI_FREQUENCY_20MHZ = 0, + SPI_FREQUENCY_33MHZ = 1, + SPI_FREQUENCY_48MHZ = 2, + SPI_FREQUENCY_50MHZ_30MHZ = 4, + SPI_FREQUENCY_17MHZ = 6, +}; + +/* flash descriptor */ +typedef struct { + uint32_t flvalsig; + uint32_t flmap0; + uint32_t flmap1; + uint32_t flmap2; +} __attribute__((packed)) fdbar_t; + +/* component section */ +typedef struct { + uint32_t flcomp; + uint32_t flill; + uint32_t flpb; +} __attribute__((packed)) fcba_t; + diff --git a/image.c b/image.c new file mode 100644 index 0000000..138436b --- /dev/null +++ b/image.c @@ -0,0 +1,185 @@ +/* + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include "em100.h" +#include "ifd.h" + +/** + * PTR_IN_RANGE - examine whether a pointer falls in [base, base + limit) + * @param ptr: the non-void* pointer to a single arbitrary-sized object. + * @param base: base address represented with char* type. + * @param limit: upper limit of the legal address. + * + */ +#define PTR_IN_RANGE(ptr, base, limit) \ + ((const char *)(ptr) >= (base) && \ + (const char *)&(ptr)[1] <= (base) + (limit)) + +static int ifd_version; +static int platform = -1; + +static fdbar_t *find_fd(char *image, int size) +{ + int i, found = 0; + + /* Scan for FD signature */ + for (i = 0; i < (size - 4); i += 4) { + if (*(uint32_t *) (image + i) == 0x0FF0A55A) { + found = 1; + break; // signature found. + } + } + + if (!found) { + printf("No Flash Descriptor found in this image\n"); + return NULL; + } + + fdbar_t *fdb = (fdbar_t *) (image + i); + return PTR_IN_RANGE(fdb, image, size) ? fdb : NULL; +} + +static fcba_t *find_fcba(char *image, int size) +{ + fdbar_t *fdb = find_fd(image, size); + if (!fdb) + return NULL; + fcba_t *fcba = (fcba_t *) (image + ((fdb->flmap0 & 0xff) << 4)); + return PTR_IN_RANGE(fcba, image, size) ? fcba : NULL; + +} + +/* + * Some newer platforms have re-defined the FCBA field that was used to + * distinguish IFD v1 v/s v2. Define a list of platforms that we know do not + * have the required FCBA field, but are IFD v2 and return true if current + * platform is one of them. + */ +static int is_platform_ifd_2(void) +{ + static const int ifd_2_platforms[] = { + PLATFORM_GLK, + PLATFORM_CNL, + PLATFORM_ICL, + PLATFORM_TGL, + }; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(ifd_2_platforms); i++) { + if (platform == ifd_2_platforms[i]) + return 1; + } + + return 0; +} + +/* + * There is no version field in the descriptor so to determine + * if this is a new descriptor format we check the hardcoded SPI + * read frequency to see if it is fixed at 20MHz or 17MHz. + */ +static int get_ifd_version_from_fcba(char *image, int size) +{ + int read_freq; + const fcba_t *fcba = find_fcba(image, size); + const fdbar_t *fdb = find_fd(image, size); + if (!fcba || !fdb) + exit(EXIT_FAILURE); + + read_freq = (fcba->flcomp >> 17) & 7; + + switch (read_freq) { + case SPI_FREQUENCY_20MHZ: + return IFD_VERSION_1; + case SPI_FREQUENCY_17MHZ: + case SPI_FREQUENCY_50MHZ_30MHZ: + return IFD_VERSION_2; + default: + fprintf(stderr, "Unknown descriptor version: %d\n", + read_freq); + exit(EXIT_FAILURE); + } +} + +static void check_ifd_version(char *image, int size) +{ + if (is_platform_ifd_2()) + ifd_version = IFD_VERSION_2; + else + ifd_version = get_ifd_version_from_fcba(image, size); +} + +static void set_spi_frequency(char *image, int size, enum spi_frequency freq) +{ + fcba_t *fcba = find_fcba(image, size); + if (!fcba) + exit(EXIT_FAILURE); + + /* clear bits 21-29 */ + fcba->flcomp &= ~0x3fe00000; + /* Read ID and Read Status Clock Frequency */ + fcba->flcomp |= freq << 27; + /* Write and Erase Clock Frequency */ + fcba->flcomp |= freq << 24; + /* Fast Read Clock Frequency */ + fcba->flcomp |= freq << 21; +} + +static void set_em100_mode(struct em100 *em100, char *image, int size) +{ + fcba_t *fcba = find_fcba(image, size); + if (!fcba) + exit(EXIT_FAILURE); + + int freq; + + if (em100->hwversion == 6) { + printf("EM100Pro-G2 can run at full speed.\n"); + return; + } + + switch (ifd_version) { + case IFD_VERSION_1: + freq = SPI_FREQUENCY_20MHZ; + break; + case IFD_VERSION_2: + freq = SPI_FREQUENCY_17MHZ; + break; + default: + freq = SPI_FREQUENCY_17MHZ; + break; + } + + fcba->flcomp &= ~(1 << 30); + set_spi_frequency(image, size, freq); +} + +int autocorrect_image(struct em100 *em100, char *image, size_t size) +{ + printf("Auto-detecting IFD image ... "); + if (find_fd(image, size)) + printf("OK\n"); + else + return 1; /* No support for other image types (yet). */ + + /* Auto-detect IFD version */ + check_ifd_version(image, size); + + /* Set EM100 mode */ + set_em100_mode(em100, image, size); + + return 0; +} -- To view, visit https://review.coreboot.org/c/em100/+/37258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ie02264facb028841d18ed84680ffa40f45987510 Gerrit-Change-Number: 37258 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: AGESA boards: Drop commented out code
by Kyösti Mälkki (Code Review) 02 Dec '19

02 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37409 ) Change subject: AGESA boards: Drop commented out code ...................................................................... AGESA boards: Drop commented out code Change-Id: I9db1147c5e112e5e6832eeece2214fece8aa6b83 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/olivehill/mptable.c M src/mainboard/asrock/imb-a180/mptable.c M src/mainboard/biostar/a68n_5200/mptable.c M src/mainboard/hp/abm/mptable.c 4 files changed, 0 insertions(+), 152 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/37409/1 diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index 75d026e..3054eff 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -99,45 +99,7 @@ outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } -#if 0 - outb(0x0B, 0xCD6); - outb(0x02, 0xCD7); - outb(0x50, 0xCD6); - outb(0x1F, 0xCD7); - - outb(0x48, 0xCD6); - outb(0xF2, 0xCD7); - - //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - - outb(0xED, 0xCD6); - outb(0x17, 0xCD7); - - *(volatile u8 *) (0xFED80D00 + 0x31) = 2; - *(volatile u8 *) (0xFED80D00 + 0x32) = 2; - *(volatile u8 *) (0xFED80D00 + 0x33) = 2; - *(volatile u8 *) (0xFED80D00 + 0x34) = 2; - - *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0x6c) = 1; - *(volatile u8 *) (0xFED80D00 + 0x6E) = 2; - *(volatile u8 *) (0xFED80D00 + 0x6f) = 2; - - *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0; - *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8; - *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0xA6) = 2; - *(volatile u8 *) (0xFED80100 + 0xA6) = 0; - - *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; -#endif /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index a3c8e51..fd4dff7 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -100,45 +100,7 @@ outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } -#if 0 - outb(0x0B, 0xCD6); - outb(0x02, 0xCD7); - outb(0x50, 0xCD6); - outb(0x1F, 0xCD7); - - outb(0x48, 0xCD6); - outb(0xF2, 0xCD7); - - //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - - outb(0xED, 0xCD6); - outb(0x17, 0xCD7); - - *(volatile u8 *) (0xFED80D00 + 0x31) = 2; - *(volatile u8 *) (0xFED80D00 + 0x32) = 2; - *(volatile u8 *) (0xFED80D00 + 0x33) = 2; - *(volatile u8 *) (0xFED80D00 + 0x34) = 2; - - *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0x6c) = 1; - *(volatile u8 *) (0xFED80D00 + 0x6E) = 2; - *(volatile u8 *) (0xFED80D00 + 0x6f) = 2; - - *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0; - *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8; - *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0xA6) = 2; - *(volatile u8 *) (0xFED80100 + 0xA6) = 0; - - *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; -#endif /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c index 75d026e..3054eff 100644 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ b/src/mainboard/biostar/a68n_5200/mptable.c @@ -99,45 +99,7 @@ outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } -#if 0 - outb(0x0B, 0xCD6); - outb(0x02, 0xCD7); - outb(0x50, 0xCD6); - outb(0x1F, 0xCD7); - - outb(0x48, 0xCD6); - outb(0xF2, 0xCD7); - - //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - - outb(0xED, 0xCD6); - outb(0x17, 0xCD7); - - *(volatile u8 *) (0xFED80D00 + 0x31) = 2; - *(volatile u8 *) (0xFED80D00 + 0x32) = 2; - *(volatile u8 *) (0xFED80D00 + 0x33) = 2; - *(volatile u8 *) (0xFED80D00 + 0x34) = 2; - - *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0x6c) = 1; - *(volatile u8 *) (0xFED80D00 + 0x6E) = 2; - *(volatile u8 *) (0xFED80D00 + 0x6f) = 2; - - *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0; - *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8; - *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0xA6) = 2; - *(volatile u8 *) (0xFED80100 + 0xA6) = 0; - - *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; -#endif /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index 75d026e..3054eff 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -99,45 +99,7 @@ outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } -#if 0 - outb(0x0B, 0xCD6); - outb(0x02, 0xCD7); - outb(0x50, 0xCD6); - outb(0x1F, 0xCD7); - - outb(0x48, 0xCD6); - outb(0xF2, 0xCD7); - - //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - - outb(0xED, 0xCD6); - outb(0x17, 0xCD7); - - *(volatile u8 *) (0xFED80D00 + 0x31) = 2; - *(volatile u8 *) (0xFED80D00 + 0x32) = 2; - *(volatile u8 *) (0xFED80D00 + 0x33) = 2; - *(volatile u8 *) (0xFED80D00 + 0x34) = 2; - - *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0x6c) = 1; - *(volatile u8 *) (0xFED80D00 + 0x6E) = 2; - *(volatile u8 *) (0xFED80D00 + 0x6f) = 2; - - *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0; - *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8; - *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0xA6) = 2; - *(volatile u8 *) (0xFED80100 + 0xA6) = 0; - - *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; -#endif /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); -- To view, visit https://review.coreboot.org/c/coreboot/+/37409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9db1147c5e112e5e6832eeece2214fece8aa6b83 Gerrit-Change-Number: 37409 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: AGESA,binaryPI: Remove unused s3_load/save_nvram
by Kyösti Mälkki (Code Review) 02 Dec '19

02 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37408 ) Change subject: AGESA,binaryPI: Remove unused s3_load/save_nvram ...................................................................... AGESA,binaryPI: Remove unused s3_load/save_nvram This is access to BIOSRAM region in ACPIMMIO. While we use the region, we do not use these functions. Change-Id: I39d1ae811cfe23595587ae0fe51c6549ecbaba6c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/hudson.h 4 files changed, 0 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/37408/1 diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index c3a4d41..c5e6c25 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -87,34 +87,4 @@ pci_write_config8(dev, 0x4a, byte); } -int s3_save_nvram_early(u32 dword, int size, int nvram_pos) -{ - int i; - printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } - - return nvram_pos; -} - -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) -{ - u32 data = *old_dword; - int i; - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - data &= ~(0xff << (i * 8)); - data |= inb(BIOSRAM_DATA) << (i *8); - nvram_pos++; - } - *old_dword = data; - printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, - nvram_pos-size); - return nvram_pos; -} - #endif /* _HUDSON_EARLY_SETUP_C_ */ diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 18303fc..4927a3a 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -65,9 +65,6 @@ void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void); -int s3_save_nvram_early(u32 dword, int size, int nvram_pos); -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); - void hudson_enable(struct device *dev); #endif /* HUDSON_H */ diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 34a3513..3453021 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -230,36 +230,6 @@ lpc_wideio_window(base, 16); } -int s3_save_nvram_early(u32 dword, int size, int nvram_pos) -{ - int i; - printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } - - return nvram_pos; -} - -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) -{ - u32 data = *old_dword; - int i; - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - data &= ~(0xff << (i * 8)); - data |= inb(BIOSRAM_DATA) << (i *8); - nvram_pos++; - } - *old_dword = data; - printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, - nvram_pos-size); - return nvram_pos; -} - void hudson_clk_output_48Mhz(void) { u32 ctrl; diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index b24629f..ac35536 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -180,8 +180,6 @@ void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); void hudson_tpm_decode_spi(void); -int s3_save_nvram_early(u32 dword, int size, int nvram_pos); -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); void configure_hudson_uart(void); void hudson_enable(struct device *dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/37408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39d1ae811cfe23595587ae0fe51c6549ecbaba6c Gerrit-Change-Number: 37408 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion: Disable GPIO dynamic PM configuration
by Furquan Shaikh (Code Review) 02 Dec '19

02 Dec '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37320 ) Change subject: mb/google/drallion: Disable GPIO dynamic PM configuration ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7282e6c2d9627846039638bdc0db3ee7ebba5f12 Gerrit-Change-Number: 37320 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Dec 2019 03:24:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
by Furquan Shaikh (Code Review) 02 Dec '19

02 Dec '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37319 ) Change subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock ...................................................................... Patch Set 8: Code-Review+2 (2 comments) https://review.coreboot.org/c/coreboot/+/37319/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37319/8//COMMIT_MSG@11 PS8, Line 11: 2. Avoid redundent definitions of soc_fill_gpio_pm_configuration nit: This wasn't really true before the change was made. :). Maybe "Move soc_gpio_pm_configuration() to gpio_common.c" https://review.coreboot.org/c/coreboot/+/37319/8/src/soc/intel/cannonlake/i… File src/soc/intel/cannonlake/include/soc/gpio.h: https://review.coreboot.org/c/coreboot/+/37319/8/src/soc/intel/cannonlake/i… PS8, Line 33: rotine nit: routine -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Tue, 03 Dec 2019 03:23:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
by Subrata Banik (Code Review) 02 Dec '19

02 Dec '19

Hello Patrick Rudolph, EricR Lai, Selma Bensaid, Bora Guvendik, build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37319 to look at the new patch set (#8). Change subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock ...................................................................... soc/intel/cannonlake: Configure GPIO PM configuration in bootblock This patch performs below operations: 1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration 2. Avoid redundent definitions of soc_fill_gpio_pm_configuration 3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration is updated with devicetree.cb value even with platform reset. BUG=b:144002424 TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/chip.c A src/soc/intel/cannonlake/gpio_common.c M src/soc/intel/cannonlake/include/soc/gpio.h 5 files changed, 53 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37319/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
by Subrata Banik (Code Review) 02 Dec '19

02 Dec '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37319 ) Change subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/37319/4/src/soc/intel/cannonlake/b… File src/soc/intel/cannonlake/bootblock/pch.c: https://review.coreboot.org/c/coreboot/+/37319/4/src/soc/intel/cannonlake/b… PS4, Line 204: Disable GPIO community PM configuration > This is only acting on the devicetree fields. It may no be disabling anything. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Tue, 03 Dec 2019 02:45:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
by Subrata Banik (Code Review) 02 Dec '19

02 Dec '19

Hello Patrick Rudolph, EricR Lai, Selma Bensaid, Bora Guvendik, build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37319 to look at the new patch set (#7). Change subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock ...................................................................... soc/intel/cannonlake: Configure GPIO PM configuration in bootblock This patch performs below operations: 1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration 2. Avoid redundent definitions of soc_fill_gpio_pm_configuration 3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration is updated with devicetree.cb value even with platform reset. BUG=b:144002424 TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/chip.c A src/soc/intel/cannonlake/gpio_common.c M src/soc/intel/cannonlake/include/soc/gpio.h 5 files changed, 55 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37319/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
by Subrata Banik (Code Review) 02 Dec '19

02 Dec '19

Hello Patrick Rudolph, EricR Lai, Selma Bensaid, Bora Guvendik, build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37319 to look at the new patch set (#6). Change subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock ...................................................................... soc/intel/cannonlake: Configure GPIO PM configuration in bootblock This patch performs below operations: 1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration 2. Avoid redundent definitions of soc_fill_gpio_pm_configuration 3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration is updated with devicetree.cb value even with platform reset. BUG=b:144002424 TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/chip.c A src/soc/intel/cannonlake/gpio_common.c M src/soc/intel/cannonlake/include/soc/gpio.h 5 files changed, 56 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37319/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2019