Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37416 )
Change subject: amdblocks/acpimmio: add common functions for AP entry ......................................................................
amdblocks/acpimmio: add common functions for AP entry
Move the stoneyridge implementation of get/set AP entry to the common block.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I9c73940ffe5f735dcd844911361355c384f617b1 --- M src/soc/amd/common/block/acpimmio/biosram.c M src/soc/amd/common/block/include/amdblocks/biosram.h M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/include/soc/northbridge.h D src/soc/amd/stoneyridge/nb_util.c M src/soc/amd/stoneyridge/romstage.c 7 files changed, 18 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/37416/1
diff --git a/src/soc/amd/common/block/acpimmio/biosram.c b/src/soc/amd/common/block/acpimmio/biosram.c index f0a1257..e33f02d 100644 --- a/src/soc/amd/common/block/acpimmio/biosram.c +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -15,6 +15,17 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/biosram.h>
+void *get_ap_entry_ptr(void) +{ + return (void *)biosram_read32(BIOSRAM_AP_ENTRY); +} + +void set_ap_entry_ptr(void *entry) +{ + biosram_write32(BIOSRAM_AP_ENTRY, (uintptr_t)entry); +} + + void backup_top_of_low_cacheable(uintptr_t ramtop) { biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index e2c1eb3..db28310 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -17,10 +17,15 @@ #include <stdint.h>
/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_AP_ENTRY 0xe8 /* 8 bytes */ #define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */
+/* Returns the bootblock C entry point for APs */ +void *get_ap_entry_ptr(void); +/* Used by BSP to store the bootblock entry point for APs */ +void set_ap_entry_ptr(void *entry); /* Saves the UMA size returned by AGESA */ void save_uma_size(uint32_t size); /* Saves the UMA base address returned by AGESA */ diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index f697fc2..1879e31 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -48,7 +48,6 @@ bootblock-y += reset.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c -bootblock-y += nb_util.c bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
romstage-y += BiosCallOuts.c @@ -65,7 +64,6 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c -romstage-y += nb_util.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
verstage-y += gpio.c @@ -75,12 +73,10 @@ verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c -verstage-y += nb_util.c
postcar-y += monotonic_timer.c postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c postcar-y += memmap.c -postcar-y += nb_util.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c
@@ -107,14 +103,12 @@ ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c -ramstage-y += nb_util.c
smm-y += monotonic_timer.c smm-y += smihandler.c smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c -smm-y += nb_util.c smm-y += gpio.c
CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index a079ec2..d92535a 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -24,9 +24,9 @@ #include <bootblock_common.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> +#include <amdblocks/biosram.h> #include <soc/pci_devs.h> #include <soc/cpu.h> -#include <soc/northbridge.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> #include <timestamp.h> diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index a0d7ce8..5694779 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -40,8 +40,6 @@ #define NB_IOAPIC_SCRATCH0 0x3e #define NB_IOAPIC_SCRATCH1 0x3f
-#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0 - /* D1F1 - HDA Configuration Registers */ #define HDA_DEV_CTRL_STATUS 0x60 #define HDA_NO_SNOOP_EN BIT(11) @@ -102,10 +100,6 @@ void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); -uint32_t nb_ioapic_read(unsigned int index); -void nb_ioapic_write(unsigned int index, uint32_t value); -void *get_ap_entry_ptr(void); -void set_ap_entry_ptr(void *entry); void set_warm_reset_flag(void); int is_warm_reset(void);
diff --git a/src/soc/amd/stoneyridge/nb_util.c b/src/soc/amd/stoneyridge/nb_util.c deleted file mode 100644 index d5de067..0000000 --- a/src/soc/amd/stoneyridge/nb_util.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Advanced Micro Devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/northbridge.h> -#include <soc/pci_devs.h> -#include <device/pci_ops.h> - -uint32_t nb_ioapic_read(unsigned int index) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA); -} - -void nb_ioapic_write(unsigned int index, uint32_t value) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value); -} - -void *get_ap_entry_ptr(void) -{ - return (void *)nb_ioapic_read(AP_SCRATCH_REG); -} - -void set_ap_entry_ptr(void *entry) -{ - nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry); -} diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 2228c1a..25eb4a1 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/biosram.h> #include <device/pci_ops.h> #include <arch/cpu.h> #include <arch/romstage.h>
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37416 )
Change subject: amdblocks/acpimmio: add common functions for AP entry ......................................................................
Patch Set 2: Code-Review+2
Don't know why build bot failed.. all looks good.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37416 )
Change subject: amdblocks/acpimmio: add common functions for AP entry ......................................................................
Patch Set 2:
Patch Set 2: Code-Review+2
Don't know why build bot failed.. all looks good.
rm: cannot remove '/cb-build/coreboot-gerrit.0/chromeos/INTEL_COMETLAKE_RVP': Directory not empty'´
Some race, a related commit changing the directory name is under review.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37416 )
Change subject: amdblocks/acpimmio: add common functions for AP entry ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37416 )
Change subject: amdblocks/acpimmio: add common functions for AP entry ......................................................................
Patch Set 3: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37416 )
Change subject: amdblocks/acpimmio: add common functions for AP entry ......................................................................
amdblocks/acpimmio: add common functions for AP entry
Move the stoneyridge implementation of get/set AP entry to the common block.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I9c73940ffe5f735dcd844911361355c384f617b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37416 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/common/block/acpimmio/biosram.c M src/soc/amd/common/block/include/amdblocks/biosram.h M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/include/soc/northbridge.h D src/soc/amd/stoneyridge/nb_util.c M src/soc/amd/stoneyridge/romstage.c 7 files changed, 18 insertions(+), 53 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Richard Spiegel: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/amd/common/block/acpimmio/biosram.c b/src/soc/amd/common/block/acpimmio/biosram.c index f0a1257..e33f02d 100644 --- a/src/soc/amd/common/block/acpimmio/biosram.c +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -15,6 +15,17 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/biosram.h>
+void *get_ap_entry_ptr(void) +{ + return (void *)biosram_read32(BIOSRAM_AP_ENTRY); +} + +void set_ap_entry_ptr(void *entry) +{ + biosram_write32(BIOSRAM_AP_ENTRY, (uintptr_t)entry); +} + + void backup_top_of_low_cacheable(uintptr_t ramtop) { biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index e2c1eb3..db28310 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -17,10 +17,15 @@ #include <stdint.h>
/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_AP_ENTRY 0xe8 /* 8 bytes */ #define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */
+/* Returns the bootblock C entry point for APs */ +void *get_ap_entry_ptr(void); +/* Used by BSP to store the bootblock entry point for APs */ +void set_ap_entry_ptr(void *entry); /* Saves the UMA size returned by AGESA */ void save_uma_size(uint32_t size); /* Saves the UMA base address returned by AGESA */ diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index d2d64c8..52c54d2 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -48,7 +48,6 @@ bootblock-y += reset.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c -bootblock-y += nb_util.c bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
romstage-y += BiosCallOuts.c @@ -65,7 +64,6 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c -romstage-y += nb_util.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
verstage-y += gpio.c @@ -75,12 +73,10 @@ verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c -verstage-y += nb_util.c
postcar-y += monotonic_timer.c postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c postcar-y += memmap.c -postcar-y += nb_util.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c
@@ -107,14 +103,12 @@ ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c -ramstage-y += nb_util.c
smm-y += monotonic_timer.c smm-y += smihandler.c smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c -smm-y += nb_util.c smm-y += gpio.c
CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index a079ec2..d92535a 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -24,9 +24,9 @@ #include <bootblock_common.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> +#include <amdblocks/biosram.h> #include <soc/pci_devs.h> #include <soc/cpu.h> -#include <soc/northbridge.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> #include <timestamp.h> diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index a0d7ce8..5694779 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -40,8 +40,6 @@ #define NB_IOAPIC_SCRATCH0 0x3e #define NB_IOAPIC_SCRATCH1 0x3f
-#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0 - /* D1F1 - HDA Configuration Registers */ #define HDA_DEV_CTRL_STATUS 0x60 #define HDA_NO_SNOOP_EN BIT(11) @@ -102,10 +100,6 @@ void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); -uint32_t nb_ioapic_read(unsigned int index); -void nb_ioapic_write(unsigned int index, uint32_t value); -void *get_ap_entry_ptr(void); -void set_ap_entry_ptr(void *entry); void set_warm_reset_flag(void); int is_warm_reset(void);
diff --git a/src/soc/amd/stoneyridge/nb_util.c b/src/soc/amd/stoneyridge/nb_util.c deleted file mode 100644 index d5de067..0000000 --- a/src/soc/amd/stoneyridge/nb_util.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Advanced Micro Devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/northbridge.h> -#include <soc/pci_devs.h> -#include <device/pci_ops.h> - -uint32_t nb_ioapic_read(unsigned int index) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA); -} - -void nb_ioapic_write(unsigned int index, uint32_t value) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value); -} - -void *get_ap_entry_ptr(void) -{ - return (void *)nb_ioapic_read(AP_SCRATCH_REG); -} - -void set_ap_entry_ptr(void *entry) -{ - nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry); -} diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 2228c1a..25eb4a1 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/biosram.h> #include <device/pci_ops.h> #include <arch/cpu.h> #include <arch/romstage.h>
-
Angel Pons (Code Review) -
Kyösti Mälkki (Code Review)
-
Michał Żygowski (Code Review)
-
Richard Spiegel (Code Review)