coreboot-gerrit November 2019

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Change in coreboot[master]: mb/google/kukui: Support panels using ANX7625
by Hung-Te Lin (Code Review) 14 Jan '20

14 Jan '20

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36767 ) Change subject: mb/google/kukui: Support panels using ANX7625 ...................................................................... mb/google/kukui: Support panels using ANX7625 For Kukui followers using ANX7625 eDP bridge to access panel. BUG=b:140132295 TEST=make # board = kukui Change-Id: I7dc9c68d076fd0ba4e963cde9414d25c17b332cb Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Makefile.inc A src/mainboard/google/kukui/panel_anx7625.c 3 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/36767/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index e6d604e..3b53478 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -42,6 +42,7 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER select DRIVER_PARADE_PS8640 if BOARD_GOOGLE_JACUZZI + select DRIVER_ANALOGIX_ANX7625 if BOARD_GOOGLE_JUNIPER || BOARD_GOOGLE_DAMU || BOARD_GOOGLE_KAPPA select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE config MAINBOARD_DIR diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 2e8a79a..7839422 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -30,4 +30,6 @@ ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c ramstage-$(CONFIG_DRIVER_PARADE_PS8640) += panel_ps8640.c +ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += panel_anx7625.c + ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c new file mode 100644 index 0000000..10cbf5c --- /dev/null +++ b/src/mainboard/google/kukui/panel_anx7625.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <drivers/analogix/anx7625/anx7625.h> +#include <edid.h> +#include <gpio.h> +#include <soc/i2c.h> +#include <string.h> + +#include "panel.h" + + +static void power_on_anx7625(void) +{ + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); + gpio_output(GPIO_PP1200_MIPIBRDG_EN, 1); //1.0 + gpio_output(GPIO_VDDIO_MIPIBRDG_EN, 1); //3.3 + gpio_output(GPIO_PP1800_LCM_EN, 1); //1.8 + mdelay(2); + gpio_output(GPIO_MIPIBRDG_PWRDN_L_1V8, 1); + mdelay(10); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 1); + gpio_output(GPIO_PP3300_LCM_EN, 1); +} + +static void dummy_power_on(void) +{ + /* The panel has been already powered on when getting panel information + * so we should do nothing here. + */ +} + +static struct panel_serializable_data anx7625_data = { + .orientation = LB_FB_ORIENTATION_NORMAL, + .init = { INIT_END_CMD }, +}; + +static struct panel_description anx7625_panel = { + .s = &anx7625_data, + .power_on = dummy_power_on, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + /* To read panel EDID, we have to first power on anx7625. */ + power_on_anx7625(); + + u8 i2c_bus = 4; + mtk_i2c_bus_init(i2c_bus); + + anx7625_init(i2c_bus); + struct edid *edid = &anx7625_data.edid; + if (anx7625_dp_get_edid(i2c_bus, edid)) { + printk(BIOS_ERR, "Can't get panel's edid\n"); + return NULL; + } + anx7625_dp_start(i2c_bus, edid); + return &anx7625_panel; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dc9c68d076fd0ba4e963cde9414d25c17b332cb Gerrit-Change-Number: 36767 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: vc/amd/agesa/f16kb: Fix out of bounds read
by Name of user not set (Code Review) 13 Jan '20

13 Jan '20

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36192 ) Change subject: vc/amd/agesa/f16kb: Fix out of bounds read ...................................................................... vc/amd/agesa/f16kb: Fix out of bounds read ByteLane is incorrectly used unitialized from prior for statement. Found nothing in following code that attempted to reference PassTestRxEnDly at that index, so appears safe to delete. Additionally, found nothing following with the OutOfRange[ByteLane]==TRUE condition that would expect 'PassTestRxEnDly[ByteLane] = RxOrig[ByteLane];'. Change-Id: Icd18a146aba6b6120d37518d8c40c7efbc05afa3 Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1241804 --- M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36192/1 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c index ce295ac..caf8f51 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c @@ -314,7 +314,6 @@ // IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t Setting PassTestRxEnDly\n"); IDS_HDT_CONSOLE (MEM_FLOW, "\t PassTestRxEnDly: "); - PassTestRxEnDly[ByteLane] = RxOrig[ByteLane]; for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { if (RxEnDlyTargetFound[ByteLane] == FALSE) { // Calculate "PassTestRxEnDly" from current "RxEnDly" -- To view, visit https://review.coreboot.org/c/coreboot/+/36192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd18a146aba6b6120d37518d8c40c7efbc05afa3 Gerrit-Change-Number: 36192 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: util/lint: Enforce SPDX licenses only in src/acpi directory
by Martin Roth (Code Review) 13 Jan '20

13 Jan '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36177 ) Change subject: util/lint: Enforce SPDX licenses only in src/acpi directory ...................................................................... util/lint: Enforce SPDX licenses only in src/acpi directory Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I9241f96eed652c8ca72d4f4a94f860a875e55680 --- M util/lint/lint-stable-000-license-headers 1 file changed, 5 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36177/1 diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers index 441e679..fcaf32c 100755 --- a/util/lint/lint-stable-000-license-headers +++ b/util/lint/lint-stable-000-license-headers @@ -1,22 +1,14 @@ #!/bin/sh +# SPDX-License-Identifier: GPL-2.0-only # This file is part of the coreboot project. # -# Copyright (C) 2016 Google Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# # DESCR: Check that files have license headers +# Directories requiring SPDX Identifiers only +util/lint/lint-000-license-headers "src/acpi" SPDX_ONLY + # Top level -util/lint/lint-000-license-headers "src/acpi src/arch src/commonlib src/console \ +util/lint/lint-000-license-headers "src/arch src/commonlib src/console \ src/cpu src/device src/ec src/mainboard src/northbridge src/soc \ src/southbridge src/superio" -- To view, visit https://review.coreboot.org/c/coreboot/+/36177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9241f96eed652c8ca72d4f4a94f860a875e55680 Gerrit-Change-Number: 36177 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mainboard/pcengines/apu2/mainboard.c: fill SMBIOS type 16 and 17
by Piotr Kleinschmidt (Code Review) 13 Jan '20

13 Jan '20

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35889 ) Change subject: mainboard/pcengines/apu2/mainboard.c: fill SMBIOS type 16 and 17 ...................................................................... mainboard/pcengines/apu2/mainboard.c: fill SMBIOS type 16 and 17 Change-Id: I24cd5abceabd11a079a8331e4b95cb69af8e94bf Signed-off-by: Piotr Kleinschmidt <piotr.kleins(a)gmail.com> --- M src/device/dram/Makefile.inc M src/lib/Makefile.inc M src/mainboard/pcengines/apu2/mainboard.c 3 files changed, 124 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/35889/1 diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index f397a53..d9df410 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1,2 @@ romstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c +ramstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c \ No newline at end of file diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e5678ff..dc09851 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -328,6 +328,7 @@ endif # CONFIG_RAMSTAGE_LIBHWBASE romstage-y += spd_bin.c +ramstage-y += spd_bin.c ifeq ($(CONFIG_GENERIC_SPD_BIN),y) LIB_SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 682120b..1d91a39 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -27,6 +27,9 @@ #include <superio/nuvoton/nct5104d/nct5104d.h> #include <smbios.h> #include <string.h> +#include <cbmem.h> +#include <spd_bin.h> +#include <cbfs.h> #include "gpio_ftns.h" #define SPD_SIZE 128 @@ -154,6 +157,81 @@ gpio->enabled = CONFIG(APU2_PINMUX_GPIO1); } +static void set_dimm_info(uint8_t *spd, struct dimm_info *dimm) +{ + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int ranks = spd_ranks[(spd[DDR3_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[DDR3_ORGANIZATION] & 7]; + int busw = spd_busw[spd[DDR3_BUS_DEV_WIDTH] & 7]; + + switch (spd[12]) { + case 0x0a: + dimm->ddr_frequency = 1600; + break; + case 0x0c: + dimm->ddr_frequency = 1333; + break; + default: + dimm->ddr_frequency = 0; + break; + } + + dimm->ddr_type = MEMORY_TYPE_DDR3; + + /* Parse the SPD data to determine the DIMM information */ + + dimm->dimm_size = capmb / 8 * busw / devw * ranks; /* MiB */ + dimm->mod_type = spd[3] & 0xf; + dimm->module_part_number[0] = '\0'; + dimm->mod_id = *(uint16_t *)&spd[117]; + + switch (busw) { + default: + case 8: + dimm->bus_width = MEMORY_BUS_WIDTH_8; + break; + case 16: + dimm->bus_width = MEMORY_BUS_WIDTH_16; + break; + case 32: + dimm->bus_width = MEMORY_BUS_WIDTH_32; + break; + case 64: + dimm->bus_width = MEMORY_BUS_WIDTH_64; + break; + } + + if(spd[3]==0x08){ + dimm->bus_width |= BIOS_MEMORY_ECC_SINGLE_BIT_CORRECTING; + } +} + +static void mainboard_get_dimm_info(u8 *spd_buffer) +{ + struct dimm_info *dimm; + struct memory_info *mem_info; + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (mem_info == NULL) + return; + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first channel memory */ + dimm = &mem_info->dimm[0]; + set_dimm_info(spd_buffer, dimm); + mem_info->dimm_cnt = 1; +} + /********************************************** * enable the dedicated function in mainboard. **********************************************/ @@ -164,6 +242,11 @@ config_gpio_mux(); + u8 spd_index = get_spd_offset(); + u8 spd_buffer[CONFIG_DIMM_SPD_SIZE]; + + read_ddr3_spd_from_cbfs(spd_buffer, spd_index); + // // Enable the RTC output // @@ -176,6 +259,8 @@ /* Initialize the PIRQ data structures for consumption */ pirq_setup(); + + mainboard_get_dimm_info(spd_buffer); } static void mainboard_final(void *chip_info) @@ -241,6 +326,43 @@ return sku; } +int fill_mainboard_smbios_type16(unsigned long *current, int *handle) +{ + u8 spd_index = get_spd_offset(); + u8 spd_buffer[CONFIG_DIMM_SPD_SIZE]; + + if (read_ddr3_spd_from_cbfs(spd_buffer, spd_index) < 0) + return 0; + + struct smbios_type16 *t = (struct smbios_type16 *)*current; + int len = sizeof(struct smbios_type16) - 2; + memset(t, 0, sizeof(struct smbios_type16)); + + t->handle = *handle; + t->length = len; + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->use = MEMORY_ARRAY_USE_SYSTEM; + t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; + t->maximum_capacity = 4 * 1024 * 1024; // 4GB (in kB) due to board design + t->extended_maximum_capacity = 0; + t->memory_error_information_handle = 0xFFFE; + t->number_of_memory_devices = 1; // only 1 device soldered down to 1 channel + + switch(spd_buffer[3]){ + case 0x08: + t->memory_error_correction = MEMORY_ARRAY_ECC_MULTI_BIT; + break; + case 0x03: + t->memory_error_correction = MEMORY_ARRAY_ECC_NONE; + break; + default: + t->memory_error_correction = MEMORY_ARRAY_ECC_UNKNOWN; + break; + } + len += smbios_string_table_len(t->eos); + return len; +} + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, .final = mainboard_final, -- To view, visit https://review.coreboot.org/c/coreboot/+/35889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24cd5abceabd11a079a8331e4b95cb69af8e94bf Gerrit-Change-Number: 35889 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: src/arch/x86/smbios.c: add SMBIOS type 16 structure
by Piotr Kleinschmidt (Code Review) 13 Jan '20

13 Jan '20

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35888 ) Change subject: src/arch/x86/smbios.c: add SMBIOS type 16 structure ...................................................................... src/arch/x86/smbios.c: add SMBIOS type 16 structure Change-Id: I590ebf89ecb3f97a9ce028ca34696e5809d66d49 Signed-off-by: Piotr Kleinschmidt <piotr.kleins(a)gmail.com> --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35888/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 4eb8726..4e8a794 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -527,6 +527,11 @@ return ""; } +int __weak fill_mainboard_smbios_type16(unsigned long *current, int *handle) +{ + return 0; +} + static int get_socket_type(void) { if (CONFIG(CPU_INTEL_SLOT_1)) @@ -938,6 +943,16 @@ return len; } +static int smbios_write_type16(unsigned long *current, int *handle) +{ + int len = fill_mainboard_smbios_type16(current, handle); + if(len){ + *current += len; + (*handle)++; + } + return len; +} + static int smbios_write_type17(unsigned long *current, int *handle) { int len = sizeof(struct smbios_type17); @@ -1176,6 +1191,8 @@ if (CONFIG(ELOG)) update_max(len, max_struct_size, elog_smbios_write_type15(&current,handle++)); + update_max(len, max_struct_size, smbios_write_type16(&current, + &handle)); update_max(len, max_struct_size, smbios_write_type17(&current, &handle)); update_max(len, max_struct_size, smbios_write_type32(&current, diff --git a/src/include/smbios.h b/src/include/smbios.h index 0bba0a7..e808177 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -52,6 +52,7 @@ const char *smbios_system_version(void); void smbios_system_set_uuid(u8 *uuid); const char *smbios_system_sku(void); +int fill_mainboard_smbios_type16(unsigned long *current, int *handle); const char *smbios_mainboard_manufacturer(void); const char *smbios_mainboard_product_name(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/35888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I590ebf89ecb3f97a9ce028ca34696e5809d66d49 Gerrit-Change-Number: 35888 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl
by Maulik V Vaghela (Code Review) 13 Jan '20

13 Jan '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37267 ) Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ...................................................................... soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl New Kconfig for Jasperlake soc was created and fsp_param for Jasperlake has differences compared to Tigerlake. Thus renaming fsp_params.c to fsp_params_tgl.c to point out correct file as per soc selected. Also, IFD tool now support jsl soc, so correct Kconfig to use correct IFD chipset based on Kconfig. Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc R src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/romstage/Makefile.inc R src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 5 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37267/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 01ce7d8..5c17b208 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -96,7 +96,8 @@ config IFD_CHIPSET string - default "tgl" + default "tgl" if SOC_INTEL_TIGERLAKE + default "jsl" if SOC_INTEL_JASPERLAKE config IED_REGION_SIZE hex diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index b402fa0..feb8d32 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y) +ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode @@ -33,7 +33,7 @@ ramstage-y += elog.c ramstage-y += espi.c ramstage-y += finalize.c -ramstage-y += fsp_params.c +ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += lockdown.c diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params_tgl.c similarity index 100% rename from src/soc/intel/tigerlake/fsp_params.c rename to src/soc/intel/tigerlake/fsp_params_tgl.c diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc index 8d151e3..4701f75 100644 --- a/src/soc/intel/tigerlake/romstage/Makefile.inc +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -13,7 +13,7 @@ # GNU General Public License for more details. # -romstage-y += fsp_params.c +romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += pch.c diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c similarity index 100% rename from src/soc/intel/tigerlake/romstage/fsp_params.c rename to src/soc/intel/tigerlake/romstage/fsp_params_tgl.c -- To view, visit https://review.coreboot.org/c/coreboot/+/37267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Gerrit-Change-Number: 37267 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

8 32

Change in coreboot[master]: drivers/aspeed/common: Add support for high resolution framebuffer
by Patrick Rudolph (Code Review) 11 Jan '20

11 Jan '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35726 ) Change subject: drivers/aspeed/common: Add support for high resolution framebuffer ...................................................................... drivers/aspeed/common: Add support for high resolution framebuffer Implement reading EDID over software I2C. Copy the linux kernel code and add a bunch of wrapper structs to make it compile. Convert the EDID to a drm_display_mode, which is understood by the driver. Tested on Supermicro X11SSH-TF using FullHD VGA monitor. Initializes the graphics in about 1 second, which is twice as fast as the VGA Option ROM. The framebuffer is advertised and woring in tianocore. Change-Id: I7803566b64158405efc04a39f80a0ec98b44e646 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/aspeed/ast2050/Kconfig M src/drivers/aspeed/ast2050/ast2050.c M src/drivers/aspeed/common/Kconfig M src/drivers/aspeed/common/Makefile.inc M src/drivers/aspeed/common/ast_drv.h A src/drivers/aspeed/common/ast_i2c.c A src/drivers/aspeed/common/ast_mode.c M src/drivers/aspeed/common/ast_tables.h 8 files changed, 1,159 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35726/1 diff --git a/src/drivers/aspeed/ast2050/Kconfig b/src/drivers/aspeed/ast2050/Kconfig index 337b181..7d2c728 100644 --- a/src/drivers/aspeed/ast2050/Kconfig +++ b/src/drivers/aspeed/ast2050/Kconfig @@ -1,5 +1,4 @@ config DRIVERS_ASPEED_AST2050 bool select DRIVERS_ASPEED_AST_COMMON - select HAVE_VGA_TEXT_FRAMEBUFFER select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 59659b8..01d58f9 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -34,6 +34,7 @@ pci_dev_set_resources(dev); } + static void aspeed_ast2050_init(struct device *dev) { struct drm_device drm_dev; @@ -50,13 +51,19 @@ outb(0xa6, 0x3d4); outb(0x2f, 0x3d5); outb(0xa7, 0x3d4); outb(0x3f, 0x3d5); - /* Initialize standard VGA text mode */ - vga_io_init(); - vga_textmode_init(); - printk(BIOS_INFO, "ASpeed VGA text mode initialized\n"); + if (CONFIG(VGA_TEXT_FRAMEBUFFER)) { + /* Initialize standard VGA text mode */ + vga_io_init(); - /* if we don't have console, at least print something... */ - vga_line_write(0, "ASpeed VGA text mode initialized"); + vga_textmode_init(); + printk(BIOS_INFO, "ASpeed VGA text mode initialized\n"); + + /* if we don't have console, at least print something... */ + vga_line_write(0, "ASpeed VGA text mode initialized"); + } else if (CONFIG(GENERIC_LINEAR_FRAMEBUFFER)) { + ast_driver_framebuffer_init(&drm_dev, 0); + printk(BIOS_INFO, "ASpeed high resolution framebuffer initialized\n"); + } } static struct device_operations aspeed_ast2050_ops = { diff --git a/src/drivers/aspeed/common/Kconfig b/src/drivers/aspeed/common/Kconfig index 653782f..c292bcf 100644 --- a/src/drivers/aspeed/common/Kconfig +++ b/src/drivers/aspeed/common/Kconfig @@ -1,3 +1,12 @@ config DRIVERS_ASPEED_AST_COMMON bool - select VGA + select HAVE_LINEAR_FRAMEBUFFER + select HAVE_VGA_TEXT_FRAMEBUFFER + select VGA if VGA_TEXT_FRAMEBUFFER + select SOFTWARE_I2C if GENERIC_LINEAR_FRAMEBUFFER + +config DRIVERS_ASPEED_I2C_BUS + int + depends on DRIVERS_ASPEED_AST_COMMON + depends on SOFTWARE_I2C + default 0 diff --git a/src/drivers/aspeed/common/Makefile.inc b/src/drivers/aspeed/common/Makefile.inc index 75f8b48..01e09a1 100644 --- a/src/drivers/aspeed/common/Makefile.inc +++ b/src/drivers/aspeed/common/Makefile.inc @@ -1 +1,4 @@ -ramstage-$(CONFIG_DRIVERS_ASPEED_AST_COMMON) += ast_dp501.c ast_main.c ast_post.c +ifeq ($(CONFIG_DRIVERS_ASPEED_AST_COMMON),y) +ramstage-y += ast_dp501.c ast_main.c ast_post.c +ramstage-$(CONFIG_GENERIC_LINEAR_FRAMEBUFFER) += ast_mode.c ast_i2c.c +endif diff --git a/src/drivers/aspeed/common/ast_drv.h b/src/drivers/aspeed/common/ast_drv.h index 53640f1..b46e98a 100644 --- a/src/drivers/aspeed/common/ast_drv.h +++ b/src/drivers/aspeed/common/ast_drv.h @@ -44,6 +44,7 @@ AST2150, AST2300, AST2400, + AST2500, AST1180, }; @@ -190,6 +191,8 @@ #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH*AST_MAX_HWC_HEIGHT*2) #define AST_HWC_SIGNATURE_SIZE 32 +#define EINVAL 22 /* Invalid argument */ + #define AST_DEFAULT_HWC_NUM 2 /* define for signature structure */ #define AST_HWC_SIGNATURE_CHECKSUM 0x00 @@ -200,6 +203,98 @@ #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 +/* ast_mode.c stuff */ +struct ast_vbios_stdtable { + u8 misc; + u8 seq[4]; + u8 crtc[25]; + u8 ar[20]; + u8 gr[9]; +}; + +struct ast_vbios_enhtable { + u32 ht; + u32 hde; + u32 hfp; + u32 hsync; + u32 vt; + u32 vde; + u32 vfp; + u32 vsync; + u32 dclk_index; + u32 flags; + u32 refresh_rate; + u32 refresh_rate_index; + u32 mode_id; +}; + +struct ast_vbios_dclk_info { + u8 param1; + u8 param2; + u8 param3; +}; + +struct ast_vbios_mode_info { + const struct ast_vbios_stdtable *std_table; + const struct ast_vbios_enhtable *enh_table; +}; + +#define DRM_MODE_FLAG_NVSYNC NVSync +#define DRM_MODE_FLAG_PVSYNC PVSync +#define DRM_MODE_FLAG_NHSYNC NHSync +#define DRM_MODE_FLAG_PHSYNC PHSync + +struct drm_display_mode { + /* Proposed mode values */ + u16 vrefresh; /* in Hz */ + u32 clock; + u16 hdisplay; + u16 vdisplay; + u32 flags; + + /* Actual mode we give to hw */ + u16 crtc_hdisplay; + u16 crtc_htotal; + u16 crtc_hblank_start; + u16 crtc_hblank_end; + u16 crtc_hsync_start; + u16 crtc_hsync_end; + u16 crtc_vtotal; + u16 crtc_vsync_start; + u16 crtc_vsync_end; + u16 crtc_vdisplay; + u16 crtc_vblank_start; + u16 crtc_vblank_end; +}; + +struct drm_format { + u32 cpp[1]; /* Colors per pixel */ +}; + +struct drm_framebuffer { + u32 pitches[1]; + struct drm_format *format; +}; + +struct drm_primary { + struct drm_framebuffer *fb; +}; + +struct drm_crtc { + struct drm_device *dev; + struct drm_primary *primary; + struct drm_display_mode mode; +}; + +struct drm_connector { + struct drm_device *dev; +}; + +enum drm_mode_status { + MODE_NOMODE, + MODE_OK +}; + #define AST_MM_ALIGN_SHIFT 4 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) @@ -220,4 +315,12 @@ bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); u8 ast_get_dp501_max_clk(struct drm_device *dev); void ast_init_3rdtx(struct drm_device *dev); + +/* ast mode */ +int ast_driver_framebuffer_init(struct drm_device *dev, int flags); + +/* ast i2c */ +void ast_software_i2c_init(unsigned bus); +int ast_software_i2c_read(unsigned bus, struct ast_private *ast_priv, uint8_t edid[256]); + #endif diff --git a/src/drivers/aspeed/common/ast_i2c.c b/src/drivers/aspeed/common/ast_i2c.c new file mode 100644 index 0000000..92cce3d --- /dev/null +++ b/src/drivers/aspeed/common/ast_i2c.c @@ -0,0 +1,137 @@ + +/* + * Copied from Linux drivers/gpu/drm/ast/ast_mode.c + * + * Copyright 2012 Red Hat Inc. + * Parts based on xf86-video-ast + * Copyright (c) 2005 ASPEED Technology Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: Dave Airlie <airlied(a)redhat.com> + * Authors: 9Elements Agency GmbH <patrick.rudolph(a)9elements.com> + */ +#include <delay.h> +#include <device/i2c_simple.h> + +#include "ast_drv.h" + +#if CONFIG_DRIVER_TPM_I2C_BUS == CONFIG_DRIVERS_ASPEED_I2C_BUS +#error Software I2C bus collision! +#endif + +#if CONFIG_EC_GOOGLE_CHROMEEC_I2C_BUS == CONFIG_DRIVERS_ASPEED_I2C_BUS +#error Software I2C bus collision! +#endif + +static struct ast_private *ast; + +static int get_clock(unsigned int bus) +{ + uint32_t val, val2, count, pass; + + count = 0; + pass = 0; + val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; + do { + val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; + if (val == val2) { + pass++; + } else { + pass = 0; + val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; + } + } while ((pass < 5) && (count++ < 0x10000)); + + return val & 1 ? 1 : 0; +} + +static int get_data(unsigned int bus) +{ + uint32_t val, val2, count, pass; + + count = 0; + pass = 0; + val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; + do { + val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; + if (val == val2) { + pass++; + } else { + pass = 0; + val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; + } + } while ((pass < 5) && (count++ < 0x10000)); + + return val & 1 ? 1 : 0; +} + +static void set_clock(unsigned int bus, int clock) +{ + int i; + u8 ujcrb7, jtemp; + + for (i = 0; i < 0x10000; i++) { + ujcrb7 = ((clock & 0x01) ? 0 : 1); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7); + jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); + if (ujcrb7 == jtemp) + break; + } +} + +static void set_data(unsigned int bus, int data) +{ + int i; + u8 ujcrb7, jtemp; + + for (i = 0; i < 0x10000; i++) { + ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7); + jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); + if (ujcrb7 == jtemp) + break; + } +} + +static struct software_i2c_ops ast_ops = { + .set_sda = set_data, + .set_scl = set_clock, + .get_sda = get_data, + .get_scl = get_clock, +}; + +void ast_software_i2c_init(unsigned bus) +{ + software_i2c[bus] = &ast_ops; + + i2c_recover_bus(bus); +} + +int ast_software_i2c_read(unsigned bus, struct ast_private *ast_priv, uint8_t edid[256]) +{ + ast = ast_priv; + + /* Need to reset internal EEPROM counter to 0 */ + return i2c_read_bytes(bus, 0x50, 0, edid, 256); +} diff --git a/src/drivers/aspeed/common/ast_mode.c b/src/drivers/aspeed/common/ast_mode.c new file mode 100644 index 0000000..b321f5d --- /dev/null +++ b/src/drivers/aspeed/common/ast_mode.c @@ -0,0 +1,777 @@ + +/* + * Copied from Linux drivers/gpu/drm/ast/ast_mode.c + * + * Copyright 2012 Red Hat Inc. + * Parts based on xf86-video-ast + * Copyright (c) 2005 ASPEED Technology Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: Dave Airlie <airlied(a)redhat.com> + * Authors: 9Elements Agency GmbH <patrick.rudolph(a)9elements.com> + */ +#include <edid.h> +#include <device/i2c_simple.h> + +#include "ast_drv.h" +#include "ast_tables.h" + + +static inline void ast_load_palette_index(struct ast_private *ast, + u8 index, u8 red, u8 green, + u8 blue) +{ + ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index); + ast_io_read8(ast, AST_IO_SEQ_PORT); + ast_io_write8(ast, AST_IO_DAC_DATA, red); + ast_io_read8(ast, AST_IO_SEQ_PORT); + ast_io_write8(ast, AST_IO_DAC_DATA, green); + ast_io_read8(ast, AST_IO_SEQ_PORT); + ast_io_write8(ast, AST_IO_DAC_DATA, blue); + ast_io_read8(ast, AST_IO_SEQ_PORT); +} + +static void ast_crtc_load_lut(struct drm_crtc *crtc) +{ + struct ast_private *ast = crtc->dev->dev_private; + /* FIXME: Gamma cor 2.6 ? */ + for (int i = 0; i < 256; i++) + ast_load_palette_index(ast, i, i, i, i); + +} + +static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = crtc->dev->dev_private; + const struct drm_framebuffer *fb = crtc->primary->fb; + u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate; + const struct ast_vbios_enhtable *best = NULL; + u32 hborder, vborder; + bool check_sync; + dev_err(crtc->dev->pdev, "fb->format->cpp[0] * 8 = %d\n", fb->format->cpp[0] * 8); + + switch (fb->format->cpp[0] * 8) { + case 8: + vbios_mode->std_table = &vbios_stdtable[VGAModeIndex]; + color_index = VGAModeIndex - 1; + break; + case 16: + vbios_mode->std_table = &vbios_stdtable[HiCModeIndex]; + color_index = HiCModeIndex; + break; + case 24: + case 32: + vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex]; + color_index = TrueCModeIndex; + break; + default: + return false; + } + dev_err(crtc->dev->pdev, "crtc->mode.crtc_hdisplay = %d\n", crtc->mode.crtc_hdisplay); + + switch (crtc->mode.crtc_hdisplay) { + case 640: + vbios_mode->enh_table = &res_640x480[refresh_rate_index]; + break; + case 800: + vbios_mode->enh_table = &res_800x600[refresh_rate_index]; + break; + case 1024: + vbios_mode->enh_table = &res_1024x768[refresh_rate_index]; + break; + case 1280: + if (crtc->mode.crtc_vdisplay == 800) + vbios_mode->enh_table = &res_1280x800[refresh_rate_index]; + else + vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; + break; + case 1360: + vbios_mode->enh_table = &res_1360x768[refresh_rate_index]; + break; + case 1440: + vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; + break; + case 1600: + if (crtc->mode.crtc_vdisplay == 900) + vbios_mode->enh_table = &res_1600x900[refresh_rate_index]; + else + vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; + break; + case 1680: + vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; + break; + case 1920: + if (crtc->mode.crtc_vdisplay == 1080) + vbios_mode->enh_table = &res_1920x1080[refresh_rate_index]; + else + vbios_mode->enh_table = &res_1920x1200[refresh_rate_index]; + break; + default: + return false; + } + + refresh_rate = mode->vrefresh; + check_sync = vbios_mode->enh_table->flags & WideScreenMode; + do { + const struct ast_vbios_enhtable *loop = vbios_mode->enh_table; + + while (loop->refresh_rate != 0xff) { + if ((check_sync) && + (((mode->flags & DRM_MODE_FLAG_NVSYNC) && + (loop->flags & PVSync)) || + ((mode->flags & DRM_MODE_FLAG_PVSYNC) && + (loop->flags & NVSync)) || + ((mode->flags & DRM_MODE_FLAG_NHSYNC) && + (loop->flags & PHSync)) || + ((mode->flags & DRM_MODE_FLAG_PHSYNC) && + (loop->flags & NHSync)))) { + loop++; + continue; + } + if (loop->refresh_rate <= refresh_rate + && (!best || loop->refresh_rate > best->refresh_rate)) + best = loop; + loop++; + } + if (best || !check_sync) + break; + check_sync = 0; + } while (1); + if (best) + vbios_mode->enh_table = best; + + hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0; + vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0; + + adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht; + adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder; + adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder; + adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder + + vbios_mode->enh_table->hfp; + adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder + + vbios_mode->enh_table->hfp + + vbios_mode->enh_table->hsync); + + adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt; + adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder; + adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder; + adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder + + vbios_mode->enh_table->vfp; + adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder + + vbios_mode->enh_table->vfp + + vbios_mode->enh_table->vsync); + + refresh_rate_index = vbios_mode->enh_table->refresh_rate_index; + mode_id = vbios_mode->enh_table->mode_id; + + if (ast->chip == AST1180) { + /* TODO 1180 */ + } else { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4)); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); + + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); + if (vbios_mode->enh_table->flags & NewModeInfo) { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, + fb->format->cpp[0] * 8); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); + + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); + } + } + + return true; +} + +static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = crtc->dev->dev_private; + const struct ast_vbios_stdtable *stdtable; + u32 i; + u8 jreg; + + /* Only 32 BPP support */ + stdtable = &vbios_stdtable[TrueCModeIndex]; + + jreg = stdtable->misc; + ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); + + /* Set SEQ */ + ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03); + for (i = 0; i < 4; i++) { + jreg = stdtable->seq[i]; + if (!i) + jreg |= 0x20; + ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg); + } + + /* Set CRTC */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); + for (i = 0; i < 25; i++) + ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); + + /* set AR */ + jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); + for (i = 0; i < 20; i++) { + jreg = stdtable->ar[i]; + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i); + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg); + } + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14); + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00); + + jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20); + + /* Set GR */ + for (i = 0; i < 9; i++) + ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); +} + +static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = crtc->dev->dev_private; + u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; + u16 temp, precache = 0; + + if ((ast->chip == AST2500) && + (vbios_mode->enh_table->flags & AST2500PreCatchCRT)) + precache = 40; + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); + + temp = (mode->crtc_htotal >> 3) - 5; + if (temp & 0x100) + jregAC |= 0x01; /* HT D[8] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); + + temp = (mode->crtc_hdisplay >> 3) - 1; + if (temp & 0x100) + jregAC |= 0x04; /* HDE D[8] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); + + temp = (mode->crtc_hblank_start >> 3) - 1; + if (temp & 0x100) + jregAC |= 0x10; /* HBS D[8] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); + + temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; + if (temp & 0x20) + jreg05 |= 0x80; /* HBE D[5] */ + if (temp & 0x40) + jregAD |= 0x01; /* HBE D[5] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); + + temp = ((mode->crtc_hsync_start-precache) >> 3) - 1; + if (temp & 0x100) + jregAC |= 0x40; /* HRS D[5] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); + + temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f; + if (temp & 0x20) + jregAD |= 0x04; /* HRE D[5] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); + + /* vert timings */ + temp = (mode->crtc_vtotal) - 2; + if (temp & 0x100) + jreg07 |= 0x01; + if (temp & 0x200) + jreg07 |= 0x20; + if (temp & 0x400) + jregAE |= 0x01; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); + + temp = (mode->crtc_vsync_start) - 1; + if (temp & 0x100) + jreg07 |= 0x04; + if (temp & 0x200) + jreg07 |= 0x80; + if (temp & 0x400) + jregAE |= 0x08; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); + + temp = (mode->crtc_vsync_end - 1) & 0x3f; + if (temp & 0x10) + jregAE |= 0x20; + if (temp & 0x20) + jregAE |= 0x40; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); + + temp = mode->crtc_vdisplay - 1; + if (temp & 0x100) + jreg07 |= 0x02; + if (temp & 0x200) + jreg07 |= 0x40; + if (temp & 0x400) + jregAE |= 0x02; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); + + temp = mode->crtc_vblank_start - 1; + if (temp & 0x100) + jreg07 |= 0x08; + if (temp & 0x200) + jreg09 |= 0x20; + if (temp & 0x400) + jregAE |= 0x04; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); + + temp = mode->crtc_vblank_end - 1; + if (temp & 0x100) + jregAE |= 0x10; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); + + if (precache) + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80); + else + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00); + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); +} + +static void ast_set_offset_reg(struct drm_crtc *crtc) +{ + struct ast_private *ast = crtc->dev->dev_private; + const struct drm_framebuffer *fb = crtc->primary->fb; + + u16 offset; + + offset = fb->pitches[0] >> 3; + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); +} + +static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = dev->dev_private; + const struct ast_vbios_dclk_info *clk_info; + + if (ast->chip == AST2500) + clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index]; + else + clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, + (clk_info->param3 & 0xc0) | + ((clk_info->param3 & 0x3) << 4)); +} + +static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = crtc->dev->dev_private; + u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; + + /* 32 BPP */ + jregA0 = 0x70; + jregA3 = 0x08; + jregA8 = 0x02; + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); + + /* Set Threshold */ + if (ast->chip == AST2300 || ast->chip == AST2400 || + ast->chip == AST2500) { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); + } else if (ast->chip == AST2100 || + ast->chip == AST1100 || + ast->chip == AST2200 || + ast->chip == AST2150) { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); + } else { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); + } +} + +static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = dev->dev_private; + u8 jreg; + + jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ); + jreg &= ~0xC0; + if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80; + if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40; + ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); +} + +static void ast_set_start_address_crt1(struct ast_private *ast, u32 offset) +{ + u32 addr; + + addr = offset >> 2; + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); +} + +static int ast_crtc_do_set_base(struct drm_crtc *crtc) +{ + struct ast_private *ast = crtc->dev->dev_private; + u64 gpu_addr; + + /* PCI BAR 0 */ + struct resource *res = find_resource(crtc->dev->pdev, 0x10); + if (!res) { + dev_err(dev->pdev, "BAR0 resource not found.\n"); + return -EIO; + } + + gpu_addr = (uintptr_t)res2mmio(res, 0, 0); + + ast_set_offset_reg(crtc); + ast_set_start_address_crt1(ast, (u32)gpu_addr); + + return 0; +} + +static int ast_crtc_mode_set(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct drm_device *dev = crtc->dev; + struct ast_private *ast = crtc->dev->dev_private; + struct ast_vbios_mode_info vbios_mode; + bool ret; + if (ast->chip == AST1180) { + dev_err(dev->pdev, "AST 1180 modesetting not supported\n"); + return -EINVAL; + } + + /* DPMS, set on */ + ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); + if (ast->tx_chip_type == AST_TX_DP501) + ast_set_dp501_video_output(crtc->dev, 1); + ast_crtc_load_lut(crtc); + + /* Get mode */ + ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode); + if (ret == false) { + dev_err(dev->pdev, "Failed to find compatible vbios mode\n"); + return -EINVAL; + } + ast_open_key(ast); + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); + + ast_set_std_reg(crtc, adjusted_mode, &vbios_mode); + ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode); + ast_set_offset_reg(crtc); + ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode); + ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode); + ast_set_sync_reg(dev, adjusted_mode, &vbios_mode); + + ast_crtc_do_set_base(crtc); + + /* Commit changes */ + + ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); + ast_crtc_load_lut(crtc); + + return 0; +} + +static int ast_get_modes(struct drm_connector *connector, struct edid *out) +{ + struct ast_private *ast = connector->dev->dev_private; + u8 edid[128]; + + bool flags = false; + if (ast->tx_chip_type == AST_TX_DP501) { + ast->dp501_maxclk = 0xff; + flags = ast_dp501_read_edid(connector->dev, (u8 *)edid); + if (flags) + ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev); + else + dev_err(dev->pdev, "I2C transmission error\n"); + } + + if (!flags) { + ast_software_i2c_read(CONFIG_DRIVERS_ASPEED_I2C_BUS, ast, edid); + } + if (decode_edid(edid, sizeof(edid), out) != EDID_CONFORMANT) { + dev_err(dev->pdev, "Failed to decode EDID\n"); + return -EIO; + } + + return 0; +} + +static enum drm_mode_status ast_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct ast_private *ast = connector->dev->dev_private; + int flags = MODE_NOMODE; + uint32_t jtemp; + + if (ast->support_wide_screen) { + if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050)) + return MODE_OK; + if ((mode->hdisplay == 1280) && (mode->vdisplay == 800)) + return MODE_OK; + if ((mode->hdisplay == 1440) && (mode->vdisplay == 900)) + return MODE_OK; + if ((mode->hdisplay == 1360) && (mode->vdisplay == 768)) + return MODE_OK; + if ((mode->hdisplay == 1600) && (mode->vdisplay == 900)) + return MODE_OK; + + if ((ast->chip == AST2100) || (ast->chip == AST2200) || + (ast->chip == AST2300) || (ast->chip == AST2400) || + (ast->chip == AST2500) || (ast->chip == AST1180)) { + if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080)) + return MODE_OK; + + if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) { + jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); + if (jtemp & 0x01) + return MODE_NOMODE; + else + return MODE_OK; + } + } + } + switch (mode->hdisplay) { + case 640: + if (mode->vdisplay == 480) flags = MODE_OK; + break; + case 800: + if (mode->vdisplay == 600) flags = MODE_OK; + break; + case 1024: + if (mode->vdisplay == 768) flags = MODE_OK; + break; + case 1280: + if (mode->vdisplay == 1024) flags = MODE_OK; + break; + case 1600: + if (mode->vdisplay == 1200) flags = MODE_OK; + break; + default: + return flags; + } + + return flags; +} + +static void ast_edid_to_drmmode(struct edid *edid, struct drm_display_mode *mode) +{ + memset(mode, 0, sizeof(*mode)); + + mode->hdisplay = edid->mode.ha; + mode->vdisplay = edid->mode.va; + mode->crtc_hdisplay = edid->mode.ha; + mode->crtc_vdisplay = edid->mode.va; + + mode->clock = edid->mode.pixel_clock; + mode->vrefresh = edid->mode.refresh; + + mode->crtc_hblank_start = edid->mode.ha + edid->mode.hso; + mode->crtc_hblank_end = edid->mode.ha + edid->mode.hso + edid->mode.hbl; + mode->crtc_hsync_start = edid->mode.ha + edid->mode.hso; + mode->crtc_hsync_end = edid->mode.ha + edid->mode.hso + edid->mode.hspw; + mode->crtc_htotal = MAX(mode->crtc_hblank_end, mode->crtc_hsync_end); + + mode->crtc_vblank_start = edid->mode.va + edid->mode.vso; + mode->crtc_vblank_end = edid->mode.va + edid->mode.vso + edid->mode.vbl; + mode->crtc_vsync_start = edid->mode.va + edid->mode.vso; + mode->crtc_vsync_end = edid->mode.va + edid->mode.vso + edid->mode.vspw; + mode->crtc_vtotal = MAX(mode->crtc_vblank_end, mode->crtc_vsync_end); + + mode->flags = 0; + if (edid->mode.phsync == '+') + mode->flags |= DRM_MODE_FLAG_PHSYNC; + else + mode->flags |= DRM_MODE_FLAG_NHSYNC; + + if (edid->mode.pvsync == '+') + mode->flags |= DRM_MODE_FLAG_PVSYNC; + else + mode->flags |= DRM_MODE_FLAG_NVSYNC; +} + +static int ast_select_mode(struct drm_connector *connector, + struct edid *edid, struct drm_display_mode *mode) +{ + bool widescreen; + int ret; + + ret = ast_get_modes(connector, edid); + if (ret) { + dev_err(dev->pdev, "Failed to get mode from EDID\n"); + return ret; + } + printk(BIOS_DEBUG, "Display has %dpx x %dpx\n", edid->mode.ha, edid->mode.va); + + widescreen = !!(((edid->mode.ha * 4) % (edid->mode.va * 3))); + + do { + /* Select a compatible smaller mode */ + if (edid->mode.ha > 1920 && widescreen) { + edid->mode.ha = 1920; + edid->mode.va = 1080; + } else if (edid->mode.ha >= 1920 && widescreen) { + edid->mode.ha = 1680; + edid->mode.va = 1050; + } else if (edid->mode.ha >= 1680 && widescreen) { + edid->mode.ha = 1600; + edid->mode.va = 900; + } else if (edid->mode.ha >= 1680 && !widescreen) { + edid->mode.ha = 1600; + edid->mode.va = 1200; + } else if (edid->mode.ha >= 1600 && widescreen) { + edid->mode.ha = 1440; + edid->mode.va = 900; + } else if (edid->mode.ha >= 1440 && widescreen) { + edid->mode.ha = 1360; + edid->mode.va = 768; + } else if (edid->mode.ha >= 1360 && widescreen) { + edid->mode.ha = 1280; + edid->mode.va = 800; + } else if (edid->mode.ha >= 1360 && !widescreen) { + edid->mode.ha = 1280; + edid->mode.va = 1024; + } else if (edid->mode.ha >= 1280) { + edid->mode.ha = 1024; + edid->mode.va = 768; + } else if (edid->mode.ha >= 1024) { + edid->mode.ha = 800; + edid->mode.va = 600; + } else if (edid->mode.ha >= 800) { + edid->mode.ha = 640; + edid->mode.va = 480; + } else { + dev_err(dev->pdev, "No compatible mode found.\n"); + + return -EIO; + } + + ast_edid_to_drmmode(edid, mode); + + } while (ast_mode_valid(connector, mode) != MODE_OK); + + /* Update EDID info */ + edid->x_resolution = edid->mode.ha; + edid->y_resolution = edid->mode.va; + edid->bytes_per_line = ALIGN_UP(edid->x_resolution * 4, 8); + + printk(BIOS_DEBUG, "Using framebuffer %dpx x %dpx pitch %d\n", + edid->x_resolution, edid->y_resolution, edid->bytes_per_line); + + return 0; +} + +static void ast_hide_cursor(struct drm_crtc *crtc) +{ + struct ast_private *ast = crtc->dev->dev_private; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00); +} + +int ast_driver_framebuffer_init(struct drm_device *dev, int flags) +{ + struct drm_display_mode adjusted_mode; + struct drm_crtc crtc; + struct drm_format format; + struct drm_primary primary; + struct drm_framebuffer fb; + struct drm_connector connector; + struct edid edid; + int ret; + + /* Init structs */ + connector.dev = dev; + + format.cpp[0] = 4; /* 32 BPP */ + fb.format = &format; + + primary.fb = &fb; + + crtc.dev = dev; + crtc.primary = &primary; + + /* Init I2C */ + ast_software_i2c_init(CONFIG_DRIVERS_ASPEED_I2C_BUS); + + /* Read EDID and find mode */ + ret = ast_select_mode(&connector, &edid, &crtc.mode); + if (ret) { + dev_err(dev->pdev, "Failed to select mode.\n"); + return ret; + } + + fb.pitches[0] = edid.bytes_per_line; + + memcpy(&adjusted_mode, &crtc.mode, sizeof(crtc.mode)); + + ret = ast_crtc_mode_set(&crtc, &crtc.mode, &adjusted_mode); + if (ret) { + dev_err(dev->pdev, "Failed to set mode.\n"); + return ret; + } + + ast_hide_cursor(&crtc); + + /* Advertise new mode */ + + /* PCI BAR 0 */ + struct resource *res = find_resource(dev->pdev, 0x10); + if (!res) { + dev_err(dev->pdev, "BAR0 resource not found.\n"); + return -EIO; + } + uintptr_t gpu_addr = (uintptr_t)res2mmio(res, 0, 0); + + edid.framebuffer_bits_per_pixel = 32; /* 32 BPP */ + set_vbe_mode_info_valid(&edid, gpu_addr); + + /* Clear display */ + memset((void *)gpu_addr, 0, edid.bytes_per_line * edid.y_resolution); + + return 0; +} diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index 6c20f36..aa54fcf 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -47,6 +47,7 @@ #define SyncPN (PVSync | NHSync) #define SyncNP (NVSync | PHSync) #define SyncNN (NVSync | NHSync) +#define AST2500PreCatchCRT 0x00004000 /* DCLK Index */ #define VCLK25_175 0x00 @@ -108,80 +109,110 @@ {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */ }; +static const struct ast_vbios_dclk_info dclk_table_ast2500[] = { + {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ + {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ + {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ + {0x76, 0x63, 0x01}, /* 03: VCLK36 */ + {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ + {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ + {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ + {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ + {0x80, 0x64, 0x00}, /* 08: VCLK65 */ + {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ + {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ + {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ + {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ + {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ + {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ + {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ + {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ + {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ + {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ + {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ + {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ + {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ + {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ + {0x58, 0x01, 0x42}, /* 17: VCLK119 */ + {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ + {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ + {0x44, 0x20, 0x43}, /* 1A: VCLK118_25 */ +}; + static struct ast_vbios_stdtable vbios_stdtable[] = { /* MD_2_3_400 */ { 0x67, - {0x00,0x03,0x00,0x02}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f, - 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00, - 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3, - 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x0c,0x00,0x0f,0x08}, - {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00, - 0xff} + {0x00, 0x03, 0x00, 0x02}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff}, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x0c, 0x00, 0x0f, 0x08}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, + 0xff} }, /* Mode12/ExtEGATable */ { 0xe3, - {0x01,0x0f,0x00,0x06}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3, - 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x01,0x00,0x0f,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, - 0xff} + {0x01, 0x0f, 0x00, 0x06}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xe9, 0x8b, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3, + 0xff}, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x01, 0x00, 0x0f, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, + 0xff} }, /* ExtVGATable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, - 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f, - 0xff} + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, + 0xff}, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, + 0xff} }, /* ExtHiCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, - 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, - 0xff} + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, + 0xff}, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, + 0xff} }, /* ExtTrueCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, }; -static struct ast_vbios_enhtable res_640x480[] = { +static const struct ast_vbios_enhtable res_640x480[] = { { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175, /* 60Hz */ (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E }, { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ @@ -194,7 +225,7 @@ (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, }; -static struct ast_vbios_enhtable res_800x600[] = { +static const struct ast_vbios_enhtable res_800x600[] = { {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */ (SyncPP | Charx8Dot), 56, 1, 0x30 }, {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60Hz */ @@ -210,7 +241,7 @@ }; -static struct ast_vbios_enhtable res_1024x768[] = { +static const struct ast_vbios_enhtable res_1024x768[] = { {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */ (SyncNN | Charx8Dot), 60, 1, 0x31 }, {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75, /* 70Hz */ @@ -223,7 +254,7 @@ (SyncPP | Charx8Dot), 0xFF, 4, 0x31 }, }; -static struct ast_vbios_enhtable res_1280x1024[] = { +static const struct ast_vbios_enhtable res_1280x1024[] = { {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108, /* 60Hz */ (SyncPP | Charx8Dot), 60, 1, 0x32 }, {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135, /* 75Hz */ @@ -234,7 +265,7 @@ (SyncPP | Charx8Dot), 0xFF, 3, 0x32 }, }; -static struct ast_vbios_enhtable res_1600x1200[] = { +static const struct ast_vbios_enhtable res_1600x1200[] = { {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* 60Hz */ (SyncPP | Charx8Dot), 60, 1, 0x33 }, {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* end */ @@ -242,34 +273,39 @@ }; /* 16:9 */ -static struct ast_vbios_enhtable res_1360x768[] = { - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ +static const struct ast_vbios_enhtable res_1360x768[] = { + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 }, - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */ - (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 }, + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* end */ + (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 0xFF, 1, 0x39 }, }; -static struct ast_vbios_enhtable res_1600x900[] = { - {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ +static const struct ast_vbios_enhtable res_1600x900[] = { + {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x3A }, + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A }, }; -static struct ast_vbios_enhtable res_1920x1080[] = { +static const struct ast_vbios_enhtable res_1920x1080[] = { {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x38 }, {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x38 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 0xFF, 1, 0x38 }, }; /* 16:10 */ -static struct ast_vbios_enhtable res_1280x800[] = { +static const struct ast_vbios_enhtable res_1280x800[] = { {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x35 }, {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 }, {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ @@ -277,29 +313,32 @@ }; -static struct ast_vbios_enhtable res_1440x900[] = { +static const struct ast_vbios_enhtable res_1440x900[] = { {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x36 }, {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 }, {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 }, }; -static struct ast_vbios_enhtable res_1680x1050[] = { +static const struct ast_vbios_enhtable res_1680x1050[] = { {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x37 }, {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 }, {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 }, }; -static struct ast_vbios_enhtable res_1920x1200[] = { +static const struct ast_vbios_enhtable res_1920x1200[] = { {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB*/ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 }, - {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x34 }, + {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB */ + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 0xFF, 1, 0x34 }, }; - #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7803566b64158405efc04a39f80a0ec98b44e646 Gerrit-Change-Number: 35726 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

9 42

Change in coreboot[master]: mb/lenovo/t431s/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 10 Jan '20

10 Jan '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37301 ) Change subject: mb/lenovo/t431s/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/t431s/devicetree: Use subsystemid inheritance Change-Id: I247129317799d342b28f2c0ed68949ecbe7d9c75 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb 1 file changed, 6 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37301/1 diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index e69f727..1a4b67a 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -13,47 +13,26 @@ register "gpu_cpu_backlight" = "0x03d2" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x2208 - end # host bridge + subsystemid 0x17aa 0x2208 inherit + device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x2208 - end # Integrated Graphics Controller + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) & 4 (dock) register "sata_port_map" = "0x13" # T431s has no Express Card slot. register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - device pci 14.0 on - subsystemid 0x17aa 0x2208 - end # USB 3.0 Controller - device pci 1a.0 on - subsystemid 0x17aa 0x2208 - end # USB Enhanced Host Controller #2 - device pci 1b.0 on - subsystemid 0x17aa 0x2208 - end # High Definition Audio Controller + device pci 1c.0 on # PCIe Port #1 - subsystemid 0x17aa 0x2208 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" register "sdwppol" = "0" - device pci 00.0 on # Ricoh SD card reader - subsystemid 0x17aa 0x2208 - end + device pci 00.0 on end # Ricoh SD card reader end end - device pci 1c.1 on - subsystemid 0x17aa 0x2208 - end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.2 off end # PCIe Port #3 - device pci 1d.0 on - subsystemid 0x17aa 0x2208 - end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge device pci 1f.0 on - subsystemid 0x17aa 0x2208 chip ec/lenovo/h8 register "config0" = "0xa6" register "config1" = "0x09" @@ -63,12 +42,6 @@ register "has_bdc_detection" = "0" end end # LPC Controller - device pci 1f.2 on - subsystemid 0x17aa 0x2208 - end # 6 port SATA AHCI Controller - device pci 1f.3 on - subsystemid 0x17aa 0x2208 - end # SMBus Controller device pci 1f.6 off end # Thermal end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I247129317799d342b28f2c0ed68949ecbe7d9c75 Gerrit-Change-Number: 37301 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: vc/amd/agesa: Remove unused assignments
by Name of user not set (Code Review) 10 Jan '20

10 Jan '20

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36257 ) Change subject: vc/amd/agesa: Remove unused assignments ...................................................................... vc/amd/agesa: Remove unused assignments 'Status' is assigned a value three times before it is checked. Remove the first two assignments. Change-Id: Id7136d62b4dbd6dce877983467960373b3a7ac22 Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1241809 --- M src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c 4 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/36257/1 diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index fd7ab4e..d74949b 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -472,13 +472,11 @@ if (ExtDisplayDeviceInfo == NULL) { //Run out of supported display device types AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) { AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index 70aa595..440c5ff 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -474,13 +474,11 @@ if (ExtDisplayDeviceInfo == NULL) { //Run out of supported display device types AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) { AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index f3af5e9..2d42063 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -488,13 +488,11 @@ if (ExtDisplayDeviceInfo == NULL) { //Run out of supported display device types AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) { AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index c9c9166..2350122 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -488,13 +488,11 @@ if (ExtDisplayDeviceInfo == NULL) { //Run out of supported display device types AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) { AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7136d62b4dbd6dce877983467960373b3a7ac22 Gerrit-Change-Number: 36257 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/x1/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 10 Jan '20

10 Jan '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37384 ) Change subject: mb/lenovo/x1/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/x1/devicetree: Use subsystemid inheritance Change-Id: I0081b5f219447b110dddfa82cbae51d9ca282f5b Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x220/variants/x1/overridetree.cb 1 file changed, 2 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/37384/1 diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb index 54f6485..cd2cd63 100644 --- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb @@ -13,12 +13,7 @@ register "gpu_pch_backlight" = "0x13121312" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21e8 - end # host bridge - device pci 02.0 on - subsystemid 0x17aa 0x21e8 - end # vga controller + subsystemid 0x17aa 0x21e8 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # Enable SATA ports 0 (HDD bay) & 2 (msata) & 3 (esatap) @@ -26,37 +21,11 @@ # X1 does not have ExpressCard slot register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - device pci 1a.0 on - subsystemid 0x17aa 0x21e8 - end # USB2 EHCI #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21e8 - end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21e8 - end # PCIe Port #2 (wlan) device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on - subsystemid 0x17aa 0x21e8 - chip drivers/ricoh/rce822 # Ricoh cardreader - device pci 00.0 on - subsystemid 0x17aa 0x21e8 - end - end - end # PCIe Port #5 (SD) - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on - subsystemid 0x17aa 0x21e8 - end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21e8 - end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge + device pci 1c.6 on end # PCIe Port #7 device pci 1f.0 on #LPC bridge - subsystemid 0x17aa 0x21e8 chip ec/lenovo/h8 register "config2" = "0xe0" register "config3" = "0xc0" @@ -66,20 +35,8 @@ register "event5_enable" = "0x3c" register "evente_enable" = "0x3d" - - # BDC detection is broken on this board: - register "has_bdc_detection" = "0" end end # LPC bridge - device pci 1f.2 on - subsystemid 0x17aa 0x21e8 - end # SATA Controller 1 - device pci 1f.3 on - subsystemid 0x17aa 0x21e8 - end # SMBus - device pci 1f.6 on - subsystemid 0x17aa 0x21e8 - end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0081b5f219447b110dddfa82cbae51d9ca282f5b Gerrit-Change-Number: 37384 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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