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Change in coreboot[master]: Documentation: xx30 ThinkPads internal flashing
by Evgeny Zinoviev (Code Review) 05 Feb '20

05 Feb '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36666 ) Change subject: Documentation: xx30 ThinkPads internal flashing ...................................................................... Documentation: xx30 ThinkPads internal flashing Add detailed instructions on how to unlock protected SPI ranges and flash coreboot internally on Lenovo ThinkPad Ivy Bridge series by exploiting stock BIOS security issues. Change-Id: I8d8551910c31fd2e6ff728e17dafaea45970166b Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/ivb_bios_flashing1.jpg A Documentation/mainboard/lenovo/ivb_bios_flashing2.jpg A Documentation/mainboard/lenovo/ivb_bios_legacy_only.jpg A Documentation/mainboard/lenovo/ivb_bios_uefi_only.jpg A Documentation/mainboard/lenovo/ivb_internal_flashing.md 6 files changed, 318 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/36666/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 8e88443..0e71add 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -90,6 +90,7 @@ - [W530](lenovo/w530.md) - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) - [T431s](lenovo/t431s.md) +- [Internal flashing](lenovo/ivb_internal_flashing.md) ### Haswell series diff --git a/Documentation/mainboard/lenovo/ivb_bios_flashing1.jpg b/Documentation/mainboard/lenovo/ivb_bios_flashing1.jpg new file mode 100644 index 0000000..10a27b0 --- /dev/null +++ b/Documentation/mainboard/lenovo/ivb_bios_flashing1.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/ivb_bios_flashing2.jpg b/Documentation/mainboard/lenovo/ivb_bios_flashing2.jpg new file mode 100644 index 0000000..4be1101 --- /dev/null +++ b/Documentation/mainboard/lenovo/ivb_bios_flashing2.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/ivb_bios_legacy_only.jpg b/Documentation/mainboard/lenovo/ivb_bios_legacy_only.jpg new file mode 100644 index 0000000..aef9c7b --- /dev/null +++ b/Documentation/mainboard/lenovo/ivb_bios_legacy_only.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/ivb_bios_uefi_only.jpg b/Documentation/mainboard/lenovo/ivb_bios_uefi_only.jpg new file mode 100644 index 0000000..7def81e --- /dev/null +++ b/Documentation/mainboard/lenovo/ivb_bios_uefi_only.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/ivb_internal_flashing.md b/Documentation/mainboard/lenovo/ivb_internal_flashing.md new file mode 100644 index 0000000..b9a023e --- /dev/null +++ b/Documentation/mainboard/lenovo/ivb_internal_flashing.md @@ -0,0 +1,317 @@ +# Ivy Bridge Lenovo ThinkPad Internal Flashing + +## Introduction + +Old versions of stock BIOS for these models have several security issues. In order to flash coreboot internally, two of them are of interest. + +**First** is the fact the SMM_BWP and BLE are not enabled in BIOS versions released before 2014. We have tested many versions on T430 and X230 and found out that SMM_BWP=1 only since the update, the changelog of which contains following line: + +> (New) Improved the UEFI BIOS security feature. + +**Second** is [S3 Boot Script vulnerability](https://support.lenovo.com/eg/ru/product_security/s3_boot_pr…, that was discovered and fixed later. + +## Requirements + +- USB drive (in case you need to downgrade BIOS) +- Linux install that (can be) loaded in UEFI mode +- [CHIPSEC](https://github.com/chipsec/chipsec) + +## BIOS versions + +Below is a table of BIOS versions that are vulnerable enough for our goals, per model. The version number means that you need to downgrade to that or earlier version. + +```eval_rst ++------------+--------------+ +| Model | BIOS version | ++============+==============+ +| X230 | 2.60 | ++------------+--------------+ +| T430 | 2.64 | ++------------+--------------+ +| T430s | 2.59 | ++------------+--------------+ +| T530 | 2.60 | ++------------+--------------+ +| W530 | 2.58 | ++------------+--------------+ +``` + +If your BIOS version is equal or lower, skip to the **[Examining protections](#examining-protections-theory)** section. If not, go through the downgrade process, described next. + +## Downgrading BIOS + +Go to the Lenovo web site and download BIOS Update Bootable CD for your machine of needed version (see above). + +Lenovo states that BIOS has "security rollback prevention", meaning once you update it to some version X, you will not be able to downgrade it to pre-X version. That's not true. It seems that this is completely client-side restriction in flashing utilities (both Windows utility and Bootable CD). You just need to call `winflash.exe` or `dosflash.exe` directly. Therefore you need to modify the bootable CD image you just downloaded. + +Extract an El Torito image: +``` +geteltorito -o ./bios.img g1uj41us.iso +``` +Mount the partition in that image: +``` +sudo mount -t vfat ./bios.img /mnt -o loop,offset=16384 +``` +List files, find the `AUTOEXEC.BAT` file and the `FLASH` directory: +``` +ls /mnt +ls /mnt/FLASH +``` + +Inside the `FLASH` directory, there should be a directory called `G1ET93WW` or similar (exact name depends on your ThinkPad model and BIOS version). See what's inside: +``` +ls /mnt/FLASH/G1ET93WW +``` +There must be a file with `.FL1` extension called `$01D2000.FL1` or something similar. + +Now open the `AUTOEXEC.BAT` file: +``` +sudo vim /mnt/AUTOEXEC.BAT +``` +You will see a list of commands: +``` +@ECHO OFF +PROMPT $p$g +cd c:\flash +command.com +``` +Replace the last line (`command.com`) with this (change path to the `.FL1` file according to yours): +``` +dosflash.exe /sd /file G1ET93WW\$01D2000.FL1 +``` + +Save the file, then unmount the partition: +``` +sudo unmount /mnt +``` + +Write this image to a USB drive (replace `/dev/sdX` with your USB drive device name): +``` +sudo dd if=./bios.img of=/dev/sdX bs=1M +``` + +Now reboot and press F1 to enter BIOS settings. Open the **Startup** tab and set the startup mode to **Legacy** (or **Both**/**Legacy First**): + +![](ivb_bios_legacy_only.jpg) + +Press F10 to save changes and reboot. + +Now, before you process, make sure that AC adapter is connected! If your battery will die during the process, you'll likely need external programmer to recover. + +Boot from the USB drive (press F12 to select boot device), and BIOS flashing process should begin: + +![](ivb_bios_flashing1.jpg) + +![](ivb_bios_flashing2.jpg) + +It may reboot a couple of times in the process. Do not interrupt it. + +When it's completed, go back to the BIOS settings and set startup mode to **UEFI** (or **Both**/**UEFI First**). This is required for vulnerability exploitation. + +![](ivb_bios_uefi_only.jpg) + +Then boot to your system and make sure that `/sys/firmware/efi` or `/sys/firmware/efivars` exist. + +## Examining protections (theory) + +There are two main ways that Intel platform provides to protect BIOS chip: +- **BIOS_CNTL** register of LPC Interface Bridge Registers (accessible via PCI configuration space, offset 0xDC). It has: + * **SMM_BWP** (*SMM BIOS Write Protect*) bit. If set to 1, the BIOS is writable only in SMM. Once set to 1, cannot be changed anymore. + * **BLE** (*BIOS Lock Enable*) bit. If set to 1, setting BIOSWE to 1 will raise SMI. Once set to 1, cannot be changed anymore. + * **BIOSWE** (*BIOS Write Enable*) bit. Controls whether BIOS is writable. This bit is always R/W. +- SPI Protected Range Registers (**PR0**-**PR4**) of SPI Configuration Registers (SPIBAR+0x74 - SPIBAR+0x84). Each register has bits that define protected range, plus WP bit, that defines whether write protection is enabled. + + There's also **FLOCKDN** bit of HSFS register (SPIBAR+0x04) of SPI Configuration Registers. When set to 1, PR0-PR4 registers cannot be written. Once set to 1, cannot be changed anymore. + +To be able to flash, we need SMM_BWP=0, BIOSWE=1, BLE=0, FLOCKDN=0 or SPI protected ranges (PRx) to have a WP bit set to 0. + +Let's see what we have. Examine HSFS register: +``` +sudo chipsec_main -m chipsec.modules.common.spi_lock +``` +You should see that FLOCKDN=1: +``` +[x][ ======================================================================= +[x][ Module: SPI Flash Controller Configuration Locks +[x][ ======================================================================= +[*] HSFS = 0xE009 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4) + [00] FDONE = 1 << Flash Cycle Done + [01] FCERR = 0 << Flash Cycle Error + [02] AEL = 0 << Access Error Log + [03] BERASE = 1 << Block/Sector Erase Size + [05] SCIP = 0 << SPI cycle in progress + [13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status + [14] FDV = 1 << Flash Descriptor Valid + [15] FLOCKDN = 1 << Flash Configuration Lock-Down +``` + +Then check BIOS_CNTL and PR0-PR4: +``` +sudo chipsec_main -m common.bios_wp +``` +Good news: on old BIOS versions, SMM_BWP=0 and BLE=0. + +Bad news: there are 4 write protected SPI ranges: + +``` +[x][ ======================================================================= +[x][ Module: BIOS Region Write Protection +[x][ ======================================================================= +[*] BC = 0x 8 << BIOS Control (b:d.f 00:31.0 + 0xDC) + [00] BIOSWE = 0 << BIOS Write Enable + [01] BLE = 0 << BIOS Lock Enable + [02] SRC = 2 << SPI Read Configuration + [04] TSS = 0 << Top Swap Status + [05] SMM_BWP = 0 << SMM BIOS Write Protection +[-] BIOS region write protection is disabled! + +[*] BIOS Region: Base = 0x00500000, Limit = 0x00BFFFFF +SPI Protected Ranges +------------------------------------------------------------ +PRx (offset) | Value | Base | Limit | WP? | RP? +------------------------------------------------------------ +PR0 (74) | 00000000 | 00000000 | 00000000 | 0 | 0 +PR1 (78) | 8BFF0B40 | 00B40000 | 00BFFFFF | 1 | 0 +PR2 (7C) | 8B100B10 | 00B10000 | 00B10FFF | 1 | 0 +PR3 (80) | 8ADE0AD0 | 00AD0000 | 00ADEFFF | 1 | 0 +PR4 (84) | 8AAF0800 | 00800000 | 00AAFFFF | 1 | 0 +``` + +Other way to examine SPI configuration registers is to just dump SPIBAR: +``` +sudo chipsec_util mmio dump SPIBAR +``` +You will see SPIBAR address (0xFED1F800) and registers (for example, 00000004 is HSFS): +``` +[mmio] MMIO register range [0x00000000FED1F800:0x00000000FED1F800+00000200]: ++00000000: 0BFF0500 ++00000004: 0004E009 +... +``` +As you can see, the only thing we need is to unset WP bit on PR0-PR4. But that cannot be done once FLOCKDN is set to 1. + +Now the fun part! + +FLOCKDN may only be cleared by a hardware reset, which includes S3 state. On S3 resume boot path, the chipset configuration has to be restored and it's done by executing so-called S3 Boot Scripts. You can dump these scripts by executing: +``` +sudo chipsec_util uefi s3bootscript +``` +There are many entries. Along them, you can find instructions to write to HSFS (remember, we know that SPIBAR is 0xFED1F800): +``` +Entry at offset 0x2B8F (len = 0x17, header len = 0x0): +Data: +02 00 17 02 00 00 00 01 00 00 00 04 f8 d1 fe 00 | +00 00 00 09 e0 04 00 | +Decoded: + Opcode : S3_BOOTSCRIPT_MEM_WRITE (0x0002) + Width : 0x02 (4 bytes) + Address: 0xFED1F804 + Count : 0x1 + Values : 0x0004E009 +``` +These scripts are stored in memory. The vulnerability is that we can overwrite this memory, change these instructions and they will be executed on S3 resume. Once we patch that instruction to not set FLOCKDN bit, we will be able to write to PR0-PR4 registers. + +## Creating a backup + +Before you proceed, please create a backup of the `bios` region. Then, in case something goes wrong, you'll be able to flash it back externally. + +The `me` region is locked, so an attempt to create a full dump will fail. But you can back up the `bios`: +``` +sudo flashrom -p internal -r bios_backup.rom --ifd -i bios +``` + +If you will even need to flash it back, use `--ifd -i bios` as well: +``` +sudo flashrom -p <YOUR_PROGRAMMER> -w bios_backup.rom --ifd -i bios +``` +**Caution:** if you will omit `--ifd -i bios` for flashing, you will brick your machine, because your backup has `FF`s in place of `fd` and `me` regions. Flash only `bios` region! + +## Removing protections (practice) + +The original boot script writes 0xE009 to HSFS. FLOCKDN is 15th bit, so let's write 0x6009 instead: +``` +sudo chipsec_main -m tools.uefi.s3script_modify -a replace_op,mmio_wr,0xFED1F804,0x6009,0x2 +``` +You will get a lot of output and in the end you should see something like this: +``` +[*] Modifying S3 boot script entry at address 0x00000000DAF49B8F.. +[mem] 0x00000000DAF49B8F +[*] Original entry: + 2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 | + 0 0 0 9 e0 4 0 | +[mem] buffer len = 0x17 to PA = 0x00000000DAF49B8F + 2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 | + 0 0 0 9 60 0 0 | ` +[mem] 0x00000000DAF49B8F +[*] Modified entry: + 2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 | + 0 0 0 9 60 0 0 | ` +[*] After sleep/resume, check the value of register 0xFED1F804 is 0x6009 +[+] PASSED: The script has been modified. Go to sleep.. +``` +Now go to S3, then resume and check FLOCKDN. It should be 0: +``` +sudo chipsec_main -m chipsec.modules.common.spi_lock +``` +``` +... +[x][ ======================================================================= +[x][ Module: SPI Flash Controller Configuration Locks +[x][ ======================================================================= +[*] HSFS = 0x6008 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4) + [00] FDONE = 0 << Flash Cycle Done + [01] FCERR = 0 << Flash Cycle Error + [02] AEL = 0 << Access Error Log + [03] BERASE = 1 << Block/Sector Erase Size + [05] SCIP = 0 << SPI cycle in progress + [13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status + [14] FDV = 1 << Flash Descriptor Valid + [15] FLOCKDN = 0 << Flash Configuration Lock-Down +[-] SPI Flash Controller configuration is not locked +[-] FAILED: SPI Flash Controller not locked correctly. +... +``` +Set BIOSWE: +``` +sudo setpci -s 00:1f.0 dc.b=09 +``` +Remove WP from protected ranges: +``` +sudo chipsec_util mmio write SPIBAR 0x74 0x4 0xAAF0800 +sudo chipsec_util mmio write SPIBAR 0x78 0x4 0xADE0AD0 +sudo chipsec_util mmio write SPIBAR 0x7C 0x4 0xB100B10 +sudo chipsec_util mmio write SPIBAR 0x80 0x4 0xBFF0B40 +``` +Verify that it worked: +``` +sudo chipsec_main -m common.bios_wp +``` +``` +[x][ ======================================================================= +[x][ Module: BIOS Region Write Protection +[x][ ======================================================================= +[*] BC = 0x 9 << BIOS Control (b:d.f 00:31.0 + 0xDC) + [00] BIOSWE = 1 << BIOS Write Enable + [01] BLE = 0 << BIOS Lock Enable + [02] SRC = 2 << SPI Read Configuration + [04] TSS = 0 << Top Swap Status + [05] SMM_BWP = 0 << SMM BIOS Write Protection +[-] BIOS region write protection is disabled! + +[*] BIOS Region: Base = 0x00500000, Limit = 0x00BFFFFF +SPI Protected Ranges +------------------------------------------------------------ +PRx (offset) | Value | Base | Limit | WP? | RP? +------------------------------------------------------------ +PR0 (74) | 0AAF0800 | 00800000 | 00AAF000 | 0 | 0 +PR1 (78) | 0ADE0AD0 | 00AD0000 | 00ADE000 | 0 | 0 +PR2 (7C) | 0B100B10 | 00B10000 | 00B10000 | 0 | 0 +PR3 (80) | 0BFF0B40 | 00B40000 | 00BFF000 | 0 | 0 +PR4 (84) | 00000000 | 00000000 | 00000000 | 0 | 0 +``` + +Bingo! + +Now you can [flash internally](/flash_tutorial/int_flashrom.md). Remember to flash only the `bios` region (use `--ifd -i bios -N` flashrom arguments). `fd` and `me` are still locked. + +Note that you should have an external SPI programmer as a backup method. It will help you recover if you flash non-working ROM by mistake. -- To view, visit https://review.coreboot.org/c/coreboot/+/36666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d8551910c31fd2e6ff728e17dafaea45970166b Gerrit-Change-Number: 36666 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: soc/intel/cannonlake: Add IccMax limitation for CML U22
by Jamie Chen (Code Review) 04 Feb '20

04 Feb '20

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37189 ) Change subject: soc/intel/cannonlake: Add IccMax limitation for CML U22 ...................................................................... soc/intel/cannonlake: Add IccMax limitation for CML U22 IccMax[IA_CORE] for U22 is 35A. Add a limitation to avoid IccMax setting over 35A in fill_vr_domain_config function. BUG:b:145094963 BRANCH: None TEST: build coreboot and fsp with enabling fw_debug. Flashed to device and checked the log. IccMax of IA_CORE have been setted correctly. Change-Id: I2ae8feee3073884109e0d171511c5ac01064ffd7 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/soc/intel/cannonlake/vr_config.c 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/37189/1 diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 25270d8..671d93d 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -14,6 +14,9 @@ * */ +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <fsp/api.h> #include <soc/ramstage.h> #include <soc/vr_config.h> @@ -74,6 +77,8 @@ { FSP_S_CONFIG *vr_params = (FSP_S_CONFIG *)params; const struct vr_config *cfg; + struct device *sa_root; + uint16_t did; if (domain < 0 || domain >= NUM_VR_DOMAINS) return; @@ -96,4 +101,15 @@ vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; vr_params->AcLoadline[domain] = cfg->ac_loadline; vr_params->DcLoadline[domain] = cfg->dc_loadline; + + /* Limit IA_CORE IccMax if CPU SKU is U22 */ + if (domain == VR_IA_CORE) { + sa_root = pcidev_path_on_root(SA_DEVFN_ROOT); + did = pci_read_config16(sa_root, PCI_DEVICE_ID); + if (did == PCI_DEVICE_ID_INTEL_CML_ULT_2_2 && + cfg->icc_max > VR_CFG_AMP(35)) { + printk(BIOS_DEBUG, "VR_CONFIG: IccMax[IA_CORE] has been limited to 35A\n"); + vr_params->IccMax[domain] = VR_CFG_AMP(35); + } + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/37189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ae8feee3073884109e0d171511c5ac01064ffd7 Gerrit-Change-Number: 37189 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

7 18

Change in coreboot[master]: mb/lenovo/t520: Switch to overridetree
by Peter Lemenkov (Code Review) 01 Feb '20

01 Feb '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37295 ) Change subject: mb/lenovo/t520: Switch to overridetree ...................................................................... mb/lenovo/t520: Switch to overridetree Change-Id: If6be9cffe97dcd8f733e3bd5a67a408dd817005a Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t520/Kconfig R src/mainboard/lenovo/t520/devicetree.cb D src/mainboard/lenovo/t520/variants/t520/devicetree.cb A src/mainboard/lenovo/t520/variants/t520/overridetree.cb A src/mainboard/lenovo/t520/variants/w520/overridetree.cb 5 files changed, 26 insertions(+), 183 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37295/1 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index a6183d9..6d31be2 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -51,9 +51,9 @@ string default "lenovo/t520" -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config FMDFILE string diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb similarity index 98% rename from src/mainboard/lenovo/t520/variants/w520/devicetree.cb rename to src/mainboard/lenovo/t520/devicetree.cb index 8b2cbe7..49e57db 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -90,7 +90,7 @@ end # PCIe Port #4 Express Card device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY - device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520 + device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb deleted file mode 100644 index 0bfa18f..0000000 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ /dev/null @@ -1,180 +0,0 @@ -chip northbridge/intel/sandybridge - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "5" - register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms - register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms - register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" - - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0x0 on end - device lapic 0xacac off end - - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - register "pci_mmio_size" = "2048" - - device domain 0 on - subsystemid 0x17aa 0x21cf inherit - - device pci 00.0 on end # host bridge - device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on - subsystemid 0x17aa 0x21d1 - end # vga controller - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "alt_gp_smi_en" = "0x0000" - register "gpi1_routing" = "2" - register "gpi13_routing" = "2" - - # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) - register "sata_port_map" = "0x1f" - # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" - - register "gen1_dec" = "0x7c1601" - register "gen2_dec" = "0x0c15e1" - register "gen4_dec" = "0x0c06a1" - - # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" - - register "c2_latency" = "101" # c2 not supported - - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - - register "spi_uvscc" = "0x2005" - register "spi_lvscc" = "0x2005" - - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end - device pci 16.2 off end - device pci 16.3 off end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x17aa 0x21ce - end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 Express Card - device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 - device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY - device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI-2-PCI bridge - - device pci 1f.0 on #LPC bridge - chip ec/lenovo/pmh7 - device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa7" - register "config1" = "0x09" - register "config2" = "0xa0" - register "config3" = "0xc2" - - register "beepmask0" = "0x00" - register "beepmask1" = "0x86" - register "has_power_management_beeps" = "0" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xd0" - register "event5_enable" = "0xfc" - register "event6_enable" = "0x00" - register "event7_enable" = "0x01" - register "event8_enable" = "0x7b" - register "event9_enable" = "0xff" - register "eventa_enable" = "0x01" - register "eventb_enable" = "0x00" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - - register "has_wwan_detection" = "1" - register "wwan_gpio_num" = "70" - register "wwan_gpio_lvl" = "0" - end - chip drivers/lenovo/hybrid_graphics - device pnp ff.f on end # dummy - - register "detect_gpio" = "21" - - register "has_panel_hybrid_gpio" = "1" - register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" - - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" - - register "has_thinker1" = "1" - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBUS controller - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end # SMBus - device pci 1f.5 off end # IDE controller - device pci 1f.6 off end # Thermal controller - end - end -end diff --git a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb new file mode 100644 index 0000000..8016d10 --- /dev/null +++ b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb @@ -0,0 +1,16 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1e.0 off end # PCI-2-PCI bridge + device pci 1f.0 on # LPC bridge + chip ec/lenovo/h8 + register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end + end # LPC bridge + device pci 1f.5 off end # IDE controller + device pci 1f.6 off end # Thermal controller + end + end +end diff --git a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb new file mode 100644 index 0000000..a6f3738 --- /dev/null +++ b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb @@ -0,0 +1,7 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520 + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/37295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6be9cffe97dcd8f733e3bd5a67a408dd817005a Gerrit-Change-Number: 37295 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: toolchain: build the bootstrap part on recent FreeBSD setups
by Idwer Vollering (Code Review) 30 Jan '20

30 Jan '20

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34999 ) Change subject: toolchain: build the bootstrap part on recent FreeBSD setups ...................................................................... toolchain: build the bootstrap part on recent FreeBSD setups "Add support for -fuse-ld=lld, backported from GCC mainline which is going to become GCC 9 (in form of files/patch-fuse-ld=lld borrowed from devel/riscv64-gcc)." Obtained through: https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=227302 Change-Id: I3fa04283a2d306a9a11a1a0d929c6b7df2ac62fb Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- A util/crossgcc/patches/gcc-8.3.0_fbsd-ld-lld.patch 1 file changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/34999/1 diff --git a/util/crossgcc/patches/gcc-8.3.0_fbsd-ld-lld.patch b/util/crossgcc/patches/gcc-8.3.0_fbsd-ld-lld.patch new file mode 100644 index 0000000..dcf6b5a --- /dev/null +++ b/util/crossgcc/patches/gcc-8.3.0_fbsd-ld-lld.patch @@ -0,0 +1,88 @@ +diff -urN gcc-8.3.0-vanilla/gcc/collect2.c gcc-8.3.0/gcc/collect2.c +--- gcc-8.3.0-vanilla/gcc/collect2.c 2018-06-22 16:52:11.000000000 +0200 ++++ gcc-8.3.0/gcc/collect2.c 2019-08-19 21:57:22.771579000 +0200 +@@ -831,6 +831,7 @@ + USE_PLUGIN_LD, + USE_GOLD_LD, + USE_BFD_LD, ++ USE_LLD_LD, + USE_LD_MAX + } selected_linker = USE_DEFAULT_LD; + static const char *const ld_suffixes[USE_LD_MAX] = +@@ -838,7 +839,8 @@ + "ld", + PLUGIN_LD_SUFFIX, + "ld.gold", +- "ld.bfd" ++ "ld.bfd", ++ "ld.lld" + }; + static const char *const real_ld_suffix = "real-ld"; + static const char *const collect_ld_suffix = "collect-ld"; +@@ -1007,6 +1009,8 @@ + selected_linker = USE_BFD_LD; + else if (strcmp (argv[i], "-fuse-ld=gold") == 0) + selected_linker = USE_GOLD_LD; ++ else if (strcmp (argv[i], "-fuse-ld=lld") == 0) ++ selected_linker = USE_LLD_LD; + + #ifdef COLLECT_EXPORT_LIST + /* These flags are position independent, although their order +@@ -1096,7 +1100,8 @@ + /* Maybe we know the right file to use (if not cross). */ + ld_file_name = 0; + #ifdef DEFAULT_LINKER +- if (selected_linker == USE_BFD_LD || selected_linker == USE_GOLD_LD) ++ if (selected_linker == USE_BFD_LD || selected_linker == USE_GOLD_LD || ++ selected_linker == USE_LLD_LD) + { + char *linker_name; + # ifdef HOST_EXECUTABLE_SUFFIX +@@ -1315,7 +1320,7 @@ + else if (!use_collect_ld + && strncmp (arg, "-fuse-ld=", 9) == 0) + { +- /* Do not pass -fuse-ld={bfd|gold} to the linker. */ ++ /* Do not pass -fuse-ld={bfd|gold|lld} to the linker. */ + ld1--; + ld2--; + } +diff -urN gcc-8.3.0-vanilla/gcc/common.opt gcc-8.3.0/gcc/common.opt +--- gcc-8.3.0-vanilla/gcc/common.opt 2018-06-16 08:52:17.000000000 +0200 ++++ gcc-8.3.0/gcc/common.opt 2019-08-19 21:58:53.386201000 +0200 +@@ -2715,6 +2715,10 @@ + Common Driver Negative(fuse-ld=bfd) + Use the gold linker instead of the default linker. + ++fuse-ld=lld ++Common Driver Negative(fuse-ld=lld) ++Use the lld LLVM linker instead of the default linker. ++ + fuse-linker-plugin + Common Undocumented Var(flag_use_linker_plugin) + +diff -urN gcc-8.3.0-vanilla/gcc/doc/invoke.texi gcc-8.3.0/gcc/doc/invoke.texi +--- gcc-8.3.0-vanilla/gcc/doc/invoke.texi 2019-02-15 00:08:18.000000000 +0100 ++++ gcc-8.3.0/gcc/doc/invoke.texi 2019-08-19 22:05:27.979804000 +0200 +@@ -12259,6 +12259,10 @@ + @opindex fuse-ld=gold + Use the @command{gold} linker instead of the default linker. + ++@item -fuse-ld=lld ++@opindex fuse-ld=lld ++Use the LLVM @command{lld} linker instead of the default linker. ++ + @cindex Libraries + @item -l@var{library} + @itemx -l @var{library} +diff -urN gcc-8.3.0-vanilla/gcc/opts.c gcc-8.3.0/gcc/opts.c +--- gcc-8.3.0-vanilla/gcc/opts.c 2019-01-31 11:00:26.000000000 +0100 ++++ gcc-8.3.0/gcc/opts.c 2019-08-19 22:00:46.309476000 +0200 +@@ -2481,6 +2481,7 @@ + + case OPT_fuse_ld_bfd: + case OPT_fuse_ld_gold: ++ case OPT_fuse_ld_lld: + case OPT_fuse_linker_plugin: + /* No-op. Used by the driver and passed to us because it starts with f.*/ + break; -- To view, visit https://review.coreboot.org/c/coreboot/+/34999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fa04283a2d306a9a11a1a0d929c6b7df2ac62fb Gerrit-Change-Number: 34999 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: Kconfig: Display a warning if the board is updated incorrectly
by Martin Roth (Code Review) 26 Jan '20

26 Jan '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33641 Change subject: Kconfig: Display a warning if the board is updated incorrectly ...................................................................... Kconfig: Display a warning if the board is updated incorrectly Even though we have a comment to run make distclean before switching mainboards, people still ignore this and end up with confusing results. To try to fix this, save the mainboard directory in a Kconfig symbol that will not get updated when the mainboard gets changed. This allows us to compare it to the actual mainboard directory which will be updated when the platform changes and put up an obnoxious warning in the mainboard directory. Add another warning in the main menu, because the initial warning is probably going to be ignored. The main menu points to some documentation on how to fix the problem. Note that this will only catch issues going forward, and won't catch any already saved config that has a problem. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I2a1ccb62c7678f264015c87b9004be6a106f804a --- A Documentation/getting_started/fix_dot_config.md M src/Kconfig M src/mainboard/Kconfig 3 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33641/1 diff --git a/Documentation/getting_started/fix_dot_config.md b/Documentation/getting_started/fix_dot_config.md new file mode 100644 index 0000000..17d89d0 --- /dev/null +++ b/Documentation/getting_started/fix_dot_config.md @@ -0,0 +1,50 @@ +# How to repair your .config file + +## Overview +Many people rely on a saved .config file for building their +platform. This is reasonable, but can create unanticipated +problems. + +## TLDR +* Backup your .config: "cp .config .config_bak" +* Create the defconfig file: "make savedefconfig" +* Edit defconfig & delete unknown config lines: "vi defconfig" +* To just get rid of the warning about a bad .config, remove +* the CONFIG_MAINBOARD_CHECK line. +* The SMBIOS lines are probably incorrect as well. The ROM size +* is very suspect. Check the correct default for your platform. +* Save the defconfig +* Generate a new full config: +* "make -B defconfig KBUILD_DEFCONFIG=defconfig" + +## defconfig or "Mini config" +Instead of saving a "full" config, people should use a defconfig. +This is just the changes from a default coreboot configuration +file. It's significantly smaller, and when a new configuration option +gets added, it just takes the default value for that option when +expanded into a full .config. + +### Generating the defconfig file +To create the defconfig file, run "make savedefconfig". By default +this will generate the file in the root coreboot directory and call +it "defconfig". If there was already a file named "defconfig", this +will overwrite that file. + +### Contents of the defconfig file +As the defconfig file contains just the differences between the +platform and the default choices for the platform. For the current +default platform, the defconfig can actually be an empty file. + +Typically the defconfig will contain at least 2 lines - a +CONFIG_VENDOR_ line and a CONFIG_BOARD_ line. Again though, if you +are building the default board for any particular vendor, that line +may not be present. + +All additional lines in a defconfig file are options that the user +has specifically chosen to update in their config. + +### Generating a .config from a defconfig +To expand the defconfig so that can be used, run: + DFILE=defconfig; make -B defconfig KBUILD_DEFCONFIG=$DFILE + +You can point DFILE to any saved defconfig. diff --git a/src/Kconfig b/src/Kconfig index 72d826f..8eae329 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -16,6 +16,15 @@ mainmenu "coreboot configuration" +if MAINBOARD_CHECK != MAINBOARD_DIR +comment "***********************************************************************" +comment "WARNING: Your config is using defaults from a different mainboard " +comment "than you currently have set. We'd recommend that you delete your " +comment ".config file and start over, but if you want to try to repair the " +comment "file, see Documentation/getting_started/fix_dot_config.md " +comment "***********************************************************************" +endif + menu "General setup" config COREBOOT_BUILD @@ -1062,6 +1071,14 @@ mainboard code supports this. On supported Intel platforms this works by changing the settings in the descriptor.bin file. +config MAINBOARD_CHECK + string "Mainboard dir - Do not change manually" + default MAINBOARD_DIR + help + Check the platform. If this symbol doesn't match the currently + selected mainboard directory, give the user warnings that they're + probably doing something wrong. + endmenu diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index c88d317..d9216a9 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -1,5 +1,16 @@ comment "Important: Run 'make distclean' before switching boards" +if MAINBOARD_CHECK != MAINBOARD_DIR +comment "***********************************************************************" +comment "WARNING: Your config is using defaults from a different mainboard " +comment "than you currently have set. We'd recommend that you delete your " +comment ".config file and start over. " +comment "* *" +comment "If you ignore this warning and build anyway, you will almost certainly " +comment "get a bad rom with undefined results. " +comment "***********************************************************************" +endif + choice prompt "Mainboard vendor" default VENDOR_EMULATION -- To view, visit https://review.coreboot.org/c/coreboot/+/33641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1ccb62c7678f264015c87b9004be6a106f804a Gerrit-Change-Number: 33641 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: Console: Allow console UART to be enabled without serial console
by Martin Roth (Code Review) 26 Jan '20

26 Jan '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33380 Change subject: Console: Allow console UART to be enabled without serial console ...................................................................... Console: Allow console UART to be enabled without serial console Currently, when we disable serial console, the serial console uart remains uninitialized. This patch allows coreboot to still set up the UART, even if we're not sending the console to it. BUG=b:74392237 TEST=Verify UART still works, even with coreboot console disabled Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ic0942634ab8a9fcafdc1ea099721c127202e9f9a --- M src/console/Kconfig M src/drivers/uart/Kconfig M src/include/console/uart.h 3 files changed, 28 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/33380/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index 61ba667..da769d3 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -33,6 +33,7 @@ bool "Serial port console output" default y depends on DRIVERS_UART + select ENABLE_UART help Send coreboot debug output to a serial port. @@ -47,7 +48,7 @@ specific UART has to be used (e.g. when the platform code performs dangerous configurations). -if CONSOLE_SERIAL +if ENABLE_UART comment "I/O mapped, 8250-compatible" depends on DRIVERS_UART_8250IO @@ -79,13 +80,13 @@ Map the COM port number to the respective I/O port. comment "Serial port base address = 0x3f8" -depends on UART_FOR_CONSOLE = 0 +depends on UART_FOR_CONSOLE = 0 && DRIVERS_UART_8250IO comment "Serial port base address = 0x2f8" -depends on UART_FOR_CONSOLE = 1 +depends on UART_FOR_CONSOLE = 1 && DRIVERS_UART_8250IO comment "Serial port base address = 0x3e8" -depends on UART_FOR_CONSOLE = 2 +depends on UART_FOR_CONSOLE = 2 && DRIVERS_UART_8250IO comment "Serial port base address = 0x2e8" -depends on UART_FOR_CONSOLE = 3 +depends on UART_FOR_CONSOLE = 3 && DRIVERS_UART_8250IO config UART_OVERRIDE_BAUDRATE boolean @@ -156,7 +157,7 @@ default 3 depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM -endif # CONSOLE_SERIAL +endif # ENABLE_UART config SPKMODEM bool "spkmodem (console on speaker) console output" diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 1f23a19..9b242fd 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -1,6 +1,21 @@ config DRIVERS_UART bool +config ENABLE_UART + def_bool n + +config ENABLE_UART_WITHOUT_CONSOLE + bool "Always configure primary UART" + depends on DRIVERS_UART + select ENABLE_UART + help + The primary UART has previously only been set up when the serial console + is enabled. + Selecting this choice will configure the console UART even if the serial + console is disabled. + + Select the UART in the console menu + config DRIVERS_UART_8250IO # FIXME: Shouldn't have a prompt, should default to n, and # should be selected by boards that have it instead. diff --git a/src/include/console/uart.h b/src/include/console/uart.h index aed67c2..6bd88ae 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -67,11 +67,16 @@ (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_VERSTAGE || \ ENV_POSTCAR || (ENV_SMM && CONFIG(DEBUG_SMI)))) -#if __CONSOLE_SERIAL_ENABLE__ +#if CONFIG(ENABLE_UART) static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } +#else +static inline void __uart_init(void) {} +#endif + +#if __CONSOLE_SERIAL_ENABLE__ static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); @@ -81,7 +86,6 @@ uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } #else -static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0942634ab8a9fcafdc1ea099721c127202e9f9a Gerrit-Change-Number: 33380 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: src/[drivers|security]: Update headers refering to BSD license
by Martin Roth (Code Review) 26 Jan '20

26 Jan '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36183 ) Change subject: src/[drivers|security]: Update headers refering to BSD license ...................................................................... src/[drivers|security]: Update headers refering to BSD license Add a BSD 3-clause license file into the coreboot/LICENSES directory. This will have additional licenses added shortly. Update text of headers referring to the LICENSE file to refer to the BSD-3-Clause license in this directory. Add the coreboot project line to each header. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ia2ae0f32e62271102acaa9af7f0e0e5376f7c565 --- A LICENSES/BSD-3-Clause.txt M src/drivers/crb/tpm.c M src/drivers/crb/tpm.h M src/drivers/spi/tpm/tis.c M src/drivers/spi/tpm/tpm.c M src/drivers/spi/tpm/tpm.h M src/drivers/vpd/vpd.c M src/drivers/vpd/vpd.h M src/drivers/vpd/vpd_cbmem.c M src/drivers/vpd/vpd_decode.c M src/drivers/vpd/vpd_decode.h M src/drivers/vpd/vpd_tables.h M src/security/tpm/tss.h M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-1.2/tss_internal.h M src/security/tpm/tss/tcg-1.2/tss_structures.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.h M src/security/tpm/tss/tcg-2.0/tss_structures.h M src/security/tpm/tss/vendor/cr50/cr50.c M src/security/tpm/tss_errors.h 22 files changed, 142 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/36183/1 diff --git a/LICENSES/BSD-3-Clause.txt b/LICENSES/BSD-3-Clause.txt new file mode 100644 index 0000000..0741db7 --- /dev/null +++ b/LICENSES/BSD-3-Clause.txt @@ -0,0 +1,26 @@ +Copyright (c) <year> <owner>. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, +this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation +and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors +may be used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index 0393417..d6ebbb5 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -1,6 +1,8 @@ -/*. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. +/* + * This file is part of the coreboot project. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. * * This is a driver for a CRB Interface. * diff --git a/src/drivers/crb/tpm.h b/src/drivers/crb/tpm.h index 9bbed19..e78b785 100644 --- a/src/drivers/crb/tpm.h +++ b/src/drivers/crb/tpm.h @@ -1,7 +1,9 @@ /* + * This file is part of the coreboot project. + * * Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. * * This is a driver for a Command Response Buffer Interface */ diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c index b50ab0a..9a6d3d1 100644 --- a/src/drivers/spi/tpm/tis.c +++ b/src/drivers/spi/tpm/tis.c @@ -1,7 +1,10 @@ /* + * This file is part of the coreboot project. + * * Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ #include <arch/early_variables.h> diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index aad7610..028ebae 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -1,8 +1,13 @@ /* - * Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * This file is part of the coreboot project. * + * Copyright 2016 The Chromium OS Authors. All rights reserved. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES Directory. + */ + +/* * This is a driver for a SPI interfaced TPM2 device. * * It assumes that the required SPI interface has been initialized before the diff --git a/src/drivers/spi/tpm/tpm.h b/src/drivers/spi/tpm/tpm.h index 214d3bd..5081757 100644 --- a/src/drivers/spi/tpm/tpm.h +++ b/src/drivers/spi/tpm/tpm.h @@ -1,7 +1,10 @@ /* + * This file is part of the coreboot project. + * * Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ #ifndef __COREBOOT_SRC_DRIVERS_SPI_TPM_TPM_H diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index 10f5703..a031cef 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -1,7 +1,10 @@ /* + * This file is part of the coreboot project. + * * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ #include <arch/early_variables.h> diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index 14b002c..0fba9fd 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -1,7 +1,10 @@ /* + * This file is part of the coreboot project. + * * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ #ifndef __VPD_H__ diff --git a/src/drivers/vpd/vpd_cbmem.c b/src/drivers/vpd/vpd_cbmem.c index 5b68506..5ddf464 100644 --- a/src/drivers/vpd/vpd_cbmem.c +++ b/src/drivers/vpd/vpd_cbmem.c @@ -1,7 +1,10 @@ /* + * This file is part of the coreboot project. + * * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ #include <console/console.h> diff --git a/src/drivers/vpd/vpd_decode.c b/src/drivers/vpd/vpd_decode.c index 527c508..aad983a 100644 --- a/src/drivers/vpd/vpd_decode.c +++ b/src/drivers/vpd/vpd_decode.c @@ -1,7 +1,10 @@ /* + * This file is part of the coreboot project. + * * Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. * * This is a copy from upstream: * https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/lib/vpd_… diff --git a/src/drivers/vpd/vpd_decode.h b/src/drivers/vpd/vpd_decode.h index 5d595f3..1a2ab68 100644 --- a/src/drivers/vpd/vpd_decode.h +++ b/src/drivers/vpd/vpd_decode.h @@ -1,7 +1,10 @@ /* + * This file is part of the coreboot project. + * * Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. * * This is a copy from upstream: * https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/include/… diff --git a/src/drivers/vpd/vpd_tables.h b/src/drivers/vpd/vpd_tables.h index 4add5bd..ffe2e38 100644 --- a/src/drivers/vpd/vpd_tables.h +++ b/src/drivers/vpd/vpd_tables.h @@ -1,7 +1,10 @@ /* + * This file is part of the coreboot project. + * * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. * * Ported from mosys project (http://code.google.com/p/mosys/). */ diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 336935d..ac5fcc4 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -1,7 +1,11 @@ -/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. * Copyright (C) 2018-2019 Eltan B.V. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ /* diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index b11d6a3..15c685c 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -1,6 +1,10 @@ -/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ /* A lightweight TPM command library. diff --git a/src/security/tpm/tss/tcg-1.2/tss_internal.h b/src/security/tpm/tss/tcg-1.2/tss_internal.h index e999cb9..be337d8 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_internal.h +++ b/src/security/tpm/tss/tcg-1.2/tss_internal.h @@ -1,6 +1,10 @@ -/* Copyright (c) 2010 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2010 The Chromium OS Authors. All rights reserved. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ #ifndef TCG_TSS_INTERNAL_H_ diff --git a/src/security/tpm/tss/tcg-1.2/tss_structures.h b/src/security/tpm/tss/tcg-1.2/tss_structures.h index 50fa3fb..37744eb 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_structures.h +++ b/src/security/tpm/tss/tcg-1.2/tss_structures.h @@ -1,6 +1,10 @@ -/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. * * Some TPM constants and type definitions for standalone compilation for use * in the firmware diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 16e40fe..dd1f702 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -1,8 +1,11 @@ /* + * This file is part of the coreboot project. + * * Copyright 2016 The Chromium OS Authors. All rights reserved. * Copyright 2017-2019 Eltan B.V. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ #include <arch/early_variables.h> diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 1bf211a..b19483e 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -1,8 +1,11 @@ /* + * This file is part of the coreboot project. + * * Copyright 2016 The Chromium OS Authors. All rights reserved. * Copyright (c) 2018 Eltan B.V. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ #include <arch/early_variables.h> diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h index d34756d..0cf6388 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h @@ -1,7 +1,10 @@ /* + * This file is part of the coreboot project. + * * Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ #ifndef TCG2_TSS_MARSHALING_H_ #define TCG2_TSS_MARSHALING_H_ diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 1530613..fa97650 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -1,7 +1,10 @@ /* + * This file is part of the coreboot project. + * * Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ #ifndef TCG2_TSS_STRUCTURES_H_ diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c index 4f128dc..c5e820c 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.c +++ b/src/security/tpm/tss/vendor/cr50/cr50.c @@ -1,7 +1,10 @@ /* + * This file is part of the coreboot project. + * * Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. + * + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ #include <arch/early_variables.h> diff --git a/src/security/tpm/tss_errors.h b/src/security/tpm/tss_errors.h index ed6fc3d..23b71e0 100644 --- a/src/security/tpm/tss_errors.h +++ b/src/security/tpm/tss_errors.h @@ -1,6 +1,9 @@ -/* Copyright (c) 2010 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2010 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by the BSD-3-Clause license that can be + * found in the LICENSES directory. */ /* TPM error codes. -- To view, visit https://review.coreboot.org/c/coreboot/+/36183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2ae0f32e62271102acaa9af7f0e0e5376f7c565 Gerrit-Change-Number: 36183 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/lenovo/x201: Remove unnecessary PMH7 bits
by Arthur Heymans (Code Review) 26 Jan '20

26 Jan '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36911 ) Change subject: mb/lenovo/x201: Remove unnecessary PMH7 bits ...................................................................... mb/lenovo/x201: Remove unnecessary PMH7 bits The bits cleared by this mostly have to do with dGPU power, which this board lacks. TESTED: x201 still boots. Change-Id: I441743f76afc7bbbee930a1c8116035e85d94e52 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/romstage.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/36911/1 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index c8e8afb..58e34c8 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -55,9 +55,6 @@ void mainboard_pre_raminit(void) { - outb(0x50, 0x15ec); - outb(inb(0x15ee) & 0x70, 0x15ee); - set_fsb_frequency(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I441743f76afc7bbbee930a1c8116035e85d94e52 Gerrit-Change-Number: 36911 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: superio/nsc: Use common defines for NSC PC8xxxx chips
by Peter Lemenkov (Code Review) 24 Jan '20

24 Jan '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31427 Change subject: superio/nsc: Use common defines for NSC PC8xxxx chips ...................................................................... superio/nsc: Use common defines for NSC PC8xxxx chips * Some common NSC defines moved to superio/nsc/common * All NSC's pc8xxxx chips uses these common definitions * Lenovo T60/X60/Z61t/T400 docking updated to use these common defines * HP ProLiant DL165 G6 Fam10 updated to use this common code Build tested - Lenovo T60/X60/Z61t/T400, HP ProLiant DL165 G6 Fam10 builds fine. Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/lenovo/t400/dock.c M src/mainboard/lenovo/t60/dock.c M src/mainboard/lenovo/x60/dock.c M src/mainboard/lenovo/z61t/dock.c A src/superio/nsc/common/superio_defs.h D src/superio/nsc/pc87309/pc87309.h M src/superio/nsc/pc87309/superio.c D src/superio/nsc/pc87360/pc87360.h M src/superio/nsc/pc87360/superio.c D src/superio/nsc/pc87366/pc87366.h M src/superio/nsc/pc87366/superio.c D src/superio/nsc/pc87382/pc87382.h M src/superio/nsc/pc87382/superio.c D src/superio/nsc/pc87384/pc87384.h M src/superio/nsc/pc87384/superio.c D src/superio/nsc/pc87392/pc87392.h M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/pc87417.h M src/superio/nsc/pc87417/superio.c 20 files changed, 219 insertions(+), 369 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31427/1 diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 6d2eed4..7f5411e 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -34,6 +34,7 @@ #include <spd.h> #include <delay.h> #include <superio/serverengines/pilot/pilot.h> +#include <superio/nsc/common/superio_defs.h> #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> @@ -50,7 +51,7 @@ #include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) -#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) +#define RTC_DEV PNP_DEV(0x4e, PC8XXXX_RTC) void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index 6d1a80c..58788e7 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -23,7 +23,7 @@ #include <device/pnp.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87382/pc87382.h> +#include <superio/nsc/common/superio_defs.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <ec/lenovo/h8/h8.h> @@ -64,8 +64,8 @@ return 0; } -static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC87382_DOCK); -static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC87382_GPIO); +static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC8XXXX_DOCK); +static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC8XXXX_GPIO); static int pc87382_init(pnp_devfn_t dlpc, u16 dlpc_base) { @@ -170,20 +170,18 @@ /* Docking station side. */ -#include <superio/nsc/pc87384/pc87384.h> - -static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC87384_GPIO); -static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC87384_SP1); +static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC8XXXX_GPIO); +static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC8XXXX_SP1); static const struct pin_config remote_gpio[] = { - {0x00, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE}, - {0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE}, - {0x03, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x04, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x05, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x06, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x07, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, + {0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE}, + {0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE}, + {0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, }; static int pc87384_init(void) diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 05dd65e..57a5a00 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87384/pc87384.h> +#include <superio/nsc/common/superio_defs.h> #include "ec/acpi/ec.h" #include "ec/lenovo/pmh7/pmh7.h" #include <southbridge/intel/i82801gx/i82801gx.h> @@ -128,38 +128,38 @@ dock_write_register(0x22, 0xa9); /* enable serial port */ - dock_write_register(0x07, PC87384_SP1); + dock_write_register(0x07, PC8XXXX_SP1); dock_write_register(0x30, 0x01); - dock_write_register(0x07, PC87384_GPIO); + dock_write_register(0x07, PC8XXXX_GPIO); dock_write_register(0x60, 0x16); dock_write_register(0x61, 0x20); /* enable GPIO */ dock_write_register(0x30, 0x01); - dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* no GPIO events enabled for PORT0 */ diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index b94d818..cf5e71d 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -20,7 +20,7 @@ #include <delay.h> #include "dock.h" #include <southbridge/intel/i82801gx/i82801gx.h> -#include <superio/nsc/pc87392/pc87392.h> +#include <superio/nsc/common/superio_defs.h> static void dlpc_write_register(int reg, int value) { @@ -165,58 +165,58 @@ dock_write_register(0x61, 0x20); /* init GPIO pins */ - dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, - PC87392_GPIO_PIN_TRIGGERS_SMI); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, + PC8XXXX_GPIO_PIN_TRIGGERS_SMI); - dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP, 0x02); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_PULLUP, 0x02); - dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, - PC87392_GPIO_PIN_TRIGGERS_SMI); + dock_gpio_set_mode(0x10, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, + PC8XXXX_GPIO_PIN_TRIGGERS_SMI); - dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x11, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x12, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x13, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x14, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x15, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x16, PC8XXXX_GPIO_PIN_PULLUP | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x17, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x20, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x21, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x22, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x23, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x24, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x25, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x26, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x27, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x30, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x31, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x32, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x33, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x34, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x35, PC8XXXX_GPIO_PIN_PULLUP | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x36, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x37, PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* enable GPIO */ dock_write_register(0x30, 0x01); diff --git a/src/mainboard/lenovo/z61t/dock.c b/src/mainboard/lenovo/z61t/dock.c index 05dd65e..57a5a00 100644 --- a/src/mainboard/lenovo/z61t/dock.c +++ b/src/mainboard/lenovo/z61t/dock.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87384/pc87384.h> +#include <superio/nsc/common/superio_defs.h> #include "ec/acpi/ec.h" #include "ec/lenovo/pmh7/pmh7.h" #include <southbridge/intel/i82801gx/i82801gx.h> @@ -128,38 +128,38 @@ dock_write_register(0x22, 0xa9); /* enable serial port */ - dock_write_register(0x07, PC87384_SP1); + dock_write_register(0x07, PC8XXXX_SP1); dock_write_register(0x30, 0x01); - dock_write_register(0x07, PC87384_GPIO); + dock_write_register(0x07, PC8XXXX_GPIO); dock_write_register(0x60, 0x16); dock_write_register(0x61, 0x20); /* enable GPIO */ dock_write_register(0x30, 0x01); - dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* no GPIO events enabled for PORT0 */ diff --git a/src/superio/nsc/common/superio_defs.h b/src/superio/nsc/common/superio_defs.h new file mode 100644 index 0000000..cc35508 --- /dev/null +++ b/src/superio/nsc/common/superio_defs.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_NSC_COMMON_SUPERIO_DEFS_H +#define SUPERIO_NSC_COMMON_SUPERIO_DEFS_H + +#define PC8XXXX_FDC 0x00 /* Floppy */ +#define PC8XXXX_PP 0x01 /* Parallel port */ +#define PC8XXXX_SP2 0x02 /* COM 2 / IR */ +#define PC8XXXX_SP1 0x03 /* COM 1 */ +#define PC8XXXX_SWC 0x04 /* System wakeup control */ +//#define PC8XXXX_PM 0x04 /* Power management */ +#define PC8XXXX_KBCM 0x05 /* Mouse */ +#define PC8XXXX_KBCK 0x06 /* Keyboard */ +#define PC8XXXX_GPIO 0x07 /* General purpose IO */ +//#define PC8XXXX_HM 0x08 +#define PC8XXXX_FSD 0x08 /* Fan speed device */ +#define PC8XXXX_ACB 0x08 +#define PC8XXXX_FSCM 0x09 +#define PC8XXXX_FMC 0x09 +#define PC8XXXX_WDT 0x0A +#define PC8XXXX_GMP 0x0B +#define PC8XXXX_MIDI 0x0C +#define PC8XXXX_VLM 0x0D +#define PC8XXXX_TMS 0x0E +#define PC8XXXX_XBUS 0x0F +#define PC8XXXX_RTC 0x10 +#define PC8XXXX_MHC 0x14 +#define PC8XXXX_DOCK 0x19 + +#define PC8XXXX_GPIO_PIN_OE 0x01 +#define PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL 0x02 +#define PC8XXXX_GPIO_PIN_PULLUP 0x04 +#define PC8XXXX_GPIO_PIN_LOCK 0x08 +#define PC8XXXX_GPIO_PIN_TRIG_LEVEL 0x10 +#define PC8XXXX_GPIO_PIN_TRIG_LOW 0x20 +#define PC8XXXX_GPIO_PIN_DEBOUNCE 0x40 + +#define PC8XXXX_GPIO_PIN_TRIGGERS_IRQ 0x01 +#define PC8XXXX_GPIO_PIN_TRIGGERS_SMI 0x02 + +#endif /* SUPERIO_NSC_COMMON_SUPERIO_DEFS_H */ diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h deleted file mode 100644 index 3b912ea..0000000 --- a/src/superio/nsc/pc87309/pc87309.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87309_H -#define SUPERIO_NSC_PC87309_H - -/* Datasheet: PC87309 SuperI/O Plug and Play Compatible Chip. */ - -#define PC87309_FDC 0x00 /* Floppy */ -#define PC87309_PP 0x01 /* Parallel port */ -#define PC87309_SP2 0x02 /* Com2 / IR */ -#define PC87309_SP1 0x03 /* Com1 */ -#define PC87309_PM 0x04 /* Power management */ -#define PC87309_KBCM 0x05 /* Mouse */ -#define PC87309_KBCK 0x06 /* Keyboard */ - -#endif /* SUPERIO_NSC_PC87309_H */ diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index 458c501..f63bea9 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87309.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -28,7 +28,7 @@ return; switch (dev->path.pnp.device) { - case PC87309_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -43,14 +43,14 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87309_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, /* TODO: PM. */ - { NULL, PC87309_KBCM, PNP_IRQ0, }, - { NULL, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87360/pc87360.h b/src/superio/nsc/pc87360/pc87360.h deleted file mode 100644 index c969746..0000000 --- a/src/superio/nsc/pc87360/pc87360.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87360_H -#define SUPERIO_NSC_PC87360_H - -#define PC87360_FDC 0x00 /* Floppy */ -#define PC87360_PP 0x01 /* Parallel port */ -#define PC87360_SP2 0x02 /* Com2 */ -#define PC87360_SP1 0x03 /* Com1 */ -#define PC87360_SWC 0x04 -#define PC87360_KBCM 0x05 /* Mouse */ -#define PC87360_KBCK 0x06 /* Keyboard */ -#define PC87360_GPIO 0x07 -#define PC87360_ACB 0x08 -#define PC87360_FSCM 0x09 -#define PC87360_WDT 0x0A - -#endif /* SUPERIO_NSC_PC87360_H */ diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index cf5c7ca..85f21a2 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -21,7 +21,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87360.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -29,7 +29,7 @@ return; switch (dev->path.pnp.device) { - case PC87360_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -44,18 +44,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87360_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87360_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87360_KBCM, PNP_IRQ0, }, - { NULL, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87366/pc87366.h b/src/superio/nsc/pc87366/pc87366.h deleted file mode 100644 index b1df69f..0000000 --- a/src/superio/nsc/pc87366/pc87366.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87366_H -#define SUPERIO_NSC_PC87366_H - -#define PC87366_FDC 0x00 /* Floppy */ -#define PC87366_PP 0x01 /* Parallel port */ -#define PC87366_SP2 0x02 /* Com2 */ -#define PC87366_SP1 0x03 /* Com1 */ -#define PC87366_SWC 0x04 -#define PC87366_KBCM 0x05 /* Mouse */ -#define PC87366_KBCK 0x06 /* Keyboard */ -#define PC87366_GPIO 0x07 -#define PC87366_ACB 0x08 -#define PC87366_FSCM 0x09 -#define PC87366_WDT 0x0A -#define PC87366_GMP 0x0b -#define PC87366_MIDI 0x0C -#define PC87366_VLM 0x0D -#define PC87366_TMS 0x0E - -#endif /* SUPERIO_NSC_PC87366_H */ diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index e1cba17..60e5e23 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -21,7 +21,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87366.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -29,7 +29,7 @@ return; switch (dev->path.pnp.device) { - case PC87366_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -44,18 +44,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87366_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87366_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87366_KBCM, PNP_IRQ0, }, - { NULL, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87382/pc87382.h b/src/superio/nsc/pc87382/pc87382.h deleted file mode 100644 index 6826f45..0000000 --- a/src/superio/nsc/pc87382/pc87382.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87382_H -#define SUPERIO_NSC_PC87382_H - -#define PC87382_IR 0x02 -#define PC87382_SP1 0x03 -#define PC87382_GPIO 0x07 -#define PC87382_DOCK 0x19 -#endif diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 688f08c..6a21f51 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87382.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -27,10 +27,10 @@ return; switch (dev->path.pnp.device) { - case PC87382_DOCK: + case PC8XXXX_DOCK: break; - case PC87382_GPIO: + case PC8XXXX_GPIO: break; } } @@ -44,11 +44,11 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87382_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8 }, - { NULL, PC87382_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87382_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, - { NULL, PC87382_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, + { NULL, PC8XXXX_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87384/pc87384.h b/src/superio/nsc/pc87384/pc87384.h deleted file mode 100644 index 2184584..0000000 --- a/src/superio/nsc/pc87384/pc87384.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87384_H -#define SUPERIO_NSC_PC87384_H - -#define PC87384_PP 0x01 -#define PC87384_SP2 0x02 -#define PC87384_SP1 0x03 -#define PC87384_GPIO 0x07 - -#define PC87384_GPIO_PIN_OE 0x01 -#define PC87384_GPIO_PIN_TYPE_PUSH_PULL 0x02 -#define PC87384_GPIO_PIN_PULLUP 0x04 -#define PC87384_GPIO_PIN_LOCK 0x08 -#define PC87384_GPIO_PIN_TRIG_LEVEL 0x10 -#define PC87384_GPIO_PIN_TRIG_LOW 0x20 -#define PC87384_GPIO_PIN_DEBOUNCE 0x40 - -#define PC87384_GPIO_PIN_TRIGGERS_IRQ 0x01 - -#endif diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index f34acd5..9548d2c 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87384.h" +#include <superio/nsc/common/superio_defs.h> static struct device_operations ops = { .read_resources = pnp_read_resources, @@ -29,10 +29,10 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87384_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87384_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87384_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87392/pc87392.h b/src/superio/nsc/pc87392/pc87392.h deleted file mode 100644 index 5832435..0000000 --- a/src/superio/nsc/pc87392/pc87392.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87392_H -#define SUPERIO_NSC_PC87392_H - -#define PC87392_FDC 0x00 -#define PC87392_PP 0x01 -#define PC87392_SP2 0x02 -#define PC87392_SP1 0x03 -#define PC87392_GPIO 0x07 -#define PC87392_WDT 0x0A - -#define PC87392_GPIO_PIN_OE 0x01 -#define PC87392_GPIO_PIN_TYPE_PUSH_PULL 0x02 -#define PC87392_GPIO_PIN_PULLUP 0x04 -#define PC87392_GPIO_PIN_LOCK 0x08 -#define PC87392_GPIO_PIN_TRIG_LEVEL 0x10 -#define PC87392_GPIO_PIN_TRIG_LOW 0x20 -#define PC87392_GPIO_PIN_DEBOUNCE 0x40 - -#define PC87392_GPIO_PIN_TRIGGERS_IRQ 0x01 -#define PC87392_GPIO_PIN_TRIGGERS_SMI 0x02 - -#endif diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index edd4619..9971b5c 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87392.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -36,13 +36,13 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87392_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87392_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87392_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8 }, - { NULL, PC87392_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87392_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 }, - { NULL, PC87392_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index b50a920..e6c7f79 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -19,17 +19,6 @@ #ifndef SUPERIO_NSC_PC87417_H #define SUPERIO_NSC_PC87417_H -#define PC87417_FDC 0x00 /* Floppy */ -#define PC87417_PP 0x01 /* Parallel Port */ -#define PC87417_SP2 0x02 /* Com2 */ -#define PC87417_SP1 0x03 /* Com1 */ -#define PC87417_SWC 0x04 /* System Wake-Up Controller (SWC) */ -#define PC87417_KBCM 0x05 /* Mouse */ -#define PC87417_KBCK 0x06 /* Keyboard */ -#define PC87417_GPIO 0x07 -#define PC87417_XBUS 0x0F -#define PC87417_RTC 0x10 - #define PC87417_GPIO_DEV PNP_DEV(0x2e, PC87417_GPIO) /* This is to get around a romcc bug */ /* #define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS) */ diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index f0e0bb1..a4e8022 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -22,7 +22,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87417.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -30,7 +30,7 @@ return; switch (dev->path.pnp.device) { - case PC87417_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -45,17 +45,17 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87417_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87417_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87417_KBCM, PNP_IRQ0, }, - { NULL, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, }, - { NULL, PC87417_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, }, + { NULL, PC8XXXX_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, }, }; static void enable_dev(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/31427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485 Gerrit-Change-Number: 31427 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: src/superio: Remove unused superio chips
by Martin Roth (Code Review) 23 Jan '20

23 Jan '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35428 ) Change subject: src/superio: Remove unused superio chips ...................................................................... src/superio: Remove unused superio chips These SIOs are not being used or tested by abuild, so remove them from the tree. src/superio/fintek/f71805f src/superio/fintek/f71872 src/superio/intel/i8900 src/superio/ite/it8613e src/superio/ite/it8671f src/superio/ite/it8716f src/superio/ite/it8786e src/superio/nsc/pc87309 src/superio/nsc/pc87360 src/superio/nsc/pc87366 src/superio/nsc/pc97317 src/superio/nuvoton/nct5539d src/superio/smsc/dme1737 src/superio/smsc/lpc47b272 src/superio/smsc/lpc47b397 src/superio/smsc/sch4037 src/superio/smsc/sio1036 src/superio/via/vt1211 src/superio/winbond/w83697hf src/superio/winbond/wpcd376i Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I61d486d2c1e2b85eb292eaa78316c36e1735ebf4 --- D src/superio/fintek/f71805f/Kconfig D src/superio/fintek/f71805f/Makefile.inc D src/superio/fintek/f71805f/f71805f.h D src/superio/fintek/f71805f/superio.c D src/superio/fintek/f71872/Kconfig D src/superio/fintek/f71872/Makefile.inc D src/superio/fintek/f71872/f71872.h D src/superio/fintek/f71872/superio.c D src/superio/intel/i8900/Kconfig D src/superio/intel/i8900/Makefile.inc D src/superio/intel/i8900/early_serial.c D src/superio/intel/i8900/i8900.h D src/superio/intel/i8900/superio.c D src/superio/ite/it8613e/Kconfig D src/superio/ite/it8613e/Makefile.inc D src/superio/ite/it8613e/chip.h D src/superio/ite/it8613e/it8613e.h D src/superio/ite/it8613e/superio.c D src/superio/ite/it8671f/Kconfig D src/superio/ite/it8671f/Makefile.inc D src/superio/ite/it8671f/early_serial.c D src/superio/ite/it8671f/it8671f.h D src/superio/ite/it8671f/superio.c D src/superio/ite/it8716f/Kconfig D src/superio/ite/it8716f/Makefile.inc D src/superio/ite/it8716f/it8716f.h D src/superio/ite/it8716f/superio.c D src/superio/ite/it8786e/Kconfig D src/superio/ite/it8786e/Makefile.inc D src/superio/ite/it8786e/acpi/superio.asl D src/superio/ite/it8786e/chip.h D src/superio/ite/it8786e/it8786e.h D src/superio/ite/it8786e/superio.c D src/superio/nsc/pc87309/Kconfig D src/superio/nsc/pc87309/Makefile.inc D src/superio/nsc/pc87309/pc87309.h D src/superio/nsc/pc87309/superio.c D src/superio/nsc/pc87360/Kconfig D src/superio/nsc/pc87360/Makefile.inc D src/superio/nsc/pc87360/pc87360.h D src/superio/nsc/pc87360/superio.c D src/superio/nsc/pc87366/Kconfig D src/superio/nsc/pc87366/Makefile.inc D src/superio/nsc/pc87366/pc87366.h D src/superio/nsc/pc87366/superio.c D src/superio/nsc/pc97317/Kconfig D src/superio/nsc/pc97317/Makefile.inc D src/superio/nsc/pc97317/early_serial.c D src/superio/nsc/pc97317/pc97317.h D src/superio/nsc/pc97317/superio.c M src/superio/nuvoton/common/early_serial.c D src/superio/nuvoton/nct5539d/Kconfig D src/superio/nuvoton/nct5539d/Makefile.inc D src/superio/nuvoton/nct5539d/nct5539d.h D src/superio/nuvoton/nct5539d/superio.c D src/superio/smsc/dme1737/Kconfig D src/superio/smsc/dme1737/Makefile.inc D src/superio/smsc/dme1737/dme1737.h D src/superio/smsc/dme1737/early_serial.c D src/superio/smsc/dme1737/superio.c D src/superio/smsc/lpc47b272/Kconfig D src/superio/smsc/lpc47b272/Makefile.inc D src/superio/smsc/lpc47b272/early_serial.c D src/superio/smsc/lpc47b272/lpc47b272.h D src/superio/smsc/lpc47b272/superio.c D src/superio/smsc/lpc47b397/Kconfig D src/superio/smsc/lpc47b397/Makefile.inc D src/superio/smsc/lpc47b397/early_serial.c D src/superio/smsc/lpc47b397/lpc47b397.h D src/superio/smsc/lpc47b397/superio.c D src/superio/smsc/sch4037/Kconfig D src/superio/smsc/sch4037/Makefile.inc D src/superio/smsc/sch4037/sch4037.h D src/superio/smsc/sch4037/sch4037_early_init.c D src/superio/smsc/sch4037/superio.c D src/superio/smsc/sio1036/Kconfig D src/superio/smsc/sio1036/Makefile.inc D src/superio/smsc/sio1036/sio1036.h D src/superio/smsc/sio1036/sio1036_early_init.c D src/superio/smsc/sio1036/superio.c D src/superio/via/vt1211/Kconfig D src/superio/via/vt1211/Makefile.inc D src/superio/via/vt1211/superio.c D src/superio/via/vt1211/vt1211.h D src/superio/winbond/w83697hf/Kconfig D src/superio/winbond/w83697hf/Makefile.inc D src/superio/winbond/w83697hf/chip.h D src/superio/winbond/w83697hf/superio.c D src/superio/winbond/w83697hf/w83697hf.h D src/superio/winbond/wpcd376i/Kconfig D src/superio/winbond/wpcd376i/Makefile.inc D src/superio/winbond/wpcd376i/chip.h D src/superio/winbond/wpcd376i/early_serial.c D src/superio/winbond/wpcd376i/superio.c D src/superio/winbond/wpcd376i/wpcd376i.h 95 files changed, 0 insertions(+), 4,058 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35428/1 diff --git a/src/superio/fintek/f71805f/Kconfig b/src/superio/fintek/f71805f/Kconfig deleted file mode 100644 index 7f06f55..0000000 --- a/src/superio/fintek/f71805f/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_FINTEK_F71805F - bool - select SUPERIO_FINTEK_COMMON_PRE_RAM diff --git a/src/superio/fintek/f71805f/Makefile.inc b/src/superio/fintek/f71805f/Makefile.inc deleted file mode 100644 index 26b23f6..0000000 --- a/src/superio/fintek/f71805f/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.c diff --git a/src/superio/fintek/f71805f/f71805f.h b/src/superio/fintek/f71805f/f71805f.h deleted file mode 100644 index b4ca60a..0000000 --- a/src/superio/fintek/f71805f/f71805f.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_FINTEK_F71805F_H -#define SUPERIO_FINTEK_F71805F_H - -/* - * Datasheet: - * - Name: F71805F/FG Super H/W Monitor + LPC IO - * - URL: http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17 - * - PDF: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf - * - Revision: V0.25P - */ - -/* Logical Device Numbers (LDN). */ -#define F71805F_FDC 0x00 /* Floppy */ -#define F71805F_SP1 0x01 /* UART1 */ -#define F71805F_SP2 0x02 /* UART2 */ -#define F71805F_PP 0x03 /* Parallel port */ -#define F71805F_HWM 0x04 /* Hardware monitor */ -#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F71805F_PME 0x0a /* Power Management Events (PME) */ - -#endif /* SUPERIO_FINTEK_F71805F_H */ diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c deleted file mode 100644 index 4719923..0000000 --- a/src/superio/fintek/f71805f/superio.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <superio/conf_mode.h> -#include <stdlib.h> -#include "f71805f.h" - -static void f71805f_init(struct device *dev) -{ - if (!dev->enabled) - return; - - /* TODO: Might potentially need code for HWM or FDC etc. */ -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = f71805f_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - /* TODO: Some of the 0x07f8 etc. values may not be correct. */ - { NULL, F71805F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, F71805F_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, F71805F_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, F71805F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, F71805F_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, - { NULL, F71805F_GPIO, PNP_IRQ0, }, - { NULL, F71805F_PME, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_fintek_f71805f_ops = { - CHIP_NAME("Fintek F71805F/FG Super I/O") - .enable_dev = enable_dev -}; diff --git a/src/superio/fintek/f71872/Kconfig b/src/superio/fintek/f71872/Kconfig deleted file mode 100644 index 516ff094..0000000 --- a/src/superio/fintek/f71872/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_FINTEK_F71872 - bool - select SUPERIO_FINTEK_COMMON_PRE_RAM diff --git a/src/superio/fintek/f71872/Makefile.inc b/src/superio/fintek/f71872/Makefile.inc deleted file mode 100644 index 7237d0b..0000000 --- a/src/superio/fintek/f71872/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_FINTEK_F71872) += superio.c diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h deleted file mode 100644 index afd238c..0000000 --- a/src/superio/fintek/f71872/f71872.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_FINTEK_F71872_H -#define SUPERIO_FINTEK_F71872_H - -/* Logical Device Numbers (LDN). */ -#define F71872_FDC 0x00 /* Floppy */ -#define F71872_SP1 0x01 /* UART1 */ -#define F71872_SP2 0x02 /* UART2 */ -#define F71872_PP 0x03 /* Parallel Port */ -#define F71872_HWM 0x04 /* Hardware Monitor */ -#define F71872_KBC 0x05 /* Keyboard/Mouse */ -#define F71872_GPIO 0x06 /* GPIO */ -#define F71872_VID 0x07 /* VID */ -#define F71872_PM 0x0a /* ACPI/PME */ - -#endif /* SUPERIO_FINTEK_F71872_H */ diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c deleted file mode 100644 index 3316ee2..0000000 --- a/src/superio/fintek/f71872/superio.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <superio/conf_mode.h> -#include <stdlib.h> -#include <pc80/keyboard.h> -#include "f71872.h" - -static void f71872_init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - /* TODO: Might potentially need code for HWM or FDC etc. */ - case F71872_KBC: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = f71872_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - /* TODO: Some of the 0x07f8 etc. values may not be correct. */ - { NULL, F71872_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, F71872_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, F71872_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, F71872_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, F71872_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, - { NULL, F71872_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, }, - { NULL, F71872_GPIO, PNP_IRQ0, }, - { NULL, F71872_VID, PNP_IO0, 0x0ff8, }, - { NULL, F71872_PM, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_fintek_f71872_ops = { - CHIP_NAME("Fintek F71872 Super I/O") - .enable_dev = enable_dev -}; diff --git a/src/superio/intel/i8900/Kconfig b/src/superio/intel/i8900/Kconfig deleted file mode 100644 index ed37f7f..0000000 --- a/src/superio/intel/i8900/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_INTEL_I8900 - bool diff --git a/src/superio/intel/i8900/Makefile.inc b/src/superio/intel/i8900/Makefile.inc deleted file mode 100644 index 562d5d1..0000000 --- a/src/superio/intel/i8900/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Arastra, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_INTEL_I8900) += early_serial.c -romstage-$(CONFIG_SUPERIO_INTEL_I8900) += early_serial.c -ramstage-$(CONFIG_SUPERIO_INTEL_I8900) += superio.c diff --git a/src/superio/intel/i8900/early_serial.c b/src/superio/intel/i8900/early_serial.c deleted file mode 100644 index 681b225..0000000 --- a/src/superio/intel/i8900/early_serial.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pnp_ops.h> -#include <device/pnp.h> -#include "i8900.h" - -static void pnp_enter_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - - outb(0x80, port); - outb(0x86, port); -} - -static void pnp_exit_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - - outb(0x68, port); - outb(0x08, port); -} - -/* Enable device interrupts, set UART_CLK predivide. */ -void i8900_configure_uart_clk(pnp_devfn_t dev, u8 predivide) -{ - pnp_enter_ext_func_mode(dev); - pnp_write_config(dev, I8900_SIW_CONFIGURATION, - (predivide << 2) | I8900_ENABLE_SIRQ); - pnp_exit_ext_func_mode(dev); -} - -void i8900_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} - -void i8900_enable_wdt(pnp_devfn_t dev, u16 iobase) -{ - /* Enable WDT */ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/intel/i8900/i8900.h b/src/superio/intel/i8900/i8900.h deleted file mode 100644 index 348d3c4..0000000 --- a/src/superio/intel/i8900/i8900.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_INTEL_I8900_I8900_H -#define SUPERIO_INTEL_I8900_I8900_H - -#include <device/pnp_type.h> - -/* - * The SIW ("Serial I/O and Watchdog Timer") integrated into the i8900 is - * very similar to a Super I/O, both in functionality and config mechanism. - * - * The SIW contains: - * - UART(s) - * - Serial interrupt controller - * - Watchdog timer (WDT) - * - LPC interface - */ - -/* Logical device numbers (LDNs). */ -#define I8900_SP1 0x04 /* Com1 */ -#define I8900_SP2 0x05 /* Com2 */ -#define I8900_WDT 0x06 /* Watchdog timer */ - -/* Registers and bit definitions: */ - -#define I8900_SIW_CONFIGURATION 0x29 - -/* - * SIW_CONFIGURATION[3:2] = UART_CLK predivide - * 00: divide by 1 - * 01: divide by 8 - * 10: divide by 26 - * 11: reserved - */ -#define I8900_UART_CLK_PREDIVIDE_1 0x00 -#define I8900_UART_CLK_PREDIVIDE_8 0x01 -#define I8900_UART_CLK_PREDIVIDE_26 0x02 -#define I8900_ENABLE_SIRQ 0x01 - -void i8900_configure_uart_clk(pnp_devfn_t dev, u8 predivide); -void i8900_enable_serial(pnp_devfn_t dev, u16 iobase); -void i8900_enable_wdt(pnp_devfn_t dev, u16 iobase); - -#endif diff --git a/src/superio/intel/i8900/superio.c b/src/superio/intel/i8900/superio.c deleted file mode 100644 index 24805bc..0000000 --- a/src/superio/intel/i8900/superio.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdlib.h> -#include <device/device.h> -#include <device/pnp.h> -#include <drivers/uart/uart8250reg.h> -#include "i8900.h" -#include <arch/io.h> - -static void pnp_enter_ext_func_mode(struct device *dev) -{ - outb(0x80, dev->path.pnp.port); - outb(0x86, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(struct device *dev) -{ - outb(0x68, dev->path.pnp.port); - outb(0x08, dev->path.pnp.port); -} - -static void i8900_init(struct device *dev) -{ - if (!dev->enabled) - return; -} - -static void i8900_pnp_set_resources(struct device *dev) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_resources(dev); - pnp_exit_ext_func_mode(dev); -} - -static void i8900_pnp_enable_resources(struct device *dev) -{ - pnp_enter_ext_func_mode(dev); - pnp_enable_resources(dev); - pnp_exit_ext_func_mode(dev); -} - -static void i8900_pnp_enable(struct device *dev) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); - pnp_exit_ext_func_mode(dev); -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = i8900_pnp_set_resources, - .enable_resources = i8900_pnp_enable_resources, - .enable = i8900_pnp_enable, - .init = i8900_init, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, I8900_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, I8900_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, I8900_WDT, PNP_IO0 | PNP_IRQ0, 0x07f8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_intel_i8900_ops = { - CHIP_NAME("Intel 8900 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig deleted file mode 100644 index f09cac2..0000000 --- a/src/superio/ite/it8613e/Kconfig +++ /dev/null @@ -1,27 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> -## Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com> -## Copyright (C) 2018 Kevin Cody-Little <kcodyjr(a)gmail.com> -## Copyright (C) 2019 Protectli -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_ITE_IT8613E - bool - select SUPERIO_ITE_COMMON_PRE_RAM - select SUPERIO_ITE_ENV_CTRL - select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 - select SUPERIO_ITE_ENV_CTRL_8BIT_PWM - select SUPERIO_ITE_ENV_CTRL_5FANS - select SUPERIO_ITE_ENV_CTRL_NO_ONOFF diff --git a/src/superio/ite/it8613e/Makefile.inc b/src/superio/ite/it8613e/Makefile.inc deleted file mode 100644 index 75ab26b..0000000 --- a/src/superio/ite/it8613e/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> -## Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com> -## Copyright (C) 2019 Protectli -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_ITE_IT8613E) += superio.c diff --git a/src/superio/ite/it8613e/chip.h b/src/superio/ite/it8613e/chip.h deleted file mode 100644 index 65875c8..0000000 --- a/src/superio/ite/it8613e/chip.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * Copyright (C) 2019 Protectli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_ITE_IT8613E_CHIP_H -#define SUPERIO_ITE_IT8613E_CHIP_H - -#include <superio/ite/common/env_ctrl_chip.h> - -struct superio_ite_it8613e_config { - struct ite_ec_config ec; -}; - -#endif /* SUPERIO_ITE_IT8613E_CHIP_H */ diff --git a/src/superio/ite/it8613e/it8613e.h b/src/superio/ite/it8613e/it8613e.h deleted file mode 100644 index 890c249..0000000 --- a/src/superio/ite/it8613e/it8613e.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com> - * Copyright (C) 2019 Protectli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_ITE_IT8613E_H -#define SUPERIO_ITE_IT8613E_H - -/* - * IT8613 supports 2 clock inputs: PCICLK and CLKIN. Multiple registers need - * to be set to choose proper source. PCICLK is required for LPC. - * - * In the table below PD means pull-down, X - don't care. - * - * |-------------------------------------------------------------------| - * | CLKIN | PCICLK | LDN7\ | GBL\ | LDN7\ | LDN7\ | GBL\ | - * | | | 71h[3] | 23h[3] | 2Dh[2] | 2Dh[1] | 23h[0] | - * |--------+--------+---------+---------+---------+---------+---------| - * | PD | 33 MHz | X | 0 | 0 | 0 | 0 | - * | PD | 24 MHz | 1 | 1 | X | 0 | 1 | - * | PD | 25 MHz | X | 0 | 1 | 0 | 0 | - * | 24 MHz | X | 0 | 1 | X | 0 | 1 | - * | 48 MHz | X | 0 | 1 | X | 0 | 0 | - * |-------------------------------------------------------------------| - * - */ - -#define IT8613E_SP1 0x01 /* Com1 */ -#define IT8613E_EC 0x04 /* Environment controller */ -#define IT8613E_KBCK 0x05 /* PS/2 keyboard */ -#define IT8613E_KBCM 0x06 /* PS/2 mouse */ -#define IT8613E_GPIO 0x07 /* GPIO */ -#define IT8613E_CIR 0x0a /* Consumer Infrared */ - -#endif /* SUPERIO_ITE_IT8613E_H */ diff --git a/src/superio/ite/it8613e/superio.c b/src/superio/ite/it8613e/superio.c deleted file mode 100644 index 7a4e336..0000000 --- a/src/superio/ite/it8613e/superio.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> - * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com> - * Copyright (C) 2019 Protectli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <pc80/keyboard.h> -#include <superio/conf_mode.h> -#include <superio/ite/common/env_ctrl.h> - -#include "chip.h" -#include "it8613e.h" - -static void it8613e_init(struct device *dev) -{ - const struct superio_ite_it8613e_config *conf = dev->chip_info; - const struct resource *res; - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case IT8613E_EC: - res = find_resource(dev, PNP_IDX_IO0); - if (!conf || !res) - break; - ite_ec_init(res->base, &conf->ec); - break; - case IT8613E_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - case IT8613E_KBCM: - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = it8613e_init, - .ops_pnp_mode = &pnp_conf_mode_870155_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - /* Serial Port 1 */ - { NULL, IT8613E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, - /* Environmental Controller */ - { NULL, IT8613E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ff8, }, - /* KBC Keyboard */ - { NULL, IT8613E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, - 0x0fff, 0x0fff, }, - /* KBC Mouse */ - { NULL, IT8613E_KBCM, PNP_IRQ0 | PNP_MSC0, }, - /* GPIO */ - { NULL, IT8613E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ffc, 0x0ff8, }, - /* Consumer Infrared */ - { NULL, IT8613E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_ite_it8613e_ops = { - CHIP_NAME("ITE IT8613E Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/ite/it8671f/Kconfig b/src/superio/ite/it8671f/Kconfig deleted file mode 100644 index ba63224..0000000 --- a/src/superio/ite/it8671f/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_ITE_IT8671F - bool - select SUPERIO_ITE_COMMON_PRE_RAM diff --git a/src/superio/ite/it8671f/Makefile.inc b/src/superio/ite/it8671f/Makefile.inc deleted file mode 100644 index f625bc1..0000000 --- a/src/superio/ite/it8671f/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_ITE_IT8671F) += early_serial.c -romstage-$(CONFIG_SUPERIO_ITE_IT8671F) += early_serial.c -ramstage-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.c diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c deleted file mode 100644 index b5b94df..0000000 --- a/src/superio/ite/it8671f/early_serial.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pnp_type.h> -#include <device/pnp.h> -#include <stdint.h> -#include "it8671f.h" - -/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ -#define SIO_BASE 0x3f0 -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8671F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8671F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */ -#define IT8671F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */ - -#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */ - -/* - * Special values used for entering MB PnP mode. The first four bytes of - * each line determine the address port, the last four are data. - */ -static const u8 init_values[] = { - 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, - 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, - 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, - 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, -}; - -static void it8671f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8671F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -/* Enter the configuration state (MB PnP mode). */ -static void it8671f_enter_conf(void) -{ - int i; - - /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ - /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ - /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ - /* Base address 0x370: 0x86 0x80 0xaa 0x55. */ - outb(0x86, IT8671F_CONFIGURATION_PORT); - outb(0x80, IT8671F_CONFIGURATION_PORT); - outb(0x55, IT8671F_CONFIGURATION_PORT); - outb(0x55, IT8671F_CONFIGURATION_PORT); - - /* Sequentially write the 32 special values. */ - for (i = 0; i < 32; i++) - outb(init_values[i], SIO_BASE); -} - -/* Exit the configuration state (MB PnP mode). */ -static void it8671f_exit_conf(void) -{ - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); -} - -/* Select 48MHz CLKIN (24MHz is the default). */ -void it8671f_48mhz_clkin(void) -{ - it8671f_enter_conf(); - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, (1 << 6)); - it8671f_exit_conf(); -} - -/* Enable the serial port(s). */ -void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - it8671f_enter_conf(); - - /* - * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), - * PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). - */ - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f); - - /* Enable serial port(s). */ - it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */ - it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */ - - it8671f_exit_conf(); -} diff --git a/src/superio/ite/it8671f/it8671f.h b/src/superio/ite/it8671f/it8671f.h deleted file mode 100644 index 5fe74bc..0000000 --- a/src/superio/ite/it8671f/it8671f.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_ITE_IT8671F_H -#define SUPERIO_ITE_IT8671F_H - -#include <device/pnp_type.h> -#include <stdint.h> - -/* Datasheet: Not available online, got it from ITE per request. */ - -#define IT8671F_FDC 0x00 /* Floppy */ -#define IT8671F_SP1 0x01 /* Com1 */ -#define IT8671F_SP2 0x02 /* Com2 */ -#define IT8671F_PP 0x03 /* Parallel port */ -#define IT8671F_KBCK 0x05 /* PS/2 keyboard */ -#define IT8671F_KBCM 0x06 /* PS/2 mouse */ - -void it8671f_48mhz_clkin(void); -void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif /* SUPERIO_ITE_IT8671F_H */ diff --git a/src/superio/ite/it8671f/superio.c b/src/superio/ite/it8671f/superio.c deleted file mode 100644 index 70da2ab..0000000 --- a/src/superio/ite/it8671f/superio.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <pc80/keyboard.h> -#include <stdlib.h> -#include <superio/conf_mode.h> -#include "it8671f.h" - -static void init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case IT8671F_FDC: /* TODO. */ - break; - case IT8671F_PP: /* TODO. */ - break; - case IT8671F_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - case IT8671F_KBCM: /* TODO. */ - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, - .ops_pnp_mode = &pnp_conf_mode_870155_aa, -}; - -/* TODO: FDC, PP, KBCM. */ -static struct pnp_info pnp_dev_info[] = { - { NULL, IT8671F_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, IT8671F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, - 0x07f8, }, - { NULL, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_ite_it8671f_ops = { - CHIP_NAME("ITE IT8671F Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/ite/it8716f/Kconfig b/src/superio/ite/it8716f/Kconfig deleted file mode 100644 index 969e788..0000000 --- a/src/superio/ite/it8716f/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_ITE_IT8716F - bool - select SUPERIO_ITE_COMMON_PRE_RAM - -config SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL - bool - depends on SUPERIO_ITE_IT8716F - default n - select SUPERIO_ITE_COMMON_PRE_RAM diff --git a/src/superio/ite/it8716f/Makefile.inc b/src/superio/ite/it8716f/Makefile.inc deleted file mode 100644 index 6125068..0000000 --- a/src/superio/ite/it8716f/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h deleted file mode 100644 index 726c4cc..0000000 --- a/src/superio/ite/it8716f/it8716f.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_ITE_IT8716F_H -#define SUPERIO_ITE_IT8716F_H - -#include <stdint.h> - -/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */ - -/* Logical device numbers (LDNs). */ -#define IT8716F_FDC 0x00 /* Floppy */ -#define IT8716F_SP1 0x01 /* Com1 */ -#define IT8716F_SP2 0x02 /* Com2 */ -#define IT8716F_PP 0x03 /* Parallel port */ -#define IT8716F_EC 0x04 /* Environment controller */ -#define IT8716F_KBCK 0x05 /* PS/2 keyboard */ -#define IT8716F_KBCM 0x06 /* PS/2 mouse */ -#define IT8716F_GPIO 0x07 /* GPIO */ -#define IT8716F_MIDI 0x08 /* MIDI port */ -#define IT8716F_GAME 0x09 /* GAME port */ -#define IT8716F_IR 0x0a /* Consumer IR */ - -/* Provided by mainboard, called by IT8716F superio.c. */ -void init_ec(u16 base); - -#endif /* SUPERIO_ITE_IT8716F_H */ diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c deleted file mode 100644 index de1ef0d..0000000 --- a/src/superio/ite/it8716f/superio.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * Copyright (C) 2007 AMD - * (Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD) - * Copyright (C) 2007 Ward Vandewege <ward(a)gnu.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <console/console.h> -#include <pc80/keyboard.h> -#include <stdlib.h> -#include <superio/conf_mode.h> - -#include "it8716f.h" - -#if !CONFIG(SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) - -void init_ec(u16 base) -{ - u8 value; - - /* Read out current value of FAN_CTL (0x14). */ - value = pnp_read_index(base, 0x14); - printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n", - base + 0x14, value); - - /* Set FAN_CTL (0x14) polarity to high, activate fans 1, 2 and 3. */ - pnp_write_index(base, 0x14, value | 0x87); - printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n", - base + 0x14, value | 0x87); -} -#endif - -static void it8716f_init(struct device *dev) -{ - struct resource *res0; - - if (!dev->enabled) - return; - - /* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */ - switch (dev->path.pnp.device) { - case IT8716F_EC: - res0 = find_resource(dev, PNP_IDX_IO0); -#define EC_INDEX_PORT 5 - init_ec(res0->base + EC_INDEX_PORT); - break; - case IT8716F_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = it8716f_init, - .ops_pnp_mode = &pnp_conf_mode_870155_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, }, - { NULL, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, - { NULL, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, - { NULL, IT8716F_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0, - 0x0ff8, 0x0ffc, }, - { NULL, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ff8, }, - { NULL, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, }, - { NULL, IT8716F_KBCM, PNP_IRQ0, }, - { NULL, IT8716F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2, - 0x0ff8, 0x0ff8, 0x0ff8, }, - { NULL, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, - { NULL, IT8716F_GAME, PNP_IO0, 0x0ff8, }, - { NULL, IT8716F_IR, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_ite_it8716f_ops = { - CHIP_NAME("ITE IT8716F Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/ite/it8786e/Kconfig b/src/superio/ite/it8786e/Kconfig deleted file mode 100644 index 9d3f258..0000000 --- a/src/superio/ite/it8786e/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2016 secunet Security Networks AG -## Copyright (C) 2018 Libretrend LDA -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_ITE_IT8786E - bool - select SUPERIO_ITE_COMMON_PRE_RAM - select SUPERIO_ITE_ENV_CTRL - select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 - select SUPERIO_ITE_ENV_CTRL_8BIT_PWM - select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG diff --git a/src/superio/ite/it8786e/Makefile.inc b/src/superio/ite/it8786e/Makefile.inc deleted file mode 100644 index 560957f..0000000 --- a/src/superio/ite/it8786e/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2016 secunet Security Networks AG -## Copyright (C) 2018 Libretrend LDA -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_ITE_IT8786E) += superio.c diff --git a/src/superio/ite/it8786e/acpi/superio.asl b/src/superio/ite/it8786e/acpi/superio.asl deleted file mode 100644 index f860da6..0000000 --- a/src/superio/ite/it8786e/acpi/superio.asl +++ /dev/null @@ -1,171 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> - * Copyright (C) 2013, 2016 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Include this file into a mainboard's DSDT _SB device tree and it will - * expose the IT8786E SuperIO and some of its functionality. - * - * It allows the change of IO ports, IRQs and DMA settings on logical - * devices, disabling and reenabling logical devices. - * - * LDN State - * 0x1 UARTA Implemented, untested - * 0x2 UARTB Implemented, untested - * 0x3 PP Not implemented - * 0x4 EC Not implemented - * 0x5 KBC Implemented, untested - * 0x6 MOUSE Implemented, untested - * 0x7 GPIO Not implemented - * 0x8 UARTC Implemented, untested - * 0x9 UARTD Implemented, untested - * 0xa UARTE Not implemented - * 0xb UARTF Not implemented - * 0xc CIR Not implemented - * - * Controllable through preprocessor defines: - * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) - * SUPERIO_PNP_BASE I/O address of the first PnP configuration register - * IT8786E_SHOW_UARTA If defined, UARTA will be exposed. - * IT8786E_SHOW_UARTB If defined, UARTB will be exposed. - * IT8786E_SHOW_UARTC If defined, UARTC will be exposed. - * IT8786E_SHOW_UARTD If defined, UARTD will be exposed. - * IT8786E_SHOW_KBC If defined, the KBC will be exposed. - * IT8786E_SHOW_PS2M If defined, PS/2 mouse support will be exposed. - */ - -#undef SUPERIO_CHIP_NAME -#define SUPERIO_CHIP_NAME IT8786E -#include <superio/acpi/pnp.asl> - -#undef PNP_DEFAULT_PSC -#define PNP_DEFAULT_PSC Return (0) /* no power management */ - -#define CONFIGURE_CONTROL CCTL - -Device (SUPERIO_DEV) { - Name (_HID, EisaId("PNP0A05")) - Name (_STR, Unicode("ITE IT8786E Super I/O")) - Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) - - /* Mutex for accesses to the configuration ports */ - Mutex (CRMX, 1) - - /* SuperIO configuration ports */ - OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) - Field (CREG, ByteAcc, NoLock, Preserve) - { - PNP_ADDR_REG, 8, - PNP_DATA_REG, 8 - } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) - { - Offset (0x02), - CONFIGURE_CONTROL, 8, /* Global configure control */ - - Offset (0x07), - PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ - - Offset (0x30), - PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ - - Offset (0x60), - PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ - PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ - Offset (0x62), - PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ - PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ - - Offset (0x70), - PNP_IRQ0, 8, /* First IRQ */ - } - - Method (_CRS) - { - /* Announce the used i/o ports to the OS */ - Return (ResourceTemplate () { - IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, - 0x01, 0x02) - }) - } - - #undef PNP_ENTER_MAGIC_1ST - #undef PNP_ENTER_MAGIC_2ND - #undef PNP_ENTER_MAGIC_3RD - #undef PNP_ENTER_MAGIC_4TH - #undef PNP_EXIT_MAGIC_1ST - #define PNP_ENTER_MAGIC_1ST 0x87 - #define PNP_ENTER_MAGIC_2ND 0x01 - #define PNP_ENTER_MAGIC_3RD 0x55 -#if SUPERIO_PNP_BASE == 0x2e - #define PNP_ENTER_MAGIC_4TH 0x55 -#else - #define PNP_ENTER_MAGIC_4TH 0xaa -#endif - #define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL - #define PNP_EXIT_SPECIAL_VAL 0x02 - #include <superio/acpi/pnp_config.asl> - -#ifdef IT8786E_SHOW_UARTA - #undef SUPERIO_UART_LDN - #undef SUPERIO_UART_DDN - #undef SUPERIO_UART_PM_REG - #undef SUPERIO_UART_PM_VAL - #undef SUPERIO_UART_PM_LDN - #define SUPERIO_UART_LDN 1 - #include <superio/acpi/pnp_uart.asl> -#endif - -#ifdef IT8786E_SHOW_UARTB - #undef SUPERIO_UART_LDN - #undef SUPERIO_UART_DDN - #undef SUPERIO_UART_PM_REG - #undef SUPERIO_UART_PM_VAL - #undef SUPERIO_UART_PM_LDN - #define SUPERIO_UART_LDN 2 - #include <superio/acpi/pnp_uart.asl> -#endif - -#ifdef IT8786E_SHOW_KBC - #undef SUPERIO_KBC_LDN - #undef SUPERIO_KBC_PS2M - #undef SUPERIO_KBC_PS2LDN - #define SUPERIO_KBC_LDN 5 -#ifdef IT8786E_SHOW_PS2M - #define SUPERIO_KBC_PS2LDN 6 -#endif - #include <superio/acpi/pnp_kbc.asl> -#endif - -#ifdef IT8786E_SHOW_UARTC - #undef SUPERIO_UART_LDN - #undef SUPERIO_UART_DDN - #undef SUPERIO_UART_PM_REG - #undef SUPERIO_UART_PM_VAL - #undef SUPERIO_UART_PM_LDN - #define SUPERIO_UART_LDN 8 - #include <superio/acpi/pnp_uart.asl> -#endif - -#ifdef IT8786E_SHOW_UARTD - #undef SUPERIO_UART_LDN - #undef SUPERIO_UART_DDN - #undef SUPERIO_UART_PM_REG - #undef SUPERIO_UART_PM_VAL - #undef SUPERIO_UART_PM_LDN - #define SUPERIO_UART_LDN 9 - #include <superio/acpi/pnp_uart.asl> -#endif -} diff --git a/src/superio/ite/it8786e/chip.h b/src/superio/ite/it8786e/chip.h deleted file mode 100644 index 4b2e811..0000000 --- a/src/superio/ite/it8786e/chip.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2019 Libretrend LDA - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_ITE_IT8786E_CHIP_H -#define SUPERIO_ITE_IT8786E_CHIP_H - -#include <superio/ite/common/env_ctrl_chip.h> - -struct superio_ite_it8786e_config { - struct ite_ec_config ec; -}; - -#endif /* SUPERIO_ITE_IT8786E_CHIP_H */ diff --git a/src/superio/ite/it8786e/it8786e.h b/src/superio/ite/it8786e/it8786e.h deleted file mode 100644 index 5f11b63..0000000 --- a/src/superio/ite/it8786e/it8786e.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2019 Libretrend LDA - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_ITE_IT8786E_H -#define SUPERIO_ITE_IT8786E_H - -#define IT8786E_SP1 0x01 /* COM1 */ -#define IT8786E_SP2 0x02 /* COM2 */ -#define IT8786E_PP 0x03 /* Printer port */ -#define IT8786E_EC 0x04 /* Environment controller */ -#define IT8786E_KBCK 0x05 /* Keyboard */ -#define IT8786E_KBCM 0x06 /* Mouse */ -#define IT8786E_GPIO 0x07 /* GPIO */ -#define IT8786E_SP3 0x08 /* COM3 */ -#define IT8786E_SP4 0x09 /* COM4 */ -#define IT8786E_CIR 0x0a /* Consumer IR */ -#define IT8786E_SP5 0x0b /* COM5 */ -#define IT8786E_SP6 0x0c /* COM6 */ - -#include <stdint.h> - -#endif /* SUPERIO_ITE_IT8786E_H */ diff --git a/src/superio/ite/it8786e/superio.c b/src/superio/ite/it8786e/superio.c deleted file mode 100644 index ac9dc4b..0000000 --- a/src/superio/ite/it8786e/superio.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2019 Libretrend LDA - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <pc80/keyboard.h> -#include <superio/conf_mode.h> -#include <superio/ite/common/env_ctrl.h> - -#include "it8786e.h" -#include "chip.h" - -static void it8786e_init(struct device *const dev) -{ - const struct superio_ite_it8786e_config *conf; - const struct resource *res; - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case IT8786E_EC: - conf = dev->chip_info; - res = find_resource(dev, PNP_IDX_IO0); - if (!conf || !res) - break; - ite_ec_init(res->base, &conf->ec); - break; - case IT8786E_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - default: - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = it8786e_init, - .ops_pnp_mode = &pnp_conf_mode_870155_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - /* Serial Port 1 */ - { NULL, IT8786E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | - PNP_MSC2, - 0x0ff8, }, - /* Serial Port 2 */ - { NULL, IT8786E_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | - PNP_MSC2, - 0x0ff8, }, - /* Printer Port */ - { NULL, IT8786E_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 | - PNP_MSC0, - 0x0ff8, 0x0ffc, }, - /* Environmental Controller */ - { NULL, IT8786E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | - PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | PNP_MSC4 | - PNP_MSC5 | PNP_MSC6 | PNP_MSCA | PNP_MSCB | - PNP_MSCC, - 0x0ff8, 0x0ffc, }, - /* KBC Keyboard */ - { NULL, IT8786E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, - 0x0fff, 0x0fff, }, - /* KBC Mouse */ - { NULL, IT8786E_KBCM, PNP_IRQ0 | PNP_MSC0, }, - /* GPIO */ - { NULL, IT8786E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | - PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | - PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 | - PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB, - 0x0ffc, 0x0fff, }, - /* Serial Port 3 */ - { NULL, IT8786E_SP3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | - PNP_MSC2, - 0x0ff8, }, - /* Serial Port 4 */ - { NULL, IT8786E_SP4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | - PNP_MSC2, - 0x0ff8, }, - /* Consumer Infrared */ - { NULL, IT8786E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, - /* Serial Port 5 */ - { NULL, IT8786E_SP5, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | - PNP_MSC2, - 0x0ff8, }, - /* Serial Port 6 */ - { NULL, IT8786E_SP6, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | - PNP_MSC2, - 0x0ff8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_ite_it8786e_ops = { - CHIP_NAME("ITE IT8786E Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/nsc/pc87309/Kconfig b/src/superio/nsc/pc87309/Kconfig deleted file mode 100644 index ff72706..0000000 --- a/src/superio/nsc/pc87309/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_NSC_PC87309 - bool - select SUPERIO_NSC_COMMON_PRE_RAM diff --git a/src/superio/nsc/pc87309/Makefile.inc b/src/superio/nsc/pc87309/Makefile.inc deleted file mode 100644 index 6c7a8ab..0000000 --- a/src/superio/nsc/pc87309/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_NSC_PC87309) += superio.c diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h deleted file mode 100644 index 3b912ea..0000000 --- a/src/superio/nsc/pc87309/pc87309.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87309_H -#define SUPERIO_NSC_PC87309_H - -/* Datasheet: PC87309 SuperI/O Plug and Play Compatible Chip. */ - -#define PC87309_FDC 0x00 /* Floppy */ -#define PC87309_PP 0x01 /* Parallel port */ -#define PC87309_SP2 0x02 /* Com2 / IR */ -#define PC87309_SP1 0x03 /* Com1 */ -#define PC87309_PM 0x04 /* Power management */ -#define PC87309_KBCM 0x05 /* Mouse */ -#define PC87309_KBCK 0x06 /* Keyboard */ - -#endif /* SUPERIO_NSC_PC87309_H */ diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c deleted file mode 100644 index 4f8f967..0000000 --- a/src/superio/nsc/pc87309/superio.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <pc80/keyboard.h> -#include <stdlib.h> -#include "pc87309.h" - -static void init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case PC87309_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, - 0x07f8, }, - { NULL, PC87309_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - /* TODO: PM. */ - { NULL, PC87309_KBCM, PNP_IRQ0, }, - { NULL, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_nsc_pc87309_ops = { - CHIP_NAME("NSC PC87309 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/nsc/pc87360/Kconfig b/src/superio/nsc/pc87360/Kconfig deleted file mode 100644 index b70b935..0000000 --- a/src/superio/nsc/pc87360/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_NSC_PC87360 - bool - select SUPERIO_NSC_COMMON_PRE_RAM diff --git a/src/superio/nsc/pc87360/Makefile.inc b/src/superio/nsc/pc87360/Makefile.inc deleted file mode 100644 index 81e2d3d..0000000 --- a/src/superio/nsc/pc87360/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_NSC_PC87360) += superio.c diff --git a/src/superio/nsc/pc87360/pc87360.h b/src/superio/nsc/pc87360/pc87360.h deleted file mode 100644 index c969746..0000000 --- a/src/superio/nsc/pc87360/pc87360.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87360_H -#define SUPERIO_NSC_PC87360_H - -#define PC87360_FDC 0x00 /* Floppy */ -#define PC87360_PP 0x01 /* Parallel port */ -#define PC87360_SP2 0x02 /* Com2 */ -#define PC87360_SP1 0x03 /* Com1 */ -#define PC87360_SWC 0x04 -#define PC87360_KBCM 0x05 /* Mouse */ -#define PC87360_KBCK 0x06 /* Keyboard */ -#define PC87360_GPIO 0x07 -#define PC87360_ACB 0x08 -#define PC87360_FSCM 0x09 -#define PC87360_WDT 0x0A - -#endif /* SUPERIO_NSC_PC87360_H */ diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c deleted file mode 100644 index 33f27e1..0000000 --- a/src/superio/nsc/pc87360/superio.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <pc80/keyboard.h> -#include <stdlib.h> -#include "pc87360.h" - -static void init(struct device *dev) -{ - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case PC87360_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, - 0x07f8, }, - { NULL, PC87360_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87360_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87360_KBCM, PNP_IRQ0, }, - { NULL, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_nsc_pc87360_ops = { - CHIP_NAME("NSC PC87360 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/nsc/pc87366/Kconfig b/src/superio/nsc/pc87366/Kconfig deleted file mode 100644 index bf17117..0000000 --- a/src/superio/nsc/pc87366/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_NSC_PC87366 - bool - select SUPERIO_NSC_COMMON_PRE_RAM diff --git a/src/superio/nsc/pc87366/Makefile.inc b/src/superio/nsc/pc87366/Makefile.inc deleted file mode 100644 index f432530..0000000 --- a/src/superio/nsc/pc87366/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_NSC_PC87366) += superio.c diff --git a/src/superio/nsc/pc87366/pc87366.h b/src/superio/nsc/pc87366/pc87366.h deleted file mode 100644 index b1df69f..0000000 --- a/src/superio/nsc/pc87366/pc87366.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87366_H -#define SUPERIO_NSC_PC87366_H - -#define PC87366_FDC 0x00 /* Floppy */ -#define PC87366_PP 0x01 /* Parallel port */ -#define PC87366_SP2 0x02 /* Com2 */ -#define PC87366_SP1 0x03 /* Com1 */ -#define PC87366_SWC 0x04 -#define PC87366_KBCM 0x05 /* Mouse */ -#define PC87366_KBCK 0x06 /* Keyboard */ -#define PC87366_GPIO 0x07 -#define PC87366_ACB 0x08 -#define PC87366_FSCM 0x09 -#define PC87366_WDT 0x0A -#define PC87366_GMP 0x0b -#define PC87366_MIDI 0x0C -#define PC87366_VLM 0x0D -#define PC87366_TMS 0x0E - -#endif /* SUPERIO_NSC_PC87366_H */ diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c deleted file mode 100644 index 6d8c66e..0000000 --- a/src/superio/nsc/pc87366/superio.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <pc80/keyboard.h> -#include <stdlib.h> -#include "pc87366.h" - -static void init(struct device *dev) -{ - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case PC87366_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, - 0x07f8, }, - { NULL, PC87366_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87366_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87366_KBCM, PNP_IRQ0, }, - { NULL, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_nsc_pc87366_ops = { - CHIP_NAME("NSC PC87366 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/nsc/pc97317/Kconfig b/src/superio/nsc/pc97317/Kconfig deleted file mode 100644 index 38f6d34..0000000 --- a/src/superio/nsc/pc97317/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_NSC_PC97317 - bool diff --git a/src/superio/nsc/pc97317/Makefile.inc b/src/superio/nsc/pc97317/Makefile.inc deleted file mode 100644 index 2f8ee76..0000000 --- a/src/superio/nsc/pc97317/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_NSC_PC97317) += early_serial.c -romstage-$(CONFIG_SUPERIO_NSC_PC97317) += early_serial.c -ramstage-$(CONFIG_SUPERIO_NSC_PC97317) += superio.c diff --git a/src/superio/nsc/pc97317/early_serial.c b/src/superio/nsc/pc97317/early_serial.c deleted file mode 100644 index 74489fa..0000000 --- a/src/superio/nsc/pc97317/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pnp_ops.h> -#include <device/pnp.h> -#include <stdint.h> -#include "pc97317.h" - -#define PM_DEV PNP_DEV(0x2e, PC97317_PM) -#define PM_BASE 0xe8 - -/* The PC97317 needs clocks to be set up before the serial port will operate. */ -void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - /* Set base address of power management unit. */ - pnp_set_logical_device(PM_DEV); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE); - pnp_set_enable(dev, 1); - - /* Use on-chip clock multiplier. */ - outb(0x03, PM_BASE); - outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1); - - /* Wait for the clock to stabilise. */ - while(!(inb(PM_BASE + 1) & 0x80)) - ; - - /* Set the base address of the port. */ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/nsc/pc97317/pc97317.h b/src/superio/nsc/pc97317/pc97317.h deleted file mode 100644 index 76717fa..0000000 --- a/src/superio/nsc/pc97317/pc97317.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC97317_H -#define SUPERIO_NSC_PC97317_H - -#define PC97317_KBCK 0x00 /* Keyboard */ -#define PC97317_KBCM 0x01 /* Mouse */ -#define PC97317_RTC 0x02 /* Real-Time Clock */ -#define PC97317_FDC 0x03 /* Floppy */ -#define PC97317_PP 0x04 /* Parallel port */ -#define PC97317_SP2 0x05 /* Com2 */ -#define PC97317_SP1 0x06 /* Com1 */ -#define PC97317_GPIO 0x07 -#define PC97317_PM 0x08 /* Power Management */ - -#include <device/pnp_type.h> -#include <stdint.h> - -void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif /* SUPERIO_NSC_PC97317_H */ diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c deleted file mode 100644 index 42f5434..0000000 --- a/src/superio/nsc/pc97317/superio.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <stdlib.h> -#include <pc80/keyboard.h> -#include "pc97317.h" - -static void init(struct device *dev) -{ - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case PC97317_KBCK: - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); /* Disable keyboard */ - pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */ - pnp_set_enable(dev, 1); /* Enable keyboard */ - pc_keyboard_init(NO_AUX_DEVICE); - break; - default: - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, }, - { NULL, PC97317_KBCM, PNP_IRQ0, }, - { NULL, PC97317_RTC, PNP_IO0 | PNP_IRQ0, 0xfffe, }, - { NULL, PC97317_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0xfff8, }, - { NULL, PC97317_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x03fc, }, - { NULL, PC97317_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, - 0xfff8, }, - { NULL, PC97317_SP1, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC97317_GPIO, PNP_IO0, 0xfff8, }, - { NULL, PC97317_PM, PNP_IO0, 0xfffe, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_nsc_pc97317_ops = { - CHIP_NAME("NSC PC97317 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index 29418db..eaa3c5a 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -65,10 +65,6 @@ { nuvoton_pnp_enter_conf_state(dev); - if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A)) - /* Route COM A to GPIO8 pin group */ - pnp_write_config(dev, 0x2a, 0x40); - if (CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) /* Route COM A to GPIO8 pin group */ pnp_write_config(dev, 0x2a, 0x40); diff --git a/src/superio/nuvoton/nct5539d/Kconfig b/src/superio/nuvoton/nct5539d/Kconfig deleted file mode 100644 index 0dd1402..0000000 --- a/src/superio/nuvoton/nct5539d/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_NUVOTON_NCT5539D - bool - select SUPERIO_NUVOTON_COMMON_PRE_RAM - -config SUPERIO_NUVOTON_NCT5539D_COM_A - bool - depends on SUPERIO_NUVOTON_NCT5539D - default n diff --git a/src/superio/nuvoton/nct5539d/Makefile.inc b/src/superio/nuvoton/nct5539d/Makefile.inc deleted file mode 100644 index 6e3fdf2..0000000 --- a/src/superio/nuvoton/nct5539d/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += superio.c diff --git a/src/superio/nuvoton/nct5539d/nct5539d.h b/src/superio/nuvoton/nct5539d/nct5539d.h deleted file mode 100644 index d4e8d08..0000000 --- a/src/superio/nuvoton/nct5539d/nct5539d.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NUVOTON_NCT5539D_H -#define SUPERIO_NUVOTON_NCT5539D_H - -/* Logical Device Numbers (LDN). */ -#define NCT5539D_SP1 0x02 /* UART A */ -#define NCT5539D_KBC 0x05 /* Keyboard Controller */ -#define NCT5539D_CIR 0x06 /* Consumer IR */ -#define NCT5539D_GPIO78 0x07 /* GPIO 7 & 8 */ -#define NCT5539D_WDT1_WDT3_GPIO0 0x08 /* WDT1, WDT3, GPIO 0 & KBC P20 */ -#define NCT5539D_GPIO2345 0x09 /* GPIO 2, 3, 4 & 5 */ -#define NCT5539D_ACPI 0x0A /* ACPI */ -#define NCT5539D_HWM_FPLED 0x0B /* HW Monitor, Front Panel LED */ -#define NCT5539D_WDT2 0x0D /* WDT2 */ -#define NCT5539D_CIRWUP 0x0E /* CIR Wake-Up */ -#define NCT5539D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open-Drain */ -#define NCT5539D_GPIO_PSO 0x11 /* GPIO, RI PSOUT Wake-Up Status */ -#define NCT5539D_SWEC 0x12 /* SW Error Control */ -#define NCT5539D_FLED 0x15 /* Fading LED */ -#define NCT5539D_DS 0x16 /* Deep Sleep */ - -/* Virtual LDNs */ -#define NCT5539D_WDT1 ((0 << 8) | NCT5539D_WDT1_WDT3_GPIO0) -#define NCT5539D_WDT3 ((4 << 8) | NCT5539D_WDT1_WDT3_GPIO0) -#define NCT5539D_GPIOBASE ((3 << 8) | NCT5539D_WDT1_WDT3_GPIO0) -#define NCT5539D_GPIO0 ((1 << 8) | NCT5539D_WDT1_WDT3_GPIO0) -#define NCT5539D_GPIO2 ((0 << 8) | NCT5539D_GPIO2345) -#define NCT5539D_GPIO3 ((1 << 8) | NCT5539D_GPIO2345) -#define NCT5539D_GPIO4 ((2 << 8) | NCT5539D_GPIO2345) -#define NCT5539D_GPIO5 ((3 << 8) | NCT5539D_GPIO2345) -#define NCT5539D_GPIO7 ((1 << 8) | NCT5539D_GPIO78) -#define NCT5539D_GPIO8 ((2 << 8) | NCT5539D_GPIO78) -#define NCT5539D_DS5 ((0 << 8) | NCT5539D_DS) -#define NCT5539D_DS3 ((1 << 8) | NCT5539D_DS) - -#endif /* SUPERIO_NUVOTON_NCT5539D_H */ diff --git a/src/superio/nuvoton/nct5539d/superio.c b/src/superio/nuvoton/nct5539d/superio.c deleted file mode 100644 index e38f845..0000000 --- a/src/superio/nuvoton/nct5539d/superio.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * Copyright (C) 2015 Matt DeVillier <matt.devillier(a)gmail.com> - * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> -* Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <pc80/keyboard.h> -#include <stdlib.h> -#include <superio/conf_mode.h> - -#include "nct5539d.h" - - -static void nct5539d_init(struct device *dev) -{ - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case NCT5539D_KBC: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = nct5539d_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, NCT5539D_SP1, PNP_IO0 | PNP_IRQ0, - 0x0ff8, }, - { NULL, NCT5539D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, - 0x0fff, 0x0fff, }, - { NULL, NCT5539D_CIR, PNP_IO0 | PNP_IRQ0, - 0x0ff8, }, - { NULL, NCT5539D_ACPI}, - { NULL, NCT5539D_HWM_FPLED, PNP_IO0 | PNP_IRQ0, - 0x0ffe, 0x0ffe, }, - { NULL, NCT5539D_WDT2}, - { NULL, NCT5539D_CIRWUP, PNP_IO0 | PNP_IRQ0, - 0x0ff8, }, - { NULL, NCT5539D_GPIO_PP_OD}, - { NULL, NCT5539D_WDT1}, - { NULL, NCT5539D_WDT3}, - { NULL, NCT5539D_GPIOBASE, PNP_IO0, - 0x0ff8, }, - { NULL, NCT5539D_GPIO0}, - { NULL, NCT5539D_GPIO2}, - { NULL, NCT5539D_GPIO3}, - { NULL, NCT5539D_GPIO4}, - { NULL, NCT5539D_GPIO5}, - { NULL, NCT5539D_GPIO7}, - { NULL, NCT5539D_GPIO8}, - { NULL, NCT5539D_GPIO_PSO}, - { NULL, NCT5539D_SWEC}, - { NULL, NCT5539D_FLED}, - { NULL, NCT5539D_DS5}, - { NULL, NCT5539D_DS3}, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_nuvoton_nct5539d_ops = { - CHIP_NAME("NUVOTON NCT5539D Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/smsc/dme1737/Kconfig b/src/superio/smsc/dme1737/Kconfig deleted file mode 100644 index 20cb12c..0000000 --- a/src/superio/smsc/dme1737/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_SMSC_DME1737 - bool diff --git a/src/superio/smsc/dme1737/Makefile.inc b/src/superio/smsc/dme1737/Makefile.inc deleted file mode 100644 index e106a02..0000000 --- a/src/superio/smsc/dme1737/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## Copyright (C) 2004 Tyan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_SMSC_DME1737) += early_serial.c -romstage-$(CONFIG_SUPERIO_SMSC_DME1737) += early_serial.c -ramstage-$(CONFIG_SUPERIO_SMSC_DME1737) += superio.c diff --git a/src/superio/smsc/dme1737/dme1737.h b/src/superio/smsc/dme1737/dme1737.h deleted file mode 100644 index f40cc35..0000000 --- a/src/superio/smsc/dme1737/dme1737.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_SMSC_DME1737_H -#define SUPERIO_SMSC_DME1737_H - -#define DME1737_FDC 0 /* Floppy */ -#define DME1737_PP 3 /* Parallel Port */ -#define DME1737_SP1 4 /* Com1 */ -#define DME1737_SP2 5 /* Com2 */ -#define DME1737_KBC 7 /* Keyboard & Mouse */ -#define DME1737_RT 10 /* Runtime reg*/ - -#include <device/pnp_type.h> -#include <stdint.h> - -void dme1737_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif /* SUPERIO_SMSC_DME1737_H */ diff --git a/src/superio/smsc/dme1737/early_serial.c b/src/superio/smsc/dme1737/early_serial.c deleted file mode 100644 index 58ad177..0000000 --- a/src/superio/smsc/dme1737/early_serial.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pnp_ops.h> -#include <device/pnp.h> -#include <stdint.h> -#include "dme1737.h" - -static void pnp_enter_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void dme1737_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/dme1737/superio.c b/src/superio/smsc/dme1737/superio.c deleted file mode 100644 index 0bfd3b8..0000000 --- a/src/superio/smsc/dme1737/superio.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <superio/conf_mode.h> -#include <device/smbus.h> -#include <pc80/keyboard.h> -#include <stdlib.h> -#include "dme1737.h" - -static void dme1737_init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case DME1737_KBC: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = dme1737_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, DME1737_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, DME1737_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, DME1737_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, DME1737_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, DME1737_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, - 0x07ff, 0x07ff, }, - { NULL, DME1737_RT, PNP_IO0, 0x0780, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_smsc_dme1737_ops = { - CHIP_NAME("SMSC DME1737 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/smsc/lpc47b272/Kconfig b/src/superio/smsc/lpc47b272/Kconfig deleted file mode 100644 index 07e6472..0000000 --- a/src/superio/smsc/lpc47b272/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_SMSC_LPC47B272 - bool diff --git a/src/superio/smsc/lpc47b272/Makefile.inc b/src/superio/smsc/lpc47b272/Makefile.inc deleted file mode 100644 index 51d77d4..0000000 --- a/src/superio/smsc/lpc47b272/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2005 Digital Design Corporation -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_SMSC_LPC47B272) += early_serial.c -romstage-$(CONFIG_SUPERIO_SMSC_LPC47B272) += early_serial.c -ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B272) += superio.c diff --git a/src/superio/smsc/lpc47b272/early_serial.c b/src/superio/smsc/lpc47b272/early_serial.c deleted file mode 100644 index 26fdfaf..0000000 --- a/src/superio/smsc/lpc47b272/early_serial.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp_ops.h> -#include <device/pnp.h> -#include <stdint.h> -#include "lpc47b272.h" - -static void pnp_enter_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/** - * Configure the base I/O port of the specified serial device and enable the - * serial device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Processor I/O port address to assign to this serial device. - */ -void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47b272/lpc47b272.h b/src/superio/smsc/lpc47b272/lpc47b272.h deleted file mode 100644 index 3fbd043..0000000 --- a/src/superio/smsc/lpc47b272/lpc47b272.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_SMSC_LPC47B272_H -#define SUPERIO_SMSC_LPC47B272_H - -#define LPC47B272_FDC 0 /* Floppy */ -#define LPC47B272_PP 3 /* Parallel Port */ -#define LPC47B272_SP1 4 /* Com1 */ -#define LPC47B272_SP2 5 /* Com2 */ -#define LPC47B272_KBC 7 /* Keyboard & Mouse */ -#define LPC47B272_RT 10 /* Runtime reg*/ - -#define LPC47B272_MAX_CONFIG_REGISTER 0x5F - -#include <device/pnp_type.h> -#include <stdint.h> - -void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif /* SUPERIO_SMSC_LPC47B272_H */ diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c deleted file mode 100644 index 6ac2d6d..0000000 --- a/src/superio/smsc/lpc47b272/superio.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* RAM driver for SMSC LPC47B272 Super I/O chip. */ - -#include <device/device.h> -#include <device/pnp.h> -#include <superio/conf_mode.h> -#include <device/smbus.h> -#include <pc80/keyboard.h> -#include <stdlib.h> -#include "lpc47b272.h" - -/** - * Initialize the specified Super I/O device. - * - * Devices other than COM ports and the keyboard controller are ignored. - * For COM ports, we configure the baud rate. - * - * @param dev Pointer to structure describing a Super I/O device. - */ -static void lpc47b272_init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case LPC47B272_KBC: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = lpc47b272_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, - 0x07ff, 0x07ff, }, - { NULL, LPC47B272_RT, PNP_IO0, 0x0780, }, -}; - -/** - * Create device structures and allocate resources to devices specified in the - * pnp_dev_info array (above). - * - * @param dev Pointer to structure describing a Super I/O device. - */ -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_smsc_lpc47b272_ops = { - CHIP_NAME("SMSC LPC47B272 Super I/O") - .enable_dev = enable_dev -}; diff --git a/src/superio/smsc/lpc47b397/Kconfig b/src/superio/smsc/lpc47b397/Kconfig deleted file mode 100644 index 80264c4..0000000 --- a/src/superio/smsc/lpc47b397/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_SMSC_LPC47B397 - bool diff --git a/src/superio/smsc/lpc47b397/Makefile.inc b/src/superio/smsc/lpc47b397/Makefile.inc deleted file mode 100644 index ddb251d..0000000 --- a/src/superio/smsc/lpc47b397/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## Copyright (C) 2004 Tyan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_SMSC_LPC47B397) += early_serial.c -romstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += early_serial.c -ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.c diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c deleted file mode 100644 index a07cd99..0000000 --- a/src/superio/smsc/lpc47b397/early_serial.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pnp_ops.h> -#include <device/pnp.h> -#include <stdint.h> -#include "lpc47b397.h" - -static void pnp_enter_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47b397/lpc47b397.h b/src/superio/smsc/lpc47b397/lpc47b397.h deleted file mode 100644 index 5f3a504..0000000 --- a/src/superio/smsc/lpc47b397/lpc47b397.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_SMSC_LPC47B397_H -#define SUPERIO_SMSC_LPC47B397_H - -#define LPC47B397_FDC 0 /* Floppy */ -#define LPC47B397_PP 3 /* Parallel Port */ -#define LPC47B397_SP1 4 /* Com1 */ -#define LPC47B397_SP2 5 /* Com2 */ -#define LPC47B397_KBC 7 /* Keyboard & Mouse */ -#define LPC47B397_HWM 8 /* HW Monitor */ -#define LPC47B397_RT 10 /* Runtime reg*/ - -#include <device/pnp_type.h> -#include <stdint.h> - -void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif /* SUPERIO_SMSC_LPC47B397_H */ diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c deleted file mode 100644 index 4b9e345..0000000 --- a/src/superio/smsc/lpc47b397/superio.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <superio/conf_mode.h> -#include <console/console.h> -#include <device/smbus.h> -#include <pc80/keyboard.h> -#include <stdlib.h> -#include "lpc47b397.h" - -static void enable_hwm_smbus(struct device *dev) -{ - /* Enable SensorBus register access. */ - u8 reg8; - - reg8 = pnp_read_config(dev, 0xf0); - reg8 |= (1 << 1); - pnp_write_config(dev, 0xf0, reg8); -} - -static void lpc47b397_init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case LPC47B397_KBC: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static void lpc47b397_pnp_enable_resources(struct device *dev) -{ - pnp_enable_resources(dev); - - pnp_enter_conf_mode(dev); - switch (dev->path.pnp.device) { - case LPC47B397_HWM: - printk(BIOS_DEBUG, "LPC47B397 SensorBus register access enabled\n"); - pnp_set_logical_device(dev); - enable_hwm_smbus(dev); - break; - } - /* dump_pnp_device(dev); */ - pnp_exit_conf_mode(dev); -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = lpc47b397_pnp_enable_resources, - .enable = pnp_alt_enable, - .init = lpc47b397_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, -}; - -#define HWM_INDEX 0 -#define HWM_DATA 1 -#define SB_INDEX 0x0b -#define SB_DATA0 0x0c -#define SB_DATA1 0x0d -#define SB_DATA2 0x0e -#define SB_DATA3 0x0f - -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - unsigned int device; - struct resource *res; - int result; - - device = dev->path.i2c.device; - - res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); - - pnp_write_index(res->base + HWM_INDEX, 0, device); /* Why 0? */ - - /* We only read it one byte one time. */ - result = pnp_read_index(res->base + SB_INDEX, address); - - return result; -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) -{ - unsigned int device; - struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); - - pnp_write_index(res->base+HWM_INDEX, 0, device); /* Why 0? */ - - /* We only write it one byte one time. */ - pnp_write_index(res->base+SB_INDEX, address, val); - - return 0; -} - -static struct smbus_bus_operations lops_smbus_bus = { - /* .recv_byte = lsmbus_recv_byte, */ - /* .send_byte = lsmbus_send_byte, */ - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static struct device_operations ops_hwm = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = lpc47b397_pnp_enable_resources, - .enable = pnp_alt_enable, - .init = lpc47b397_init, - .ops_smbus_bus = &lops_smbus_bus, - .ops_pnp_mode = &pnp_conf_mode_55_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, - 0x07ff, 0x07ff, }, - { &ops_hwm, LPC47B397_HWM, PNP_IO0, 0x07f0, }, - { NULL, LPC47B397_RT, PNP_IO0, 0x0780, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_smsc_lpc47b397_ops = { - CHIP_NAME("SMSC LPC47B397 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/smsc/sch4037/Kconfig b/src/superio/smsc/sch4037/Kconfig deleted file mode 100644 index ce87f75..0000000 --- a/src/superio/smsc/sch4037/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_SMSC_SCH4037 - bool diff --git a/src/superio/smsc/sch4037/Makefile.inc b/src/superio/smsc/sch4037/Makefile.inc deleted file mode 100644 index ac7d7de..0000000 --- a/src/superio/smsc/sch4037/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -bootblock-$(CONFIG_SUPERIO_SMSC_SCH4037) += sch4037_early_init.c -romstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += sch4037_early_init.c -ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c diff --git a/src/superio/smsc/sch4037/sch4037.h b/src/superio/smsc/sch4037/sch4037.h deleted file mode 100644 index f0fa3cd..0000000 --- a/src/superio/smsc/sch4037/sch4037.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_SCH_4037_H -#define SUPERIO_SCH_4037_H - -#define SCH4037_FDD 0 /* FDD */ -#define SCH4037_LPT 3 /* LPT */ -#define SMSCSUPERIO_SP1 4 /* Com1 */ -#define SMSCSUPERIO_SP2 5 /* Com2 */ -#define SCH4037_RTC 6 /* RTC */ -#define SCH4037_KBC 7 /* KBC */ -#define SCH4037_HWM 8 /* HWM */ -#define SCH4037_RUNTIME 0x0A /* Runtime */ -#define SCH4037_XBUS 0x0B /* X-BUS */ - -void sch4037_early_init(unsigned port); - -#endif /* SUPERIO_SCH_4037_H */ diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c deleted file mode 100644 index a416ab8..0000000 --- a/src/superio/smsc/sch4037/sch4037_early_init.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <arch/io.h> -#include <device/pnp_ops.h> -#include <device/pnp.h> -#include <stdint.h> - -#include "sch4037.h" - -static void pnp_enter_conf_state(pnp_devfn_t dev) -{ - unsigned port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(pnp_devfn_t dev) -{ - unsigned port = dev >> 8; - outb(0xaa, port); -} - -void sch4037_early_init(unsigned port) -{ - pnp_devfn_t dev; - - dev = PNP_DEV(port, SMSCSUPERIO_SP1); - pnp_enter_conf_state(dev); - - /* Auto power management */ - pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ - pnp_write_config(dev, 0x23, 0); - - /* Enable SMSC UART 0 */ - dev = PNP_DEV(port, SMSCSUPERIO_SP1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); - pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); - - /* Enabled High speed, disabled MIDI support. */ - pnp_write_config(dev, 0xF0, 0x02); - pnp_set_enable(dev, 1); - - /* Enable keyboard */ - dev = PNP_DEV(port, SCH4037_KBC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ - pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ - pnp_set_enable(dev, 1); - - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c deleted file mode 100644 index 5e49aa7..0000000 --- a/src/superio/smsc/sch4037/superio.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* RAM driver for the SMSC KBC1100 Super I/O chip */ - -#include <device/device.h> -#include <device/pnp.h> -#include <superio/conf_mode.h> -#include <pc80/keyboard.h> -#include <stdlib.h> - -#include "sch4037.h" - -static void sch4037_init(struct device *dev) -{ - if (!dev->enabled) { - return; - } - - switch (dev->path.pnp.device) { - case SCH4037_KBC: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = sch4037_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, - 0x7ff, 0x7ff, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_smsc_sch4037_ops = { - CHIP_NAME("SMSC SCH4037 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/smsc/sio1036/Kconfig b/src/superio/smsc/sio1036/Kconfig deleted file mode 100644 index df519de..0000000 --- a/src/superio/smsc/sio1036/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_SMSC_SIO1036 - bool diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc deleted file mode 100644 index e9fdae2..0000000 --- a/src/superio/smsc/sio1036/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -bootblock-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c -romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c -ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h deleted file mode 100644 index 610beba..0000000 --- a/src/superio/smsc/sio1036/sio1036.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_SMSC_SIO1306_H -#define SUPERIO_SMSC_SIO1306_H - -#define SIO1036_SP1 0 /* Com1 */ - -#define UART_POWER_DOWN (1 << 7) -#define LPT_POWER_DOWN (1 << 2) -#define IR_OUTPUT_MUX (1 << 6) - -#include <device/pnp_type.h> -#include <stdint.h> - -void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif /* SUPERIO_SMSC_SIO1306_H */ diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c deleted file mode 100644 index 47f317f..0000000 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ - -#include <arch/io.h> -#include <device/pnp_ops.h> -#include <stdint.h> - -#include "sio1036.h" - -static inline void sio1036_enter_conf_state(pnp_devfn_t dev) -{ - unsigned port = dev >> 8; - outb(0x55, port); -} - -static inline void sio1036_exit_conf_state(pnp_devfn_t dev) -{ - unsigned port = dev >> 8; - outb(0xaa, port); -} - -/* Detect SMSC SIO1036 LPC Debug Card status */ -static u8 detect_sio1036_chip(unsigned port) -{ - pnp_devfn_t dev = PNP_DEV(port, SIO1036_SP1); - unsigned data; - - sio1036_enter_conf_state(dev); - data = pnp_read_config(dev, 0x0D); - sio1036_exit_conf_state(dev); - - /* Detect SMSC SIO1036 chip */ - if (data == 0x82) { - /* Found SMSC SIO1036 chip */ - return 0; - } - else { - return 1; - }; -} - -void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - unsigned port = dev >> 8; - - if (detect_sio1036_chip(port) != 0) - return; - - sio1036_enter_conf_state(dev); - - /* Enable SMSC UART 0 */ - /* Valid configuration cycle */ - pnp_write_config(dev, 0x00, 0x28); - - /* PP power/mode/cr lock */ - pnp_write_config(dev, 0x01, 0x98 | LPT_POWER_DOWN); - pnp_write_config(dev, 0x02, 0x08 | UART_POWER_DOWN); - - /*Auto power management*/ - pnp_write_config(dev, 0x07, 0x00); - - /*ECP FIFO threhod */ - pnp_write_config(dev, 0x0A, 0x00 | IR_OUTPUT_MUX); - - /*GPIO direction register 2 */ - pnp_write_config(dev, 0x033, 0x00); - - /*UART Mode */ - pnp_write_config(dev, 0x0C, 0x02); - - /* GPIO polarity regisgter 2 */ - pnp_write_config(dev, 0x034, 0x00); - - /* Enable SMSC UART 0 */ - /*Set base io address */ - pnp_write_config(dev, 0x25, (u8)(iobase >> 2)); - - /* Set UART IRQ onto 0x04 */ - pnp_write_config(dev, 0x28, 0x04); - - sio1036_exit_conf_state(dev); -} diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c deleted file mode 100644 index a192831..0000000 --- a/src/superio/smsc/sio1036/superio.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* RAM driver for the SMSC SIO1036 Super I/O chip */ - -#include <device/device.h> -#include <device/pnp.h> -#include <superio/conf_mode.h> -#include <stdlib.h> - -#include "sio1036.h" - -static void sio1036_init(struct device *dev) -{ - if (!dev->enabled) { - return; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = sio1036_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, SIO1036_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_smsc_sio1036_ops = { - CHIP_NAME("SMSC SIO1036 Super I/O") - .enable_dev = enable_dev -}; diff --git a/src/superio/via/vt1211/Kconfig b/src/superio/via/vt1211/Kconfig deleted file mode 100644 index b2de1d3..0000000 --- a/src/superio/via/vt1211/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_VIA_VT1211 - bool diff --git a/src/superio/via/vt1211/Makefile.inc b/src/superio/via/vt1211/Makefile.inc deleted file mode 100644 index d3044af..0000000 --- a/src/superio/via/vt1211/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_VIA_VT1211) += superio.c diff --git a/src/superio/via/vt1211/superio.c b/src/superio/via/vt1211/superio.c deleted file mode 100644 index 4d7c8de..0000000 --- a/src/superio/via/vt1211/superio.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pnp.h> -#include <superio/conf_mode.h> -#include <stdlib.h> -#include "vt1211.h" - -static u8 hwm_io_regs[] = { - 0x10,0x03, 0x11,0x10, 0x12,0x0d, 0x13,0x7f, - 0x14,0x21, 0x15,0x81, 0x16,0xbd, 0x17,0x8a, - 0x18,0x00, 0x19,0x00, 0x1a,0x00, 0x1b,0x00, - 0x1d,0xff, 0x1e,0x00, 0x1f,0x73, 0x20,0x67, - 0x21,0xc1, 0x22,0xca, 0x23,0x74, 0x24,0xc2, - 0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x00, - 0x2a,0x00, 0x2b,0xff, 0x2c,0x00, 0x2d,0xff, - 0x2e,0x00, 0x2f,0xff, 0x30,0x00, 0x31,0xff, - 0x32,0x00, 0x33,0xff, 0x34,0x00, 0x39,0xff, - 0x3a,0x00, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff, - 0x3e,0x00, 0x3f,0xb0, 0x43,0xff, 0x44,0xff, - 0x46,0xff, 0x47,0x50, 0x4a,0x03, 0x4b,0xc0, - 0x4c,0x00, 0x4d,0x00, 0x4e,0x0f, 0x5d,0x77, - 0x5c,0x00, 0x5f,0x33, 0x40,0x01, -}; - -static void vt1211_set_iobase(struct device *dev, u8 index, u16 iobase) -{ - switch (dev->path.pnp.device) { - case VT1211_FDC: - case VT1211_PP: - case VT1211_SP1: - case VT1211_SP2: - pnp_write_config(dev, index + 0, (iobase >> 2) & 0xff); - break; - case VT1211_ROM: - /* TODO: Error. VT1211_ROM doesn't have an I/O base. */ - break; - case VT1211_MIDI: - case VT1211_GAME: - case VT1211_GPIO: - case VT1211_WDG: - case VT1211_WUC: - case VT1211_HWM: - case VT1211_FIR: - default: - pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); - pnp_write_config(dev, index + 1, iobase & 0xff); - break; - } -} - -/* Initialize VT1211 hardware monitor registers, which are at 0xECXX. */ -static void init_hwm(u16 base) -{ - int i; - - for (i = 0; i < sizeof(hwm_io_regs); i += 2) - outb(hwm_io_regs[i + 1], base + hwm_io_regs[i]); -} - -static void vt1211_init(struct device *dev) -{ - struct resource *res0; - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case VT1211_HWM: - res0 = find_resource(dev, PNP_IDX_IO0); - init_hwm(res0->base); - break; - case VT1211_FDC: - case VT1211_PP: - case VT1211_MIDI: - case VT1211_GAME: - case VT1211_GPIO: - case VT1211_WDG: - case VT1211_WUC: - case VT1211_FIR: - case VT1211_ROM: - /* TODO: Any init needed for these LDNs? */ - break; - default: - printk(BIOS_INFO, "VT1211: Cannot init unknown device!\n"); - } -} - -static void vt1211_pnp_enable_resources(struct device *dev) -{ - printk(BIOS_DEBUG, "%s - enabling\n", dev_path(dev)); - pnp_enable_resources(dev); -} - -static void vt1211_pnp_set_resources(struct device *dev) -{ - struct resource *res; - -#if CONFIG(CONSOLE_SERIAL) && CONFIG(DRIVERS_UART_8250IO) - /* TODO: Do the same for SP2? */ - if (dev->path.pnp.device == VT1211_SP1) { - for (res = dev->resource_list; res; res = res->next) { - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } - return; - } -#endif - - pnp_enter_conf_mode(dev); - - pnp_set_logical_device(dev); - - /* Paranoia says I should disable the device here... */ - for (res = dev->resource_list; res; res = res->next) { - if (!(res->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx " - "not assigned\n", dev_path(dev), res->index, - resource_type(res), res->size); - continue; - } - - /* Now store the resource. */ - if (res->flags & IORESOURCE_IO) { - vt1211_set_iobase(dev, res->index, res->base); - } else if (res->flags & IORESOURCE_DRQ) { - pnp_set_drq(dev, res->index, res->base); - } else if (res->flags & IORESOURCE_IRQ) { - pnp_set_irq(dev, res->index, res->base); - } else { - printk(BIOS_ERR, "ERROR: %s %02lx unknown resource " - "type\n", dev_path(dev), res->index); - return; - } - res->flags |= IORESOURCE_STORED; - - report_resource_stored(dev, res, ""); - } - - pnp_exit_conf_mode(dev); -} - -struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = vt1211_pnp_set_resources, - .enable_resources = vt1211_pnp_enable_resources, - .enable = pnp_alt_enable, - .init = vt1211_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, -}; - -/* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */ -static struct pnp_info pnp_dev_info[] = { - { NULL, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, VT1211_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, VT1211_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, 0xfffc, }, - { NULL, VT1211_GAME, PNP_IO0, 0xfff8, }, - { NULL, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, VT1211_WDG, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, VT1211_WUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, VT1211_HWM, PNP_IO0 | PNP_IRQ0, 0xff00, }, - { NULL, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0xff00, }, - { NULL, VT1211_ROM, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_via_vt1211_ops = { - CHIP_NAME("VIA VT1211 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/via/vt1211/vt1211.h b/src/superio/via/vt1211/vt1211.h deleted file mode 100644 index 9f0a1ef..0000000 --- a/src/superio/via/vt1211/vt1211.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_VIA_VT1211_VT1211_H -#define SUPERIO_VIA_VT1211_VT1211_H - -/* Logical device numbers (LDNs). */ -#define VT1211_FDC 0x00 /* Floppy */ -#define VT1211_PP 0x01 /* Parallel port */ -#define VT1211_SP1 0x02 /* COM1 */ -#define VT1211_SP2 0x03 /* COM2 */ -#define VT1211_MIDI 0x06 /* MIDI */ -#define VT1211_GAME 0x07 /* Game port (GMP) */ -#define VT1211_GPIO 0x08 /* GPIO */ -#define VT1211_WDG 0x09 /* Watchdog timer (WDG) */ -#define VT1211_WUC 0x0a /* Wake-up control (WUC) */ -#define VT1211_HWM 0x0b /* Hardware monitor (HM) */ -#define VT1211_FIR 0x0c /* Very fast IR (VFIR/FIR) */ -#define VT1211_ROM 0x0d /* Flash ROM */ - -#endif diff --git a/src/superio/winbond/w83697hf/Kconfig b/src/superio/winbond/w83697hf/Kconfig deleted file mode 100644 index 6ca03fe..0000000 --- a/src/superio/winbond/w83697hf/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_WINBOND_W83697HF - bool - select SUPERIO_WINBOND_COMMON_PRE_RAM diff --git a/src/superio/winbond/w83697hf/Makefile.inc b/src/superio/winbond/w83697hf/Makefile.inc deleted file mode 100644 index d1ef2b0..0000000 --- a/src/superio/winbond/w83697hf/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_WINBOND_W83697HF) += superio.c diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h deleted file mode 100644 index f7fc798..0000000 --- a/src/superio/winbond/w83697hf/chip.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_WINBOND_W83697HF_CHIP_H -#define SUPERIO_WINBOND_W83697HF_CHIP_H - - -struct superio_winbond_w83697hf_config { - unsigned int hwmon_fan1_divisor; - unsigned int hwmon_fan2_divisor; -}; - -#endif /* SUPERIO_WINBOND_W83697HF_CHIP_H */ diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c deleted file mode 100644 index a3c132c..0000000 --- a/src/superio/winbond/w83697hf/superio.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/device.h> -#include <device/pnp.h> -#include <superio/conf_mode.h> -#include <console/console.h> -#include <lib.h> -#include <stdlib.h> -#include "chip.h" -#include "w83697hf.h" - -static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { - unsigned char enc, buf; - - if (divisor) { - enc = log2(divisor); - if (1 << enc != divisor || enc > 7) - die("invalid fan divisor"); - outb(0x4e, base + 5); - outb(0x00, base + 6); - outb(0x47, base + 5); - outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); - outb(0x5d, base + 5); - buf = inb(base + 6); - /* the above inb() auto-increments the address pointer ... */ - outb(0x5d, base + 5); - outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); - } -} - -static void w83697hf_init(struct device *dev) -{ - struct resource *res0; - struct superio_winbond_w83697hf_config *cfg; - - if (!dev->enabled) - return; - - cfg = dev->chip_info; - - switch (dev->path.pnp.device) { - case W83697HF_HWM: - if (cfg) { - res0 = find_resource(dev, PNP_IDX_IO0); - hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); - hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); - } - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = w83697hf_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, W83697HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, W83697HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, W83697HF_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, W83697HF_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, W83697HF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, - 0x07ff, 0x07fe, }, - { NULL, W83697HF_MIDI_GPIO5, }, - { NULL, W83697HF_GPIO234, }, - { NULL, W83697HF_ACPI, }, - { NULL, W83697HF_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_winbond_w83697hf_ops = { - CHIP_NAME("Winbond W83697HF Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h deleted file mode 100644 index 52466a8..0000000 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_WINBOND_W83697HF_H -#define SUPERIO_WINBOND_W83697HF_H - -#define W83697HF_FDC 0 /* Floppy */ -#define W83697HF_PP 1 /* Parallel port */ -#define W83697HF_SP1 2 /* Com1 */ -#define W83697HF_SP2 3 /* Com2 */ -#define W83697HF_CIR 6 /* Consumer IR */ -#define W83697HF_GAME_GPIO1 7 /* Game port, GPIO 1 */ -#define W83697HF_MIDI_GPIO5 8 /* MIDI, GPIO 5 */ -#define W83697HF_GPIO234 9 /* GPIO 2, 3, 4 */ -#define W83697HF_ACPI 10 /* ACPI */ -#define W83697HF_HWM 11 /* Hardware monitor */ - -#endif /* SUPERIO_WINBOND_W83697HF_H */ diff --git a/src/superio/winbond/wpcd376i/Kconfig b/src/superio/winbond/wpcd376i/Kconfig deleted file mode 100644 index 57cce7b..0000000 --- a/src/superio/winbond/wpcd376i/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_WINBOND_WPCD376I - bool - select SUPERIO_WINBOND_COMMON_PRE_RAM diff --git a/src/superio/winbond/wpcd376i/Makefile.inc b/src/superio/winbond/wpcd376i/Makefile.inc deleted file mode 100644 index cebd175..0000000 --- a/src/superio/winbond/wpcd376i/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += early_serial.c -romstage-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += early_serial.c -ramstage-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += superio.c diff --git a/src/superio/winbond/wpcd376i/chip.h b/src/superio/winbond/wpcd376i/chip.h deleted file mode 100644 index c16743d..0000000 --- a/src/superio/winbond/wpcd376i/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_WINBOND_WPCD376I_CHIP_H -#define SUPERIO_WINBOND_WPCD376I_CHIP_H - -struct superio_winbond_wpcd376i_config { -}; -#endif diff --git a/src/superio/winbond/wpcd376i/early_serial.c b/src/superio/winbond/wpcd376i/early_serial.c deleted file mode 100644 index 9f9ff6b..0000000 --- a/src/superio/winbond/wpcd376i/early_serial.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Marc Jones <marcj303(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Pre-RAM driver for the Winbond WPCD376I Super I/O chip. */ - - -#include <device/pnp_ops.h> -#include <device/pnp_def.h> -#include "wpcd376i.h" - -void wpcd376i_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c deleted file mode 100644 index ae4fce4..0000000 --- a/src/superio/winbond/wpcd376i/superio.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <drivers/uart/uart8250reg.h> -#include <pc80/keyboard.h> -#include <stdlib.h> -#include "chip.h" -#include "wpcd376i.h" - -static void init(struct device *dev) -{ - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case WPCD376I_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, WPCD376I_FDC, - PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC8, - 0x07f8, }, - { NULL, WPCD376I_LPT, - PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC8, - 0x03f8, }, - { NULL, WPCD376I_SP1, - PNP_IO0 | PNP_IRQ0 | PNP_MSC0, - 0x07f8, }, - { NULL, WPCD376I_SWC, - PNP_IO0 | PNP_IO1 | PNP_IRQ0, - 0xfff0, 0xfff0, }, - { NULL, WPCD376I_KBCM, - PNP_IRQ0, }, - { NULL, WPCD376I_KBCK, - PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, - 0x07f8, 0x07f8, }, - { NULL, WPCD376I_GPIO, - PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | - PNP_MSC8, - 0xffe0, }, - { NULL, WPCD376I_ECIR, - PNP_IO0 | PNP_IO1 | PNP_IRQ0, - 0xfff0, 0xfff0, }, - { NULL, WPCD376I_IR, - PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1 | PNP_MSC0, - 0xfff8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_winbond_wpcd376i_ops = { - CHIP_NAME("Winbond WPCD376I Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/winbond/wpcd376i/wpcd376i.h b/src/superio/winbond/wpcd376i/wpcd376i.h deleted file mode 100644 index a90b13b..0000000 --- a/src/superio/winbond/wpcd376i/wpcd376i.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_WINBOND_WPCD376I_WPCD376I_H -#define SUPERIO_WINBOND_WPCD376I_WPCD376I_H - -#include <device/pnp_type.h> - -/* Logical Device Numbers (LDN). */ -#define WPCD376I_FDC 0x00 /* Floppy */ -#define WPCD376I_LPT 0x01 /* Parallel port */ -/* 0x02 Undefined */ -#define WPCD376I_SP1 0x03 /* UART1 */ -#define WPCD376I_SWC 0x04 /* System wake-up control */ -#define WPCD376I_KBCM 0x05 /* PS/2 mouse */ -#define WPCD376I_KBCK 0x06 /* PS/2 keyboard */ -#define WPCD376I_GPIO 0x07 /* General Purpose I/O */ -#define WPCD376I_ECIR 0x15 /* Enhanced Consumer Infrared Functions (ECIR) */ -#define WPCD376I_IR 0x16 /* UART3 & Infrared port */ - -void wpcd376i_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61d486d2c1e2b85eb292eaa78316c36e1735ebf4 Gerrit-Change-Number: 35428 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019