coreboot-gerrit November 2019

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Change in coreboot[master]: google/endeavour: add variant based on karma
by Jeff Chase (Code Review) 10 Jan '20

10 Jan '20

Jeff Chase has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36791 ) Change subject: google/endeavour: add variant based on karma ...................................................................... google/endeavour: add variant based on karma BUG=b:144307303 TEST=build Change-Id: I09a10e99877d18361b31b36bed703b02508ccd05 --- M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/Kconfig.name A src/mainboard/google/fizz/variants/endeavour/Makefile.inc A src/mainboard/google/fizz/variants/endeavour/gpio.c A src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl A src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h A src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h A src/mainboard/google/fizz/variants/endeavour/nhlt.c A src/mainboard/google/fizz/variants/endeavour/overridetree.cb 9 files changed, 389 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/36791/1 diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 44ac064..689f5ec 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -52,11 +52,13 @@ string default "Fizz" if BOARD_GOOGLE_FIZZ default "Karma" if BOARD_GOOGLE_KARMA + default "Endeavour" if BOARD_GOOGLE_ENDEAVOUR config MAINBOARD_FAMILY string default "Google_Fizz" if BOARD_GOOGLE_FIZZ default "Google_Kalista" if BOARD_GOOGLE_KARMA + default "Google_Endeavour" if BOARD_GOOGLE_ENDEAVOUR config MAX_CPUS int @@ -78,6 +80,7 @@ string default "fizz" if BOARD_GOOGLE_FIZZ default "karma" if BOARD_GOOGLE_KARMA + default "endeavour" if BOARD_GOOGLE_ENDEAVOUR config INCLUDE_NHLT_BLOBS bool "Include blobs for audio." diff --git a/src/mainboard/google/fizz/Kconfig.name b/src/mainboard/google/fizz/Kconfig.name index 608a58d..45cdbd9 100644 --- a/src/mainboard/google/fizz/Kconfig.name +++ b/src/mainboard/google/fizz/Kconfig.name @@ -7,3 +7,7 @@ config BOARD_GOOGLE_KARMA bool "-> Karma" select BOARD_GOOGLE_BASEBOARD_FIZZ + +config BOARD_GOOGLE_ENDEAVOUR + bool "-> Endeavour" + select BOARD_GOOGLE_BASEBOARD_FIZZ diff --git a/src/mainboard/google/fizz/variants/endeavour/Makefile.inc b/src/mainboard/google/fizz/variants/endeavour/Makefile.inc new file mode 100644 index 0000000..0ad298b --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += nhlt.c diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c new file mode 100644 index 0000000..c11055c --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -0,0 +1,280 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */ +/* ESPI_IO0 */ +/* ESPI_IO1 */ +/* ESPI_IO2 */ +/* ESPI_IO3 */ +/* ESPI_CS# */ +/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ +/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, + EDGE), /* SD_CDZ */ +/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ +/* ESPI_CLK */ +/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ +/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ +/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, + DEEP), /* eSPI mode */ +/* ESPI_RESET# */ +/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */ +/* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */ +/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), + +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */ +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ +/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), +/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, + NF1), /* CLK_PCIE_LAN_REQ# */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, + NF1), /* PCIE_CLKREQ_SSD# */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, + NF1), /* PCIE_CLKREQ_NGFF1# */ +/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */ +/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */ +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, + NF1), /* PCIE_CLKREQ_WLAN# */ +/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */ +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */ +/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */ +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MOSI */ +/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ +/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU, + DEEP), /* VR_DISABLE_L */ +/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU, + DEEP), /* HWA_TRST_N */ +/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ +/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */ + +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ +/* SMBALERT# */ PAD_CFG_NC(GPP_C2), +/* SML0CLK */ PAD_CFG_NC(GPP_C3), +/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, + DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */ +/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU, + DEEP), /* GPIO1 */ +/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU, + DEEP), /* GPIO2 */ +/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU, + DEEP), /* GPIO3 */ +/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU, + DEEP), /* GPIO4 */ +/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, + DEEP), /* SKU_ID0 */ +/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, + DEEP), /* SKU_ID1 */ +/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, + DEEP), /* SKU_ID2 */ +/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, + DEEP), /* SKU_ID3 */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), +/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, + DEEP), /* SCREW_SPI_WP_STATUS */ + +/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */ +/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */ +/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */ +/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */ +/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */ +/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), +/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), +/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, + PLTRST, EDGE), /* HP_IRQ_GPIO */ +/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, + DEEP), /* OEM_ID1 */ +/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, + DEEP), /* OEM_ID2 */ +/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, + DEEP), /* OEM_ID3 */ +/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), +/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), +/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), +/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP121 */ +/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP122 */ +/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */ +/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP258 */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ + +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, + PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, + NF1), /* MB_PCIE_SATA#_DET */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, + NF1), /* DB_PCIE_SATA#_DET */ +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ +/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), +/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */ +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */ +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, + NF1), /* Rear Dual-Stack USB Ports */ +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, + NF1), /* Front USB Ports */ +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, + NF1), /* Rear Single USB Port */ +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, + NF1), /* INT_HDMI_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, + NF1), /* DDI2_HPD */ +/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */ +/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */ +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, + NF1), /* HDMI_DDCCLK_SW */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, + NF1), /* HDMI_DDCCLK_DATA */ +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */ +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */ +/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), + +/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP191 */ +/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP192 */ +/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP190 */ +/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */ +/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, + NF1), /* PCH_I2C2_H1_3V3_SDA */ +/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, + NF1), /* PCH_I2C2_H1_3V3_SCL */ +/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), +/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), +/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), +/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, + NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ +/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, + NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ +/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), +/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), +/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), +/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), +/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), +/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), +/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), +/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), +/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), +/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), +/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), +/* RSVD */ PAD_CFG_NC(GPP_F23), + +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */ +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */ + +/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */ +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ +/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */ +/* RSVD */ PAD_CFG_NC(GPD7), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ +/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */ +/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */ +/* LANPHYC */ PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MOSI */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, + PLTRST), /* H1_PCH_INT_ODL */ +/* Ensure UART pins are in native mode for H1. */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, + DEEP), /* SCREW_SPI_WP_STATUS */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, + NF1), /* MB_PCIE_SATA#_DET */ +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ +}; + +const struct pad_config * __weak variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config * __weak + variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio * __weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl b/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..1e82bc9 --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h b/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h new file mode 100644 index 0000000..1396a2f --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <baseboard/ec.h> + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h b/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h new file mode 100644 index 0000000..3f82b9f --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/fizz/variants/endeavour/nhlt.c b/src/mainboard/google/fizz/variants/endeavour/nhlt.c new file mode 100644 index 0000000..07a66e8 --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/nhlt.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <baseboard/variants.h> +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +void __weak variant_nhlt_init(struct nhlt *nhlt) +{ + + /* RT5663 Headset codec */ + if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + +} + +void __weak variant_nhlt_oem_overrides(const char **oem_id, + const char **oem_table_id, + uint32_t *oem_revision) +{ + *oem_id = "GOOGLE"; + *oem_table_id = "ENDEAVOUR"; + *oem_revision = 0; +} diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb new file mode 100644 index 0000000..500e6cf --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/skylake + device domain 0 on + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/36791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a10e99877d18361b31b36bed703b02508ccd05 Gerrit-Change-Number: 36791 Gerrit-PatchSet: 1 Gerrit-Owner: Jeff Chase <jnchase(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm: Don't redefine LAPIC_ID
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37173 ) Change subject: cpu/x86/smm: Don't redefine LAPIC_ID ...................................................................... cpu/x86/smm: Don't redefine LAPIC_ID Use already defined LAPIC_ID in <cpu/x86/lapic_def.h>. Change-Id: Iaf7da1ea0df58020fe53f2a3482b0f535265b03f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/smm/smihandler.c M src/cpu/x86/smm/smmrelocate.S 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/37173/1 diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 20417d1..9710142 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -15,6 +15,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> +#include <cpu/x86/lapic_def.h> #include <cpu/x86/smm.h> #include <cpu/x86/smi_deprecated.h> #include <cpu/amd/amd64_save_state.h> @@ -78,10 +79,9 @@ ); } -#define LAPIC_ID 0xfee00020 static __always_inline unsigned long nodeid(void) { - return (*((volatile unsigned long *)(LAPIC_ID)) >> 24); + return (*((volatile unsigned long *)(LOCAL_APIC_ADDR | LAPIC_ID)) >> 24); } void io_trap_handler(int smif) diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index f64b365..1ee7b59 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -31,7 +31,7 @@ #error "Only use this file with ASEG." #endif /* CONFIG_SMM_ASEG */ -#define LAPIC_ID 0xfee00020 +#include <cpu/x86/lapic_def.h> .global smm_relocation_start .global smm_relocation_end @@ -113,7 +113,7 @@ smm_relocate: /* Get this CPU's LAPIC ID */ - movl $LAPIC_ID, %esi + movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi ADDR32(movl) (%esi), %ecx shr $24, %ecx -- To view, visit https://review.coreboot.org/c/coreboot/+/37173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf7da1ea0df58020fe53f2a3482b0f535265b03f Gerrit-Change-Number: 37173 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/i945: Consolidate sdram_setup_processor_side()
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33781 Change subject: nb/i945: Consolidate sdram_setup_processor_side() ...................................................................... nb/i945: Consolidate sdram_setup_processor_side() Change-Id: I9c5aae06ae8e3643253fe4a5b080448403f81ebc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/33781/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 281e7b2..c994786 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2695,13 +2695,11 @@ static void sdram_setup_processor_side(void) { - if (i945_silicon_revision() == 0) + if (i945_silicon_revision() == 0) { MCHBAR32(FSBPMC3) |= (1 << 2); - - MCHBAR8(0xb00) |= 1; - - if (i945_silicon_revision() == 0) MCHBAR32(SLPCTL) |= (1 << 8); + } + MCHBAR8(0xb00) |= 1; } /** -- To view, visit https://review.coreboot.org/c/coreboot/+/33781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c5aae06ae8e3643253fe4a5b080448403f81ebc Gerrit-Change-Number: 33781 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: nb/i945: Remove unneeded whitespaces
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36467 ) Change subject: nb/i945: Remove unneeded whitespaces ...................................................................... nb/i945: Remove unneeded whitespaces Change-Id: Ib1cbb5d466666eff6006d1137525dd5fb0de8e18 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/36467/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 7096774..27fdf00 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -816,9 +816,9 @@ const u8 *slew_group; /* Dual Channel needs different tables. */ if (dual_channel) - slew_group = dual_channel_slew_group_lookup; + slew_group = dual_channel_slew_group_lookup; else - slew_group = single_channel_slew_group_lookup; + slew_group = single_channel_slew_group_lookup; switch (slew_group[index]) { case DQ2030: return dq2030; @@ -957,7 +957,7 @@ printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n"); strength_multiplier = dual_channel_strength_multiplier; dual_channel = 1; - idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; + idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; } else { printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n"); strength_multiplier = single_channel_strength_multiplier; @@ -1209,7 +1209,7 @@ if (sysinfo->interleaved) tolud = (cum0 + cum1) << 1; else - tolud = (cum1 ? cum1 : cum0) << 1; + tolud = (cum1 ? cum1 : cum0) << 1; /* The TOM register has a different format */ tom = tolud >> 3; @@ -1349,7 +1349,7 @@ reg32 |= (1 << 11); MCHBAR32(C0DRC1) = reg32; - /* Do we have to do this if we're in Single Channel Mode? */ + /* Do we have to do this if we're in Single Channel Mode? */ reg32 = MCHBAR32(C1DRC1); for (i = 4; i < 8; i++) { @@ -1706,7 +1706,7 @@ if (voltage == VOLTAGE_1_50) { second_vco = 1; - } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) { + } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) { u16 mem = sysinfo->memory_frequency; u16 fsb = sysinfo->fsb_frequency; @@ -2034,7 +2034,7 @@ u32 chan0 = 0, chan1 = 0; int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated; - chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || + chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); chan1_populated = (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED); @@ -2514,7 +2514,7 @@ } #define RTT_ODT_NONE 0 -#define RTT_ODT_50_OHM ((1 << 9) | (1 << 5)) +#define RTT_ODT_50_OHM ((1 << 9) | (1 << 5)) #define RTT_ODT_75_OHM (1 << 5) #define RTT_ODT_150_OHM (1 << 9) -- To view, visit https://review.coreboot.org/c/coreboot/+/36467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1cbb5d466666eff6006d1137525dd5fb0de8e18 Gerrit-Change-Number: 36467 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: nb/intel/i440bx: Remove never used 'dra' value
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34558 ) Change subject: nb/intel/i440bx: Remove never used 'dra' value ...................................................................... nb/intel/i440bx: Remove never used 'dra' value Change-Id: I65c41f56d7a0639eac821844e653e5644aca4f0c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i440bx/raminit.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/34558/1 diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 91959c7..3a1b66a 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -799,7 +799,6 @@ } /* "DRA" is our RPS for the two rows on this DIMM. */ - dra = 0; /* Columns */ col = spd_read_byte(device, SPD_NUM_COLUMNS); -- To view, visit https://review.coreboot.org/c/coreboot/+/34558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c41f56d7a0639eac821844e653e5644aca4f0c Gerrit-Change-Number: 34558 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x4x/gma: Store 'vga_disable' if MAINBOARD_USE_LIBGFXINIT
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34434 ) Change subject: nb/intel/x4x/gma: Store 'vga_disable' if MAINBOARD_USE_LIBGFXINIT ...................................................................... nb/intel/x4x/gma: Store 'vga_disable' if MAINBOARD_USE_LIBGFXINIT Found-by: scan-build 7.0.1-8 Change-Id: I6feaa3a19d44b1d6f650bc7bc72dc575b032f4b1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/x4x/gma.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/34434/1 diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 61731fe..6577153 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -68,9 +68,8 @@ /* configure GMBUSFREQ */ pci_update_config16(dev, 0xcc, ~0x1ff, 0xbc); - int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; - if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; if (vga_disable) { printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/34434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6feaa3a19d44b1d6f650bc7bc72dc575b032f4b1 Gerrit-Change-Number: 34434 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: sb/intel/i82801gx: Remove superfluous tabs
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36928 ) Change subject: sb/intel/i82801gx: Remove superfluous tabs ...................................................................... sb/intel/i82801gx: Remove superfluous tabs Change-Id: Ia12836c6a3bb412afc3c0f0089704c1298da6d16 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801gx/i82801gx.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/36928/1 diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 75b9575..1fca400 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -88,4 +88,4 @@ uint32_t gen4_dec; }; -#endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */ +#endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3d27faa..f28d2b2 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -356,4 +356,4 @@ #define TCO1_CNT 0x68 #endif /* __ACPI__ */ -#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ +#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia12836c6a3bb412afc3c0f0089704c1298da6d16 Gerrit-Change-Number: 36928 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/dram/ddr2.c: Code re-formating
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36858 ) Change subject: device/dram/ddr2.c: Code re-formating ...................................................................... device/dram/ddr2.c: Code re-formating Change-Id: I937aadca21ddaa9ab4ae354c3a1324a222ae0ff6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr2.c 1 file changed, 47 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/36858/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 5319806..299a590 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -12,7 +12,7 @@ * GNU General Public License for more details. */ -/** +/* * @file ddr2.c * * \brief Utilities for decoding DDR2 SPDs @@ -29,7 +29,7 @@ * = DDR2 SPD decoding helpers *----------------------------------------------------------------------------*/ -/** +/* * \brief Checks if the DIMM is Registered based on byte[20] of the SPD * * Tells if the DIMM type is registered or not. @@ -38,15 +38,15 @@ */ int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type) { - if ((type == SPD_DDR2_DIMM_TYPE_RDIMM) - || (type == SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM) - || (type == SPD_DDR2_DIMM_TYPE_MINI_RDIMM)) + if ((type == SPD_DDR2_DIMM_TYPE_RDIMM) || + (type == SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM) || + (type == SPD_DDR2_DIMM_TYPE_MINI_RDIMM)) return 1; return 0; } -/** +/* * \brief Calculate the checksum of a DDR2 SPD unique identifier * * @param spd pointer to raw SPD data @@ -69,7 +69,7 @@ return c; } -/** +/* * \brief Calculate the CRC of a DDR2 SPD unique identifier * * @param spd pointer to raw SPD data @@ -93,7 +93,7 @@ return ddr_crc16(id_bytes, 15); } -/** +/* * \brief Return size of SPD. * * Returns size of SPD. Usually 128 Byte. @@ -103,7 +103,7 @@ return MIN(byte0, SPD_SIZE_MAX_DDR2); } -/** +/* * \brief Return size of eeprom. * * Returns size of eeprom. Usually 256 Byte. @@ -119,7 +119,7 @@ return 1 << byte1; } -/** +/* * \brief Return index of MSB set * * Returns the index of MSB set. @@ -129,7 +129,7 @@ return log2(c); } -/** +/* * \brief Decode SPD tck cycle time * * Decodes a raw SPD data from a DDR2 DIMM. @@ -156,8 +156,7 @@ break; case 0xe: case 0xf: - printk(BIOS_WARNING, "Invalid tck setting. " - "lower nibble is 0x%x\n", c & 0xf); + printk(BIOS_WARNING, "Invalid tck setting. lower nibble is 0x%x\n", c & 0xf); return CB_ERR; default: low = (c & 0xf) * 10; @@ -167,7 +166,7 @@ return CB_SUCCESS; } -/** +/* * \brief Decode SPD bcd style timings * * Decodes a raw SPD data from a DDR2 DIMM. @@ -186,7 +185,7 @@ return CB_SUCCESS; } -/** +/* * \brief Decode SPD tRP, tRRP cycle time * * Decodes a raw SPD data from a DDR2 DIMM. @@ -202,7 +201,7 @@ return ((high * 100 + low) << 8) / 100; } -/** +/* * \brief Decode SPD tRR time * * Decodes a raw SPD data from a DDR2 DIMM. @@ -236,7 +235,7 @@ return CB_SUCCESS; } -/** +/* * \brief Decode SPD tRC,tRFC time * * Decodes a raw SPD data from a DDR2 DIMM. @@ -301,7 +300,7 @@ *tRFC = (*tRFC << 8) / 100; } -/** +/* * \brief Decode the raw SPD data * * Decodes a raw SPD data from a DDR2 DIMM, and organizes it into a @@ -348,9 +347,8 @@ reg8 = spd[62]; if ((reg8 & 0xf0) != 0x10) { - printk(BIOS_WARNING, - "ERROR: Unsupported SPD revision %01x.%01x\n", - reg8 >> 4, reg8 & 0xf); + printk(BIOS_WARNING, "ERROR: Unsupported SPD revision %01x.%01x\n", reg8 >> 4, + reg8 & 0xf); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; } @@ -368,18 +366,15 @@ dimm->row_bits = spd[3]; printram(" Rows : %u\n", dimm->row_bits); - if ((dimm->row_bits > 31) || - ((dimm->row_bits > 15) && (dimm->rev < 0x13))) { - printk(BIOS_WARNING, - "SPD decode: invalid number of memory rows\n"); + if ((dimm->row_bits > 31) || ((dimm->row_bits > 15) && (dimm->rev < 0x13))) { + printk(BIOS_WARNING, "SPD decode: invalid number of memory rows\n"); ret = SPD_STATUS_INVALID_FIELD; } dimm->col_bits = spd[4]; printram(" Columns : %u\n", dimm->col_bits); if (dimm->col_bits > 15) { - printk(BIOS_WARNING, - "SPD decode: invalid number of memory columns\n"); + printk(BIOS_WARNING, "SPD decode: invalid number of memory columns\n"); ret = SPD_STATUS_INVALID_FIELD; } @@ -403,8 +398,7 @@ dimm->banks = spd[17]; printram(" Banks : %u\n", dimm->banks); if (!dimm->banks) { - printk(BIOS_WARNING, - "SPD decode: invalid module banks count\n"); + printk(BIOS_WARNING, "SPD decode: invalid module banks count\n"); ret = SPD_STATUS_INVALID_FIELD; } @@ -440,20 +434,17 @@ dimm->cas_supported = spd[18]; if ((dimm->cas_supported & 0x3) || !dimm->cas_supported) { - printk(BIOS_WARNING, - "SPD decode: invalid CAS support advertised.\n"); + printk(BIOS_WARNING, "SPD decode: invalid CAS support advertised.\n"); ret = SPD_STATUS_INVALID_FIELD; } printram(" Supported CAS mask : 0x%x\n", dimm->cas_supported); if ((dimm->rev < 0x13) && (dimm->cas_supported & 0x80)) { - printk(BIOS_WARNING, - "SPD decode: invalid CAS support advertised.\n"); + printk(BIOS_WARNING, "SPD decode: invalid CAS support advertised.\n"); ret = SPD_STATUS_INVALID_FIELD; } if ((dimm->rev < 0x12) && (dimm->cas_supported & 0x40)) { - printk(BIOS_WARNING, - "SPD decode: invalid CAS support advertised.\n"); + printk(BIOS_WARNING, "SPD decode: invalid CAS support advertised.\n"); ret = SPD_STATUS_INVALID_FIELD; } @@ -462,59 +453,43 @@ /* SDRAM Cycle time at Maximum Supported CAS Latency (CL), CL=X */ if (spd_decode_tck_time(&dimm->cycle_time[cl], spd[9]) != CB_SUCCESS) { - printk(BIOS_WARNING, - "SPD decode: invalid min tCL for CAS%d\n", cl); + printk(BIOS_WARNING, "SPD decode: invalid min tCL for CAS%d\n", cl); ret = SPD_STATUS_INVALID_FIELD; } /* SDRAM Access from Clock */ - if (spd_decode_bcd_time(&dimm->access_time[cl], spd[10]) - != CB_SUCCESS) { - printk(BIOS_WARNING, - "SPD decode: invalid min tAC for CAS%d\n", cl); + if (spd_decode_bcd_time(&dimm->access_time[cl], spd[10]) != CB_SUCCESS) { + printk(BIOS_WARNING, "SPD decode: invalid min tAC for CAS%d\n", cl); ret = SPD_STATUS_INVALID_FIELD; } if (dimm->cas_supported & (1 << (cl - 1))) { /* Minimum Clock Cycle at CLX-1 */ - if (spd_decode_tck_time(&dimm->cycle_time[cl - 1], spd[23]) - != CB_SUCCESS) { - printk(BIOS_WARNING, - "SPD decode: invalid min tCL for CAS%d\n", - cl - 1); + if (spd_decode_tck_time(&dimm->cycle_time[cl - 1], spd[23]) != CB_SUCCESS) { + printk(BIOS_WARNING, "SPD decode: invalid min tCL for CAS%d\n", cl - 1); ret = SPD_STATUS_INVALID_FIELD; } /* Maximum Data Access Time (tAC) from Clock at CLX-1 */ - if (spd_decode_bcd_time(&dimm->access_time[cl - 1], spd[24]) - != CB_SUCCESS) { - printk(BIOS_WARNING, - "SPD decode: invalid min tAC for CAS%d\n", - cl - 1); + if (spd_decode_bcd_time(&dimm->access_time[cl - 1], spd[24]) != CB_SUCCESS) { + printk(BIOS_WARNING, "SPD decode: invalid min tAC for CAS%d\n", cl - 1); ret = SPD_STATUS_INVALID_FIELD; } } if (dimm->cas_supported & (1 << (cl - 2))) { /* Minimum Clock Cycle at CLX-2 */ - if (spd_decode_tck_time(&dimm->cycle_time[cl - 2], spd[25]) - != CB_SUCCESS) { - printk(BIOS_WARNING, - "SPD decode: invalid min tCL for CAS%d\n", - cl - 2); + if (spd_decode_tck_time(&dimm->cycle_time[cl - 2], spd[25]) != CB_SUCCESS) { + printk(BIOS_WARNING, "SPD decode: invalid min tCL for CAS%d\n", cl - 2); ret = SPD_STATUS_INVALID_FIELD; } /* Maximum Data Access Time (tAC) from Clock at CLX-2 */ - if (spd_decode_bcd_time(&dimm->access_time[cl - 2], spd[26]) - != CB_SUCCESS) { - printk(BIOS_WARNING, - "SPD decode: invalid min tAC for CAS%d\n", - cl - 2); + if (spd_decode_bcd_time(&dimm->access_time[cl - 2], spd[26]) != CB_SUCCESS) { + printk(BIOS_WARNING, "SPD decode: invalid min tAC for CAS%d\n", cl - 2); ret = SPD_STATUS_INVALID_FIELD; } } reg8 = (spd[31] >> 5) | (spd[31] << 3); if (!reg8) { - printk(BIOS_WARNING, - "SPD decode: invalid rank density.\n"); + printk(BIOS_WARNING, "SPD decode: invalid rank density.\n"); ret = SPD_STATUS_INVALID_FIELD; } @@ -611,8 +586,7 @@ printram(" ECC support : %x\n", dimm->flags.is_ecc); dimm->flags.stacked = !!(spd[5] & 0x10); - printram(" Package : %s\n", - dimm->flags.stacked ? "stack" : "planar"); + printram(" Package : %s\n", dimm->flags.stacked ? "stack" : "planar"); if (spd_size > 71) { memcpy(&dimm->manufacturer_id, &spd[64], 4); @@ -662,14 +636,14 @@ printk(BIOS_INFO, "%s%3u.%.3u us\n", msg, mant, fp); } -/** -* \brief Print the info in DIMM -* -* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is -* selected, or for a purely informative output. -* -* @param dimm pointer to already decoded @ref dimm_attr structure -*/ +/* + * \brief Print the info in DIMM + * + * Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is + * selected, or for a purely informative output. + * + * @param dimm pointer to already decoded @ref dimm_attr structure + */ void dram_print_spd_ddr2(const struct dimm_attr_ddr2_st *dimm) { char buf[32]; -- To view, visit https://review.coreboot.org/c/coreboot/+/36858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I937aadca21ddaa9ab4ae354c3a1324a222ae0ff6 Gerrit-Change-Number: 36858 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Use <types.h> when <stdint.h> and <stddef.h> are needes
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37364 ) Change subject: src: Use <types.h> when <stdint.h> and <stddef.h> are needes ...................................................................... src: Use <types.h> when <stdint.h> and <stddef.h> are needes types.h is supposed to provide stdint.h and stddef.h headers. Also, some unused <stdlib.h> removed Change-Id: I1e0c2a4dfaa5b1cde0dd4a9e213be0b383e1017f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/exception.c M src/arch/arm/eabi_compat.c M src/arch/arm/include/armv4/arch/cache.h M src/arch/arm/include/armv7/arch/cache.h M src/arch/arm64/armv8/exception.c M src/arch/arm64/armv8/mmu.c M src/arch/arm64/include/armv8/arch/cache.h M src/arch/riscv/misaligned.c M src/arch/x86/include/arch/acpigen.h M src/arch/x86/include/arch/ebda.h M src/arch/x86/include/smm.h M src/commonlib/storage/bouncebuf.h M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/vstore.c M src/ec/google/wilco/chip.c M src/include/device/i2c_bus.h M src/lib/bootmem.c M src/lib/fit.c M src/lib/imd_cbmem.c M src/lib/rmodule.c M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/cavium/cn81xx/spi.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/skylake/me.c M src/soc/samsung/exynos5250/spi.c M src/soc/samsung/exynos5420/spi.c M src/soc/sifive/fu540/clock.c 27 files changed, 28 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37364/1 diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c index d6891b0..ea2b2b8 100644 --- a/src/arch/arm/armv7/exception.c +++ b/src/arch/arm/armv7/exception.c @@ -27,11 +27,10 @@ * SUCH DAMAGE. */ -#include <stdint.h> -#include <types.h> #include <arch/cache.h> #include <arch/exception.h> #include <console/console.h> +#include <types.h> uint8_t exception_stack[0x100] __attribute__((aligned(8))); extern void *exception_stack_end; diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c index 45f4651..8b80ee4 100644 --- a/src/arch/arm/eabi_compat.c +++ b/src/arch/arm/eabi_compat.c @@ -14,10 +14,9 @@ * Utility functions needed for (some) EABI conformant tool chains. */ -#include <stdint.h> -#include <stddef.h> #include <string.h> #include <console/console.h> +#include <types.h> /* FIXME(dhendrix): prototypes added for assembler */ int raise(int signum) __attribute__((used)); diff --git a/src/arch/arm/include/armv4/arch/cache.h b/src/arch/arm/include/armv4/arch/cache.h index ed3b96f..0fbc8a9 100644 --- a/src/arch/arm/include/armv4/arch/cache.h +++ b/src/arch/arm/include/armv4/arch/cache.h @@ -32,8 +32,7 @@ #ifndef ARM_CACHE_H #define ARM_CACHE_H -#include <stddef.h> -#include <stdint.h> +#include <types.h> /* * Cache maintenance API diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index b2b6a33..431a5bf 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -33,8 +33,7 @@ #ifndef ARM_CACHE_H #define ARM_CACHE_H -#include <stddef.h> -#include <stdint.h> +#include <types.h> /* SCTLR bits */ #define SCTLR_M (1 << 0) /* MMU enable */ diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 579e104..79cc4ce 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -27,14 +27,13 @@ * SUCH DAMAGE. */ -#include <stdint.h> -#include <types.h> #include <arch/barrier.h> #include <arch/cache.h> #include <arch/exception.h> #include <arch/transition.h> #include <console/console.h> #include <arch/lib_helpers.h> +#include <types.h> uint8_t exception_stack[0x200] __attribute__((aligned(16))); diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 67dca48..37db34d 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -28,11 +28,9 @@ */ #include <assert.h> -#include <stdlib.h> -#include <stdint.h> #include <string.h> #include <symbols.h> - +#include <types.h> #include <console/console.h> #include <arch/mmu.h> #include <arch/lib_helpers.h> diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 3de2e80..cd97140 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -55,10 +55,9 @@ #ifndef __ASSEMBLER__ -#include <stddef.h> -#include <stdint.h> #include <arch/barrier.h> #include <arch/lib_helpers.h> +#include <types.h> /* dcache clean by virtual address to PoC */ void dcache_clean_by_mva(void const *addr, size_t len); diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c index ebff2d6..7ae123f 100644 --- a/src/arch/riscv/misaligned.c +++ b/src/arch/riscv/misaligned.c @@ -13,11 +13,10 @@ * GNU General Public License for more details. */ -#include <stddef.h> -#include <stdint.h> #include <vm.h> #include <arch/exception.h> #include <commonlib/helpers.h> +#include <types.h> /* these functions are defined in src/arch/riscv/fp_asm.S */ #if defined(__riscv_flen) diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 6fd9f73..e8d68e7 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -14,11 +14,10 @@ #ifndef LIBACPI_H #define LIBACPI_H -#include <stdlib.h> -#include <stdint.h> #include <arch/acpi.h> #include <arch/acpi_device.h> #include <arch/acpi_pld.h> +#include <types.h> /* Values that can be returned for ACPI Device _STA method */ #define ACPI_STATUS_DEVICE_PRESENT (1 << 0) diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h index 6ee3332..638d2ad 100644 --- a/src/arch/x86/include/arch/ebda.h +++ b/src/arch/x86/include/arch/ebda.h @@ -15,8 +15,7 @@ #ifndef __ARCH_EBDA_H #define __ARCH_EBDA_H -#include <stdint.h> -#include <stddef.h> +#include <types.h> #define X86_BDA_SIZE 0x200 #define X86_BDA_BASE ((void *)0x400) diff --git a/src/arch/x86/include/smm.h b/src/arch/x86/include/smm.h index 320bac6..eec1a36 100644 --- a/src/arch/x86/include/smm.h +++ b/src/arch/x86/include/smm.h @@ -11,9 +11,8 @@ * GNU General Public License for more details. */ -#include <stddef.h> -#include <stdint.h> #include <cpu/x86/smm.h> +#include <types.h> /* * calls into SMM with the given cmd and subcmd in eax, and arg in ebx diff --git a/src/commonlib/storage/bouncebuf.h b/src/commonlib/storage/bouncebuf.h index 3e702fa..d43df47 100644 --- a/src/commonlib/storage/bouncebuf.h +++ b/src/commonlib/storage/bouncebuf.h @@ -17,9 +17,7 @@ #ifndef __COMMONLIB_STORAGE_BOUNCEBUF_H__ #define __COMMONLIB_STORAGE_BOUNCEBUF_H__ -#include <stddef.h> -#include <stdint.h> -#include <stdlib.h> +#include <types.h> /* * GEN_BB_READ -- Data are read from the buffer eg. by DMA hardware. diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 1d7e7ee..a2b10cd 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -19,8 +19,7 @@ #include <delay.h> #include <device/pnp.h> #include <ec/google/common/mec.h> -#include <stdint.h> -#include <stdlib.h> +#include <types.h> #include "chip.h" #include "ec.h" diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c index 28c2603..f5e01f0 100644 --- a/src/ec/google/chromeec/vstore.c +++ b/src/ec/google/chromeec/vstore.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <string.h> -#include <stdlib.h> +#include <types.h> + #include "ec.h" #include "ec_commands.h" diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 09211f8..478d00d 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -21,8 +21,7 @@ #include <device/pnp.h> #include <ec/acpi/ec.h> #include <pc80/keyboard.h> -#include <stdint.h> -#include <stdlib.h> +#include <types.h> #include "commands.h" #include "ec.h" diff --git a/src/include/device/i2c_bus.h b/src/include/device/i2c_bus.h index 5302d20..35c2c05 100644 --- a/src/include/device/i2c_bus.h +++ b/src/include/device/i2c_bus.h @@ -14,10 +14,9 @@ #ifndef _DEVICE_I2C_BUS_H_ #define _DEVICE_I2C_BUS_H_ -#include <stdlib.h> -#include <stdint.h> #include <device/i2c.h> #include <device/device.h> +#include <types.h> /* I2C bus operation for ramstage drivers */ struct i2c_bus_operations { diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index 8ca3bbd..1a0abde 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -19,9 +19,9 @@ #include <bootmem.h> #include <cbmem.h> #include <device/resource.h> -#include <stdlib.h> #include <symbols.h> #include <assert.h> +#include <types.h> static int initialized; static int table_written; diff --git a/src/lib/fit.c b/src/lib/fit.c index 831e518..5858241 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -19,10 +19,9 @@ #include <console/console.h> #include <ctype.h> #include <endian.h> -#include <stdint.h> #include <bootmem.h> -#include <stdlib.h> #include <string.h> +#include <types.h> #include <program_loading.h> #include <memrange.h> #include <fit.h> diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 6fd48d5..9cd4f37 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -21,7 +21,7 @@ #include <cbmem.h> #include <imd.h> #include <lib.h> -#include <stdlib.h> +#include <types.h> /* The program loader passes on cbmem_top and the program entry point has to fill in the _cbmem_top_ptr symbol based on the calling arguments. */ diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 56529d2..6b5874c 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -15,12 +15,11 @@ #include <assert.h> #include <cbmem.h> #include <cbfs.h> -#include <stdint.h> -#include <stdlib.h> #include <string.h> #include <console/console.h> #include <program_loading.h> #include <rmodule.h> +#include <types.h> /* Change this define to get more verbose debugging for module loading. */ #define PK_ADJ_LEVEL BIOS_NEVER diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index c55e734..69e1778 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -21,10 +21,10 @@ #include <console/console.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> -#include <stdlib.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/dimm_spd.h> #include <amdblocks/car.h> +#include <types.h> #include "chip.h" diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c index 2ba25a2..7a89530 100644 --- a/src/soc/cavium/cn81xx/spi.c +++ b/src/soc/cavium/cn81xx/spi.c @@ -25,8 +25,8 @@ #include <soc/clock.h> #include <spi-generic.h> #include <spi_flash.h> -#include <stdlib.h> #include <timer.h> +#include <types.h> union cavium_spi_cfg { u64 u; diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 5c29add..1906fb3 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -25,7 +25,7 @@ #include <soc/pci_devs.h> #include <spi_flash.h> #include <spi-generic.h> -#include <stdlib.h> +#include <types.h> /* * Get the FAST_SPIBAR. diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index f90a165..8e6484f 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -22,8 +22,7 @@ #include <soc/iomap.h> #include <soc/me.h> #include <soc/pci_devs.h> -#include <stdint.h> -#include <stdlib.h> +#include <types.h> /* HFSTS1[3:0] Current Working State Values */ diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index e35f888..bdcec1f 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -21,8 +21,8 @@ #include <soc/clk.h> #include <soc/gpio.h> #include <soc/spi.h> -#include <stdlib.h> #include <symbols.h> +#include <types.h> #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI # define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "EXYNOS_SPI: " x) diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 1903f6b..2f2ba5a 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -20,9 +20,9 @@ #include <soc/cpu.h> #include <soc/spi.h> #include <spi-generic.h> -#include <stdlib.h> #include <string.h> #include <symbols.h> +#include <types.h> #define EXYNOS_SPI_MAX_TRANSFER_BYTES (65535) diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 60a8a13..82491a6 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -17,8 +17,7 @@ #include <console/console.h> #include <soc/clock.h> #include <soc/addressmap.h> -#include <stdlib.h> -#include <stdint.h> +#include <types.h> // 33.33 Mhz after reset #define FU540_BASE_FQY 33330 -- To view, visit https://review.coreboot.org/c/coreboot/+/37364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e0c2a4dfaa5b1cde0dd4a9e213be0b383e1017f Gerrit-Change-Number: 37364 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Add missing include <stddef.h>
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37365 ) Change subject: src: Add missing include <stddef.h> ...................................................................... src: Add missing include <stddef.h> Also use <types.h> when <stdint.h> and <stddef.h> are needed. Some uneeded include <stdlib.h> removes. Change-Id: I619ae22679d86a4d0b565a3717f0fb9aa487eb8b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/fit_payload.c M src/arch/x86/acpi_device.c M src/arch/x86/include/arch/early_variables.h M src/commonlib/mem_pool.c M src/commonlib/region.c M src/lib/coreboot_table.c M src/security/tpm/tspi/tspi.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/intel/skylake/pmutil.c M src/soc/qualcomm/ipq40xx/spi.c 11 files changed, 15 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37365/1 diff --git a/src/arch/arm64/fit_payload.c b/src/arch/arm64/fit_payload.c index 4ade1c7..c9023a4 100644 --- a/src/arch/arm64/fit_payload.c +++ b/src/arch/arm64/fit_payload.c @@ -14,8 +14,8 @@ #include <console/console.h> #include <bootmem.h> -#include <stdlib.h> #include <program_loading.h> +#include <stddef.h> #include <string.h> #include <commonlib/compression.h> #include <commonlib/cbfs_serialized.h> diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index d367108..f0b3127 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -20,6 +20,8 @@ #if CONFIG(GENERIC_GPIO_LIB) #include <gpio.h> #endif +#include <stddef.h> +#include <stdlib.h> #define ACPI_DP_UUID "daffd814-6eba-4d8c-8a91-bc9bbf4aa301" #define ACPI_DP_CHILD_UUID "dbb8e3e6-5886-4ba6-8795-1319f52a966b" diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 7393cc9..6025dd2 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -16,7 +16,7 @@ #include <arch/symbols.h> #include <commonlib/helpers.h> -#include <stdlib.h> +#include <stddef.h> #if ENV_ROMSTAGE && CONFIG(CAR_GLOBAL_MIGRATION) diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c index 0aa821b..3040661 100644 --- a/src/commonlib/mem_pool.c +++ b/src/commonlib/mem_pool.c @@ -13,6 +13,8 @@ #include <commonlib/helpers.h> #include <commonlib/mem_pool.h> +#include <stddef.h> +#include <stdlib.h> void *mem_pool_alloc(struct mem_pool *mp, size_t sz) { diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 4a7e285..106357a 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -13,6 +13,8 @@ #include <commonlib/helpers.h> #include <commonlib/region.h> +#include <stddef.h> +#include <stdlib.h> #include <string.h> int region_is_subregion(const struct region *p, const struct region *c) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 7245a63..edd5c47 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -27,11 +27,11 @@ #include <boardid.h> #include <device/device.h> #include <fmap.h> -#include <stdlib.h> #include <cbfs.h> #include <cbmem.h> #include <bootmem.h> #include <bootsplash.h> +#include <stddef.h> #include <spi_flash.h> #include <security/vboot/misc.h> #include <security/vboot/vbnv_layout.h> diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 966b8b7..0ae1d84 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -19,12 +19,12 @@ #include <console/console.h> #include <security/tpm/tspi.h> #include <security/tpm/tss.h> -#include <stdlib.h> #if CONFIG(VBOOT) #include <vb2_api.h> #include <vb2_sha.h> #include <assert.h> #endif +#include <stddef.h> #if CONFIG(TPM1) static uint32_t tpm1_invoke_state_machine(void) diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 720e7c4..9b4a42b 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -7,8 +7,9 @@ #include <commonlib/iobuf.h> #include <console/console.h> -#include <stdlib.h> +#include <stddef.h> #include <string.h> +#include <types.h> #include "tss_marshaling.h" #include <security/tpm/tss/vendor/cr50/cr50.h> diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 044a1b0..b988926 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -35,8 +35,8 @@ #include <soc/southbridge.h> #include <soc/pci_devs.h> #include <soc/iomap.h> +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <arch/bert_storage.h> diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index eb36e48..89582f9 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -29,7 +29,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/tco.h> -#include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -38,6 +37,7 @@ #include <soc/pmc.h> #include <soc/smbus.h> #include <security/vboot/vbnv.h> +#include <stddef.h> #include "chip.h" diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index b68e1cb..72a5b9d 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -33,7 +33,7 @@ #include <gpio.h> #include <soc/iomap.h> #include <soc/spi.h> -#include <stdlib.h> +#include <stddef.h> static const struct blsp_spi spi_reg[] = { /* BLSP0 registers for SPI interface */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I619ae22679d86a4d0b565a3717f0fb9aa487eb8b Gerrit-Change-Number: 37365 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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