Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33777
Change subject: asus/am1i-a: set VGA_BIOS_ID to 1002,9830 instead of default 1002,9836
......................................................................
asus/am1i-a: set VGA_BIOS_ID to 1002,9830 instead of default 1002,9836
The majority of Socket AM1 APUs [1] - three out of five (three Athlons, the
most powerful for this socket) - have the integrated VGA with 1002,9830 ID,
while only one Sempron has 1002,9836. Set the default to more common one.
[1] https://en.wikipedia.org/wiki/List_of_AMD_accelerated_processing_units#%22K…
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd
---
M src/mainboard/asus/am1i-a/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/33777/1
diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig
index d50edbe..42ab5c6 100644
--- a/src/mainboard/asus/am1i-a/Kconfig
+++ b/src/mainboard/asus/am1i-a/Kconfig
@@ -44,7 +44,7 @@
config VGA_BIOS_ID
string
- default "1002,9836"
+ default "1002,9830"
config HUDSON_LEGACY_FREE
bool
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd
Gerrit-Change-Number: 33777
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33872
Change subject: MAINTAINERS: Add myself as a maintainer for Lenovo G505S and ASUS AM1I-A
......................................................................
MAINTAINERS: Add myself as a maintainer for Lenovo G505S and ASUS AM1I-A
These are the boards I have and currently working on.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: I874770813a96ecd27138b02a16f6bc737572351a
---
M MAINTAINERS
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/33872/1
diff --git a/MAINTAINERS b/MAINTAINERS
index 73ca6df..14d075a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -164,6 +164,11 @@
S: Maintained
F: src/mainboard/lenovo/
+LENOVO G505S MAINBOARD
+M: Mike Banon <mikebdp2(a)gmail.com>
+S: Maintained
+F: src/mainboard/lenovo/g505s
+
APPLE MAINBOARDS
M: Evgeny Zinoviev <me(a)ch1p.io>
S: Maintained
@@ -333,6 +338,11 @@
S: Maintained
F: src/mainboard/asrock/h81m-hds/
+ASUS AM1I-A MAINBOARD
+M: Mike Banon <mikebdp2(a)gmail.com>
+S: Maintained
+F: src/mainboard/asus/am1i-a
+
ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS
M: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
S: Supported
--
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Gerrit-Branch: master
Gerrit-Change-Id: I874770813a96ecd27138b02a16f6bc737572351a
Gerrit-Change-Number: 33872
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
Ravi Chandra Sadineni has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34801 )
Change subject: chromeec: Depend on events_copy_b to identify the wake source.
......................................................................
chromeec: Depend on events_copy_b to identify the wake source.
Using google_chromeec_get_event() clears the event too. Thus if the
kernel has to identify the wake source, it has no way to do that. Thus
instead depend on events_copy_b to log the wake source. Please look at
go/hostevent-refactor for more info.
BUG=b:133262012
BRANCH=None
TEST=Hack hatch bios and make sure hostevent log is correct.
Change-Id: I39caae2689e0c2a7bec16416978877885a9afc6c
Signed-off-by: Ravi Chandra Sadineni <ravisadineni(a)chromium.org>
---
M src/ec/google/chromeec/ec.c
1 file changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/34801/1
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 5a2630e..9ba9b1b 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -428,7 +428,8 @@
void google_chromeec_log_events(uint64_t mask)
{
- u8 event;
+ u64 events;
+ int i;
uint64_t wake_mask;
bool restore_wake_mask = false;
@@ -445,11 +446,14 @@
restore_wake_mask = true;
}
- while ((event = google_chromeec_get_event()) != 0) {
- if (EC_HOST_EVENT_MASK(event) & mask)
- elog_add_event_byte(ELOG_TYPE_EC_EVENT, event);
+ events = google_chromeec_get_events_b() & mask;
+ for (i = 0; i < sizeof(events) * 8; i++) {
+ if (EC_HOST_EVENT_MASK(i) & events)
+ elog_add_event_byte(ELOG_TYPE_EC_EVENT, i);
}
+ google_chromeec_clear_events_b(events);
+
if (restore_wake_mask)
google_chromeec_set_wake_mask(wake_mask);
}
@@ -467,10 +471,6 @@
/* Disable SMI and wake events. */
google_chromeec_set_smi_mask(0);
- /* Clear pending events. */
- while (google_chromeec_get_event() != 0)
- ;
-
/* Restore SCI event mask. */
google_chromeec_set_sci_mask(info->sci_events);
--
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Gerrit-Branch: master
Gerrit-Change-Id: I39caae2689e0c2a7bec16416978877885a9afc6c
Gerrit-Change-Number: 34801
Gerrit-PatchSet: 1
Gerrit-Owner: Ravi Chandra Sadineni <ravisadineni(a)chromium.org>
Gerrit-MessageType: newchange
Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36034 )
Change subject: soc/intel/common/block/timer: Add config to enable/disable PM timer support
......................................................................
soc/intel/common/block/timer: Add config to enable/disable PM timer support
Added config to support PM Timer enable/disable.
BUG=none
TEST=none
Change-Id: I42fcf23523889d47f0491fad662ca6b3587ab348
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
---
M src/soc/intel/common/block/timer/Kconfig
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/36034/1
diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig
index a214ef0..4e5f03c 100644
--- a/src/soc/intel/common/block/timer/Kconfig
+++ b/src/soc/intel/common/block/timer/Kconfig
@@ -12,3 +12,9 @@
the FSP Integration guide Legacy 8254 timer clock gating UPD needs
to be disabled in order to boot SeaBIOS or run OpRom,
but should otherwise be enabled.
+
+config USE_ACPI_PM_TIMER
+ bool "Use ACPI PM Timer"
+ help
+ This disables the ACPI PM Timer by default.
+
--
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Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com>
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