coreboot-gerrit November 2019

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Change in ...coreboot[master]: src/cpu/x86 STM Support
by Name of user not set (Code Review) 20 Dec '19

20 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33236 Change subject: src/cpu/x86 STM Support ...................................................................... src/cpu/x86 STM Support STM initialization Change-Id: I3a0adcefc0f6e22a9da5fe53952481a77737e5eb --- M src/cpu/x86/mp_init.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33236/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3889c7d..881d8a2 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -37,8 +37,12 @@ #include <symbols.h> #include <thread.h> +#include <security/intel/stm/StmApi.h> + #define MAX_APIC_IDS 256 +extern int LoadStmImage(uint32_t mseg); + struct mp_callback { void (*func)(void *); void *arg; @@ -823,6 +827,10 @@ { size_t smm_save_state_size = mp_state.smm_save_state_size; +#ifdef CONFIG_STM + uint32_t mseg; +#endif + /* Do nothing if SMM is disabled.*/ if (!is_smm_enabled()) return; @@ -839,6 +847,14 @@ printk(BIOS_ERR, "Unable to install SMM permanent handler.\n"); smm_disable(); } +#ifdef CONFIG_STM + + /* Calculate mseg location*/ + mseg = mp_state.perm_smbase + (mp_state.perm_smsize - CONFIG_MSEG_SIZE); + + /* Load the STM into the MSEG */ + LoadStmImage(mseg); +#endif /* Ensure the SMM handlers hit DRAM before performing first SMI. */ wbinvd(); @@ -1023,6 +1039,15 @@ if (ops->get_smm_info != NULL) ops->get_smm_info(&state->perm_smbase, &state->perm_smsize, &state->smm_save_state_size); +#ifdef CONFIG_STM + + /* Currently, the CPU SMM save state size is based on a simplistic + * algorithm. (set it to 1K) + * note: In the future, this will need to handle newer x86 processors + * that require 32k alignment of the save state on 32K boundries.*/ + state->smm_save_state_size += (sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR) + 0x1000) & 0xfffff000; + +#endif /* CONFIG_STM */ /* * Default to smm_initiate_relocation() if trigger callback isn't -- To view, visit https://review.coreboot.org/c/coreboot/+/33236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a0adcefc0f6e22a9da5fe53952481a77737e5eb Gerrit-Change-Number: 33236 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

4 25

Change in ...coreboot[master]: cpu/x86/smm/ STM Support
by Name of user not set (Code Review) 20 Dec '19

20 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33235 Change subject: cpu/x86/smm/ STM Support ...................................................................... cpu/x86/smm/ STM Support SMI Handler modifications needed to setup the STM data structures Change-Id: I935cd5a8bc0bf293240324c2e3a04a655d44c69f --- M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 4 files changed, 92 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/33235/1 diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index f9af965..26ddd66 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -18,6 +18,15 @@ #include <cpu/x86/smm.h> #include <rmodule.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/cache.h> + +#include <security/intel/stm/StmApi.h> +#include <security/intel/stm/StmPlatformResource.h> +#include <arch/acpi.h> +#include <lib.h> +#include <security/intel/stm/SmmStm.h> + #if IS_ENABLED(CONFIG_SPI_FLASH_SMM) #include <spi-generic.h> #endif @@ -116,6 +125,10 @@ return base; } +#ifdef CONFIG_STM + static uint32_t MsegInit = 0; // used for STM/mseg initialization +#endif + asmlinkage void smm_handler_start(void *arg) { const struct smm_module_params *p; @@ -123,7 +136,16 @@ int cpu; uintptr_t actual_canary; uintptr_t expected_canary; +#ifdef CONFIG_STM + int MsegInit2 = 1; // assume that the STM has been set + /* this initialzation strategy works on the assumption that all + * processors will enter SMM at generally the same time. + * If a single processor lags then a locking/counting scheme will + * need to be implemented. */ + if (MsegInit == 0) + MsegInit2 = 0; +#endif p = arg; runtime = p->runtime; cpu = p->cpu; @@ -140,9 +162,33 @@ "Invalid CPU number assigned in SMM stub: %d\n", cpu); return; } +#ifdef CONFIG_STM + if (MsegInit == 0) { + + /* Initialize the MSEG base address for each logical processor + * and indicate that there is an STM present */ + msr_t InitMseg; + msr_t MsegChk; + + InitMseg.lo = smm_runtime->mseg | IA32_SMM_MONITOR_VALID; + InitMseg.hi = 0; + + wrmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX, InitMseg); + + MsegChk = rdmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX); + console_init(); + + printk(BIOS_DEBUG, "MSEG Initialized (%d) 0x%08x 0x%08x\n", + cpu, MsegChk.hi, MsegChk.lo); + } + +#endif /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { +#ifdef CONFIG_STM + void *smbase = (void *) smm_runtime->smbase; +#endif /* For security reasons we don't release the other CPUs * until the CPU with the lock is actually done */ while (smi_handler_status == SMI_LOCKED) { @@ -150,13 +196,35 @@ ".byte 0xf3, 0x90\n" /* PAUSE */ ); } +#ifdef CONFIG_STM + if (MsegInit2 == 0) { + + /* Setup an SMM Descriptor for this logical processor */ + SetupSmmDescriptor(smbase, smm_runtime->save_state_size, cpu, smm_runtime->start32_offset); + MsegInit2 = 1; + } +#endif + wbinvd(); return; } +#ifdef CONFIG_STM + + if (MsegInit == 0) { + void *smbase = (void *) smm_runtime->smbase; + + AddResourcesCmd(); + + /* Setup an SMM Descriptor for this logical processor */ + + SetupSmmDescriptor(smbase, smm_runtime->save_state_size, cpu, + smm_runtime->start32_offset); + MsegInit = 1; // flag that we are done + wbinvd(); // force the tables to memory + } +#endif smi_backup_pci_address(); - console_init(); - printk(BIOS_SPEW, "\nSMI# #%d\n", cpu); /* Allow drivers to initialize variables in SMM context. */ diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 6c16645..4f15fdd 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -18,6 +18,7 @@ #include <cpu/x86/smm.h> #include <cpu/x86/cache.h> #include <console/console.h> +#include <security/intel/stm/SmmStm.h> #define FXSAVE_SIZE 512 @@ -268,6 +269,9 @@ stub_params->fxsave_area_size = FXSAVE_SIZE; stub_params->runtime.smbase = (uintptr_t)smbase; stub_params->runtime.save_state_size = params->per_cpu_save_state_size; + + /* mseg is after the smi handler */ + stub_params->runtime.mseg = (uint32_t) params->stack_top; /* Initialize the APIC id to CPU number table to be 1:1 */ for (i = 0; i < params->num_concurrent_stacks; i++) @@ -354,7 +358,13 @@ /* Stacks start at the top of the region. */ base = smram; + +#ifdef CONFIG_STM + base += size - CONFIG_MSEG_SIZE; // take out the mseg +#else base += size; +#endif + params->stack_top = base; /* SMM module starts at offset SMM_DEFAULT_SIZE with the load alignment diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 59eb27c..3817424 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -46,6 +46,11 @@ .long 0 save_state_size: .long 0 +mseg: +.long 0 +/* allows the STM to bring up SMM in 32-bit mode*/ +start32_offset: +.long smm_trampoline32 - _start /* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ @@ -92,6 +97,10 @@ /* gdt selector 0x10, flat data segment */ .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 + + /* gdt selector 0x18 tr segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x8b, 0x80, 0x00 smm_relocate_gdt_end: .align 4 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 576449d..b2d7445 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -512,6 +512,9 @@ struct smm_runtime { u32 smbase; u32 save_state_size; + u32 mseg; + /* used so that the STM can start the SMI handler in 32bit mode */ + u32 start32_offset; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader -- To view, visit https://review.coreboot.org/c/coreboot/+/33235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I935cd5a8bc0bf293240324c2e3a04a655d44c69f Gerrit-Change-Number: 33235 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

5 25

Change in coreboot[master]: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
by huayang duan (Code Review) 20 Dec '19

20 Dec '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36990 ) Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute ...................................................................... soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute the delay cell result should using the ddr clock pll rate for compute, should not div 2 more. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1 --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 1 file changed, 14 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36990/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 1dc1ca5..c61e237 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -1588,18 +1588,24 @@ struct per_byte_dly center_dly[DQS_NUMBER]; u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH]; + + /* + * The clock rate should be (data rate/2 - 4), + * and the 4MHz is introduced to reduce interference from + * RF peripherals like modem, WiFi, BlueTooth. + */ switch (freq_group) { case LP4X_DDR1600: - clock_rate = 800; + clock_rate = 796; break; case LP4X_DDR2400: - clock_rate = 1200; + clock_rate = 1196; break; case LP4X_DDR3200: - clock_rate = 1600; + clock_rate = 1596; break; case LP4X_DDR3600: - clock_rate = 1866; + clock_rate = 1792; break; default: die("Invalid DDR frequency group %u\n", freq_group); @@ -1612,7 +1618,7 @@ use_delay_cell = 0; if (fast_calib && bypass_tx) { - dramc_dbg("bypass TX\n"); + dramc_dbg("bypass TX, clock_rate:%d\n", clock_rate); for (u8 byte = 0; byte < DQS_NUMBER; byte++) { center_dly[byte].min_center = params->tx_center_min[chn][rank][byte]; center_dly[byte].max_center = params->tx_center_max[chn][rank][byte]; @@ -1645,8 +1651,10 @@ tune_diff = vref_dly[index].win_center - center_dly[byte].min_center; dq_delay_cell[index] = ((tune_diff * 100000000) / - (clock_rate / 2 * 64)) / dly_cell_unit; + (clock_rate * 64)) / dly_cell_unit; byte_dly_cell[byte] |= (dq_delay_cell[index] << (bit * 4)); + dramc_show("u1DelayCellOfst[%d]=%d cells (%d PI)\n", + index, dq_delay_cell[index], tune_diff); } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/36990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1 Gerrit-Change-Number: 36990 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

5 30

Change in coreboot[master]: arch/x86: Drop romcc bootblock
by Arthur Heymans (Code Review) 20 Dec '19

20 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37335 ) Change subject: arch/x86: Drop romcc bootblock ...................................................................... arch/x86: Drop romcc bootblock Change-Id: I79accbe1d5a554fea75fbd866995f385f718421a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Makefile.inc D src/arch/x86/bootblock.ld D src/arch/x86/bootblock_normal.c D src/arch/x86/bootblock_romcc.S D src/arch/x86/bootblock_simple.c M src/arch/x86/car.ld M src/arch/x86/memlayout.ld M src/lib/Makefile.inc 8 files changed, 0 insertions(+), 242 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/37335/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 423c351..f553159 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -116,8 +116,6 @@ bootblock-y += id.S $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) - bootblock-y += bootblock_crt0.S ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) @@ -128,59 +126,6 @@ bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S -else # ROMCC_BOOTBLOCK - -# x86-specific linker flags -ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) -LDFLAGS_bootblock += -m elf_i386 --oformat elf32-i386 -else -LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64 -endif - -# Add the assembly file that pulls in the rest of the dependencies in -# the right order. Make sure the auto generated bootblock.inc is a proper -# dependency. Make the same true for the linker sript. -bootblock-y += bootblock_romcc.S -bootblock-y += walkcbfs.S -$(call src-to-obj,bootblock,$(dir)/bootblock_romcc.S): $(objgenerated)/bootblock.inc - -bootblock-y += bootblock.ld -$(call src-to-obj,bootblock,$(dir)/bootblock.ld): $(objgenerated)/bootblock.ld - -bootblock_romccflags := -mcpu=i386 -O2 -D__BOOTBLOCK__ -ifeq ($(CONFIG_SSE),y) -bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__BOOTBLOCK__ -endif - -# This is a hack in case there are no per chipset linker files. -$(objgenerated)/empty: build-dirs - touch $@ - -$(objgenerated)/bootblock.ld: $$(filter-out $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld), $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty - @printf " GEN $(subst $(obj)/,,$(@))\n" - cat $^ >> $@.tmp - mv $@.tmp $@ - --include $(objgenerated)/bootblock.inc.d -$(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) -# The open quote in the subst messes with syntax highlighting. Fix it - ") - @printf " ROMCC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ - $< > $(objgenerated)/bootblock.inc.d - $(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \ - $< -o $(objgenerated)/bootblock_romcc.c - $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ - -# bootblock.ld is part of $(bootblock-objs) -$(objcbfs)/bootblock.debug: $$(bootblock-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ - $(filter-out %.ld,$(bootblock-objs)) \ - -T $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld) - -endif # ROMCC_BOOTBLOCK - - endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ############################################################################### @@ -223,9 +168,7 @@ romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c # gdt_init.S is included by entry32.inc when romstage is the first C # environment. -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) romstage-y += gdt_init.S -endif romstage-y += cbmem.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld deleted file mode 100644 index 10cd700..0000000 --- a/src/arch/x86/bootblock.ld +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/x86/failover.ld> -#include <cpu/x86/16bit/entry16.ld> -#include <cpu/x86/16bit/reset16.ld> -#include <arch/x86/id.ld> -#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) -#include <cpu/intel/fit/fit.ld> -#endif - -/* Include generated .ld files. */ -#include <generated/bootblock.ld> diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c deleted file mode 100644 index 905ecb2..0000000 --- a/src/arch/x86/bootblock_normal.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <smp/node.h> -#include <arch/bootblock_romcc.h> -#include <pc80/mc146818rtc.h> -#include <halt.h> - -static const char *get_fallback(const char *stagelist) -{ - while (*stagelist) - stagelist++; - return ++stagelist; -} - -static void main(unsigned long bist) -{ - u8 boot_mode; - const char *default_filenames = - "normal/romstage\0fallback/romstage"; - - if (boot_cpu()) { - bootblock_mainboard_init(); - - sanitize_cmos(); - - boot_mode = do_normal_boot(); - } else { - - /* Questionable single byte read from CMOS. - * Do not add any other CMOS access in the - * bootblock for AP CPUs. - */ - boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE)); - } - - char *normal_candidate = (char *)walkcbfs("coreboot-stages"); - - if (!normal_candidate) - normal_candidate = default_filenames; - - unsigned long entry; - - if (boot_mode) { - entry = findstage(normal_candidate); - if (entry) - call(entry, bist); - } - - entry = findstage(get_fallback(normal_candidate)); - if (entry) - call(entry, bist); - - /* duh. we're stuck */ - halt(); -} diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S deleted file mode 100644 index 7d6f42f..0000000 --- a/src/arch/x86/bootblock_romcc.S +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * This is the original bootblock used by coreboot on x86 systems. It contains - * a monolithic code flow, assembled from the following stages: - * - reset16.inc: the reset vector - * - entry16.inc: protected mode setup - * - entry32.inc: segment descriptor setup - * - timestamp.inc: store TSC in MMX registers - * - generated/bootblock.inc: ROMCC part of the bootblock - * - * This is used on platforms which select ROMCC_BOOTBLOCK, and it - * tries to do the absolute minimum before walking CBFS and jumping to romstage. - * - * This file assembles the bootblock program by the order of the includes. Thus, - * it's extremely important that one pays very careful attention to the order - * of the includes. - */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/16bit/entry16.inc> -#include <cpu/x86/16bit/reset16.inc> -#include <cpu/x86/32bit/entry32.inc> - -#include <arch/x86/timestamp.inc> - -#if CONFIG(SSE) -#include <cpu/x86/sse_enable.inc> -#endif - -/* - * This bootblock.inc file is generated by ROMCC. The above program flow - * falls through to this point. ROMCC assumes the last function it parsed - * is the main function and it places its instructions at the beginning of - * the generated file. Moreover, any library/common code needed in bootblock - * needs to come after bootblock.inc. - */ -#include <generated/bootblock.inc> diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c deleted file mode 100644 index d161435..0000000 --- a/src/arch/x86/bootblock_simple.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <smp/node.h> -#include <arch/bootblock_romcc.h> -#include <pc80/mc146818rtc.h> -#include <halt.h> - -static void main(unsigned long bist) -{ - if (boot_cpu()) { - bootblock_mainboard_init(); - - sanitize_cmos(); -#if CONFIG(CMOS_POST) - cmos_post_init(); -#endif - } - - const char *target1 = "fallback/romstage"; - unsigned long entry; - entry = findstage(target1); - if (entry) - call(entry, bist); - halt(); -} diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 483a908..05ab57f 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -36,11 +36,9 @@ /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ -#if !CONFIG(ROMCC_BOOTBLOCK) _car_stack = .; . += CONFIG_DCACHE_BSP_STACK_SIZE; _ecar_stack = .; -#endif /* The pre-ram cbmem console as well as the timestamp region are fixed * in size. Therefore place them above the car global section so that * multiple stages (romstage and verstage) have a consistent @@ -90,10 +88,6 @@ _ebss = .; _car_unallocated_start = .; -#if CONFIG(ROMCC_BOOTBLOCK) - _car_stack = .; - _ecar_stack = _car_region_end; -#endif _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); } @@ -121,6 +115,4 @@ #if CONFIG(PAGING_IN_CACHE_AS_RAM) _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); #endif -#if !CONFIG(ROMCC_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); -#endif diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index f8ae9f3..1e401a5 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -49,7 +49,6 @@ #include EARLY_MEMLAYOUT #elif ENV_BOOTBLOCK - /* arch/x86/bootblock.ld contains the logic for the ROMCC_BOOTBLOCK linking. */ BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index b444ea3..748f55a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -268,9 +268,7 @@ postcar-$(CONFIG_GENERIC_UDELAY) += timer.c # Use program.ld for all the platforms which use C fo the bootblock. -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += program.ld -endif decompressor-y += program.ld postcar-y += program.ld -- To view, visit https://review.coreboot.org/c/coreboot/+/37335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79accbe1d5a554fea75fbd866995f385f718421a Gerrit-Change-Number: 37335 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: [WIP] Move AGESA and apufw higher in CBFS
by Kyösti Mälkki (Code Review) 19 Dec '19

19 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31076 Change subject: [WIP] Move AGESA and apufw higher in CBFS ...................................................................... [WIP] Move AGESA and apufw higher in CBFS Increases continuous free space in CBFS from 5.8 MiB to 7.1 MiB. Will not work with released binaryPI build from 3rdparty/blobs. Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc M src/vendorcode/amd/pi/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31076/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 81fe7ff..57bad38 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -75,7 +75,7 @@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) else -HUDSON_FWM_POSITION=0xfff20000 +HUDSON_FWM_POSITION=0xfffa0000 endif ifeq ($(CONFIG_HUDSON_PSP), y) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index f463b7d..3dc7052 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -96,7 +96,7 @@ config AGESA_BINARY_PI_LOCATION hex "AGESA PI binary address in ROM" - default 0xFFE00000 + default 0xFFF00000 depends on !AGESA_BINARY_PI_AS_STAGE help Specify the ROM address at which to store the binary Platform -- To view, visit https://review.coreboot.org/c/coreboot/+/31076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb Gerrit-Change-Number: 31076 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: include/cpu/x86: Add STM Support
by Name of user not set (Code Review) 19 Dec '19

19 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33985 Change subject: include/cpu/x86: Add STM Support ...................................................................... include/cpu/x86: Add STM Support Addtions to cpu/x86 include for STM support. Change-Id: I2b8e68b2928aefc7996b6a9560c52f71c7c0e1d0 --- M src/include/cpu/x86/msr.h M src/include/cpu/x86/smm.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33985/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index d1e9169..c9d92a7 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -30,6 +30,7 @@ #define IA32_BIOS_SIGN_ID 0x8b #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 +/* STM */ #define IA32_SMM_MONITOR_CTL_MSR 0x9B #define IA32_SMM_MONITOR_VALID (1<<0) #define IA32_MCG_CAP 0x179 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index b2d7445..3bd6e41 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -512,6 +512,7 @@ struct smm_runtime { u32 smbase; u32 save_state_size; + /* useg to get the mseg address into smm for setup */ u32 mseg; /* used so that the STM can start the SMI handler in 32bit mode */ u32 start32_offset; -- To view, visit https://review.coreboot.org/c/coreboot/+/33985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b8e68b2928aefc7996b6a9560c52f71c7c0e1d0 Gerrit-Change-Number: 33985 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

8 24

Change in coreboot[master]: {northbridge,soc,southbridge}: Get rid of wrong _ADR objects
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36318 ) Change subject: {northbridge,soc,southbridge}: Get rid of wrong _ADR objects ...................................................................... {northbridge,soc,southbridge}: Get rid of wrong _ADR objects ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: Ifb777c09aeef09a6a4cbee254b081519f5b6c457 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/agesa/family14/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/northbridge.asl M src/soc/intel/broadwell/acpi/serialio.asl M src/soc/intel/fsp_broadwell_de/acpi/uncore.asl M src/southbridge/intel/lynxpoint/acpi/serialio.asl 5 files changed, 0 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/36318/1 diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index e95c95a..5a54874 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -18,7 +18,6 @@ External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ Device(AMRT) { diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index fe78534..208ea26 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -19,7 +19,6 @@ External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index 1b44e95..1968502 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -159,7 +159,6 @@ // Serial IO DMA Controller Name (_HID, "INTL9C60") Name (_UID, 1) - Name (_ADR, 0x00150000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -205,7 +204,6 @@ Return ("INT33C2") } Name (_UID, 1) - Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -276,7 +274,6 @@ Return ("INT33C3") } Name (_UID, 1) - Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -347,7 +344,6 @@ Return ("INT33C0") } Name (_UID, 1) - Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -403,7 +399,6 @@ Return ("INT33C1") } Name (_UID, 1) - Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -471,7 +466,6 @@ Return ("INT33C4") } Name (_UID, 1) - Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -539,7 +533,6 @@ Return ("INT33C5") } Name (_UID, 1) - Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -596,7 +589,6 @@ } Name (_CID, "PNP0D40") Name (_UID, 1) - Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () diff --git a/src/soc/intel/fsp_broadwell_de/acpi/uncore.asl b/src/soc/intel/fsp_broadwell_de/acpi/uncore.asl index 86b1410..aded1db 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi/uncore.asl +++ b/src/soc/intel/fsp_broadwell_de/acpi/uncore.asl @@ -238,7 +238,6 @@ Return (0xff) } - Name (_ADR, 0x00) Method (_STA, 0, NotSerialized) { Return (0xf) diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 9323b91..88138a1 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -125,7 +125,6 @@ // Serial IO DMA Controller Name (_HID, "INTL9C60") Name (_UID, 1) - Name (_ADR, 0x00150000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -163,7 +162,6 @@ Name (_HID, "INT33C2") Name (_CID, "INT33C2") Name (_UID, 1) - Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -245,7 +243,6 @@ Name (_HID, "INT33C3") Name (_CID, "INT33C3") Name (_UID, 1) - Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -327,7 +324,6 @@ Name (_HID, "INT33C0") Name (_CID, "INT33C0") Name (_UID, 1) - Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -365,7 +361,6 @@ Name (_HID, "INT33C1") Name (_CID, "INT33C1") Name (_UID, 1) - Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -416,7 +411,6 @@ Name (_HID, "INT33C4") Name (_CID, "INT33C4") Name (_UID, 1) - Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -467,7 +461,6 @@ Name (_HID, "INT33C5") Name (_CID, "INT33C5") Name (_UID, 1) - Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -505,7 +498,6 @@ Name (_HID, "INT33C6") Name (_CID, "PNP0D40") Name (_UID, 1) - Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () -- To view, visit https://review.coreboot.org/c/coreboot/+/36318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb777c09aeef09a6a4cbee254b081519f5b6c457 Gerrit-Change-Number: 36318 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 11

Change in ...coreboot[master]: mainboard/lenovo: remove stdlib.h when unused
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33901 Change subject: mainboard/lenovo: remove stdlib.h when unused ...................................................................... mainboard/lenovo: remove stdlib.h when unused Change-Id: I6af1d44f9a05c153b6a355318a39adc9a3d6c0c9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/g505s/BiosCallOuts.c M src/mainboard/lenovo/g505s/buildOpts.c 2 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/33901/1 diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c index 2b1ac04..afa2fce 100644 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c @@ -16,10 +16,8 @@ #include <AGESA.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> - #include <southbridge/amd/agesa/hudson/imc.h> #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index c3e40ce..559e1a6 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -27,8 +27,6 @@ #include "mainboard.h" -#include <stdlib.h> - #include <vendorcode/amd/agesa/f15tn/AGESA.h> /* Include the files that instantiate the configuration definitions. */ @@ -43,7 +41,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE -- To view, visit https://review.coreboot.org/c/coreboot/+/33901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6af1d44f9a05c153b6a355318a39adc9a3d6c0c9 Gerrit-Change-Number: 33901 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: src: Remove unused 'include <arch/cpu.h>'
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36080 ) Change subject: src: Remove unused 'include <arch/cpu.h>' ...................................................................... src: Remove unused 'include <arch/cpu.h>' Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpi_s3.c M src/arch/x86/include/arch/exception.h M src/arch/x86/include/arch/romstage.h M src/arch/x86/include/arch/stages.h M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/haswell.h M src/cpu/x86/lapic/apic_timer.c M src/device/oprom/realmode/x86.h M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/include/fsp/util.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/include/bootblock_common.h M src/include/console/console.h M src/include/cpu/amd/car.h M src/include/cpu/x86/mtrr.h M src/include/cpu/x86/smm.h M src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c M src/soc/imgtec/pistachio/bootblock.c M src/soc/imgtec/pistachio/monotonic_timer.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/quark/include/soc/ramstage.h M src/soc/intel/quark/memmap.c M src/soc/samsung/exynos5420/smp.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 35 files changed, 0 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36080/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 52f8a20..844364a 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -14,7 +14,6 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <fallback.h> diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h index df6f9e5..167fdb1 100644 --- a/src/arch/x86/include/arch/exception.h +++ b/src/arch/x86/include/arch/exception.h @@ -28,7 +28,6 @@ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H -#include <arch/cpu.h> #if CONFIG(IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE asmlinkage void exception_init(void); diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 15c93f2..86d4e63 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -14,7 +14,6 @@ #ifndef __ARCH_ROMSTAGE_H__ #define __ARCH_ROMSTAGE_H__ -#include <arch/cpu.h> #include <stddef.h> #include <stdint.h> diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 3ef3cae..ebecf51 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -14,7 +14,6 @@ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H -#include <arch/cpu.h> asmlinkage void copy_and_run(void); diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 94e5d36..7653753 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -12,7 +12,6 @@ */ #include <stdint.h> -#include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4c67ba8..723e2fc 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -15,7 +15,6 @@ #ifndef _CPU_INTEL_HASWELL_H #define _CPU_INTEL_HASWELL_H -#include <arch/cpu.h> /* Haswell CPU types */ #define HASWELL_FAMILY_MOBILE 0x306c0 diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 58836b5..0c53d8c 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <delay.h> #include <thread.h> -#include <arch/cpu.h> #include <arch/early_variables.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> diff --git a/src/device/oprom/realmode/x86.h b/src/device/oprom/realmode/x86.h index a68b50e..ee14a87 100644 --- a/src/device/oprom/realmode/x86.h +++ b/src/device/oprom/realmode/x86.h @@ -14,7 +14,6 @@ #ifndef __DEVICE_OPROM_REALMODE_X86_H__ #define __DEVICE_OPROM_REALMODE_X86_H__ -#include <arch/cpu.h> #define REALMODE_BASE ((void *)0x600) diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 750d192..fb78d34 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <string.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <bootstate.h> #include <cbfs.h> #include <cbmem.h> diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 3d99fa6..0c1b84d 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -16,7 +16,6 @@ #ifndef FSP1_1_CAR_H #define FSP1_1_CAR_H -#include <arch/cpu.h> #include <fsp/api.h> #include <stdint.h> diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 2caceeb..d0a5b60 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -20,7 +20,6 @@ #include <stddef.h> #include <stdint.h> -#include <arch/cpu.h> #include <memory_info.h> #include <fsp/car.h> #include <fsp/util.h> diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 45b8eda..7ec748e 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -18,7 +18,6 @@ #define FSP1_1_UTIL_H #include <rules.h> -#include <arch/cpu.h> #include <fsp/api.h> /* Current users expect to get the SoC's FSP definitions by including util.h. */ #include <fsp/soc_binding.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index ef7ecd1..b781c11 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -15,7 +15,6 @@ #include <boot/coreboot_tables.h> #include <commonlib/region.h> -#include <arch/cpu.h> #include <fsp/api.h> #include <fsp/info_header.h> #include <memrange.h> diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 1081f27..8bf195f 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -16,7 +16,6 @@ #ifndef __BOOTBLOCK_COMMON_H #define __BOOTBLOCK_COMMON_H -#include <arch/cpu.h> #include <main_decl.h> #include <timestamp.h> #include <types.h> diff --git a/src/include/console/console.h b/src/include/console/console.h index 1c2a276..5169207 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -17,7 +17,6 @@ #define CONSOLE_CONSOLE_H_ #include <stdint.h> -#include <arch/cpu.h> #include <console/post_codes.h> /* console.h is supposed to provide the log levels defined in here: */ diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 359fa6b..b13995c 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -1,8 +1,6 @@ #ifndef _CPU_AMD_CAR_H #define _CPU_AMD_CAR_H -#include <arch/cpu.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); asmlinkage void *post_cache_as_ram(void); asmlinkage void cache_as_ram_new_stack(void); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 29256c8..e00ccd3 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -4,7 +4,6 @@ #include <commonlib/helpers.h> #ifndef __ASSEMBLER__ #include <cpu/x86/msr.h> -#include <arch/cpu.h> #endif /* These are the region types */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index d8b9efe..48f40be 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -16,7 +16,6 @@ #ifndef CPU_X86_SMM_H #define CPU_X86_SMM_H -#include <arch/cpu.h> #include <types.h> #define SMM_DEFAULT_BASE 0x30000 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c index ccea732..214b304 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c @@ -16,7 +16,6 @@ #include "mct_d_gcc.h" #include <stdint.h> -#include <arch/cpu.h> void _WRMSR(u32 addr, u32 lo, u32 hi) { diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c index ac4a740..f603b50 100644 --- a/src/soc/imgtec/pistachio/bootblock.c +++ b/src/soc/imgtec/pistachio/bootblock.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <arch/mmu.h> #include <assert.h> #include <stdint.h> diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c index bbcd8a1..23c1c39 100644 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ b/src/soc/imgtec/pistachio/monotonic_timer.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <device/mmio.h> #include <soc/cpu.h> #include <stdint.h> diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index e86861c..c13c914 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -17,7 +17,6 @@ #define _BAYTRAIL_ROMSTAGE_H_ #include <stdint.h> -#include <arch/cpu.h> #include <soc/mrc_wrapper.h> void mainboard_fill_mrc_params(struct mrc_params *mp); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 3c0c07f..da35601 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -20,7 +20,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index dbd2950..f68b7ce 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -18,7 +18,6 @@ #include <arch/acpi.h> #include <arch/acpigen.h> -#include <arch/cpu.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index cd37cf6..7d0270f 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -17,7 +17,6 @@ #define _BROADWELL_ROMSTAGE_H_ #include <stdint.h> -#include <arch/cpu.h> #include <soc/pei_data.h> struct chipset_power_state; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 2bebcb8..9a560ae 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -21,7 +21,6 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> -#include <arch/cpu.h> #include <arch/io.h> #include <device/pci_ops.h> #include <arch/ioapic.h> diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index e969a04..685c6bc 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -19,7 +19,6 @@ #include <arch/acpi.h> #include <arch/acpigen.h> -#include <arch/cpu.h> #include <arch/smp/mpspec.h> #include <cpu/x86/smm.h> #include <string.h> diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 59dc6be..acfe8c4 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <arch/acpi.h> #include <arch/acpigen.h> -#include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> #include <cpu/intel/speedstep.h> diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index ada8899..b6bb304 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -17,7 +17,6 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include <arch/cpu.h> #include <device/device.h> #include <soc/QuarkNcSocId.h> diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index b8b8506..60f9843 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <arch/romstage.h> #include <cbmem.h> #include <soc/reg_access.h> diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 5e16063..2c93e45 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <device/mmio.h> #include <soc/cpu.h> #include <soc/power.h> diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 5f0dd8c..266c30f 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -26,7 +26,6 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index d12c379..32dbf79 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -27,7 +27,6 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <cpu/x86/smm.h> #include <string.h> #include <cbmem.h> diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 3657656..fb1a4c2 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -27,7 +27,6 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <elog.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4b44759..660c981 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -26,7 +26,6 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/36080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Gerrit-Change-Number: 36080 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/arch: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32820 Change subject: src/arch: Use 'include <stdlib.h>' when appropriate ...................................................................... src/arch: Use 'include <stdlib.h>' when appropriate Change-Id: I79f065703b5249ca9630b06de7142bc52675076e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/mmu.c M src/arch/arm/cpu.c M src/arch/mips/mmu.c M src/arch/x86/acpigen_dsm.c M src/arch/x86/cbmem.c M src/arch/x86/mmap_boot.c 6 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32820/1 diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index ce9d3fd..f0a5fa6 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -29,12 +29,9 @@ */ #include <assert.h> -#include <stdlib.h> #include <stdint.h> #include <symbols.h> - #include <console/console.h> - #include <arch/cache.h> #if CONFIG(ARM_LPAE) diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c index fae1a37..0637bf6 100644 --- a/src/arch/arm/cpu.c +++ b/src/arch/arm/cpu.c @@ -27,7 +27,6 @@ * SUCH DAMAGE. * */ -#include <stdlib.h> #include <arch/cpu.h> /* Return the CPU struct which is at the high memory address of the stack. diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c index b144fd3..2ceb2a7 100644 --- a/src/arch/mips/mmu.c +++ b/src/arch/mips/mmu.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <stddef.h> #include <stdint.h> -#include <stdlib.h> #define MIN_PAGE_SIZE (4 * KiB) diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c index 1aab90b..8c9cd350 100644 --- a/src/arch/x86/acpigen_dsm.c +++ b/src/arch/x86/acpigen_dsm.c @@ -15,7 +15,6 @@ #include <arch/acpigen.h> #include <arch/acpigen_dsm.h> -#include <stdlib.h> /* ------------------- I2C HID DSM ---------------------------- */ diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 648633f..abd163d 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <cbmem.h> #include <arch/acpi.h> diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index abfa024..98b5643 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -15,7 +15,6 @@ #include <boot_device.h> #include <endian.h> -#include <stdlib.h> /* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ #define rom_base ((void *)(uintptr_t)(0x100000000ULL-CONFIG_ROM_SIZE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/32820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79f065703b5249ca9630b06de7142bc52675076e Gerrit-Change-Number: 32820 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019