coreboot-gerrit November 2019

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Change in coreboot[master]: util/romcc: Drop romcc support
by Arthur Heymans (Code Review) 27 Dec '19

27 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37337 ) Change subject: util/romcc: Drop romcc support ...................................................................... util/romcc: Drop romcc support Finally all boards use a GCC compiled bootblock! Change-Id: I0c9a1b19dbdc32b43875da7d685718bae9d7f5f4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D util/romcc/COPYING D util/romcc/Makefile D util/romcc/description.md D util/romcc/results/linux_test1.out D util/romcc/results/linux_test10.out D util/romcc/results/linux_test11.out D util/romcc/results/linux_test12.out D util/romcc/results/linux_test13.out D util/romcc/results/linux_test2.out D util/romcc/results/linux_test3.out D util/romcc/results/linux_test4.out D util/romcc/results/linux_test5.out D util/romcc/results/linux_test6.out D util/romcc/results/linux_test7.out D util/romcc/results/linux_test8.out D util/romcc/results/linux_test9.out D util/romcc/romcc.1 D util/romcc/romcc.c D util/romcc/test.sh D util/romcc/tests/fail_test1.c D util/romcc/tests/fail_test10.c D util/romcc/tests/fail_test11.c D util/romcc/tests/fail_test2.c D util/romcc/tests/fail_test3.c D util/romcc/tests/fail_test4.c D util/romcc/tests/fail_test5.c D util/romcc/tests/fail_test6.c D util/romcc/tests/fail_test7.c D util/romcc/tests/fail_test8.c D util/romcc/tests/fail_test9.c D util/romcc/tests/hello_world.c D util/romcc/tests/hello_world1.c D util/romcc/tests/hello_world2.c D util/romcc/tests/include/linux_console.h D util/romcc/tests/include/linux_syscall.h D util/romcc/tests/include/linuxi386_syscall.h D util/romcc/tests/ldscript.ld D util/romcc/tests/linux_console.h D util/romcc/tests/linux_syscall.h D util/romcc/tests/linux_test1.c D util/romcc/tests/linux_test10.c D util/romcc/tests/linux_test11.c D util/romcc/tests/linux_test12.c D util/romcc/tests/linux_test13.c D util/romcc/tests/linux_test2.c D util/romcc/tests/linux_test3.c D util/romcc/tests/linux_test4.c D util/romcc/tests/linux_test5.c D util/romcc/tests/linux_test6.c D util/romcc/tests/linux_test7.c D util/romcc/tests/linux_test8.c D util/romcc/tests/linux_test9.c D util/romcc/tests/linuxi386_syscall.h D util/romcc/tests/raminit_test.c D util/romcc/tests/raminit_test1.c D util/romcc/tests/raminit_test2.c D util/romcc/tests/raminit_test3.c D util/romcc/tests/raminit_test4.c D util/romcc/tests/raminit_test5.c D util/romcc/tests/raminit_test6.c D util/romcc/tests/raminit_test7.c D util/romcc/tests/simple_test.c D util/romcc/tests/simple_test1.c D util/romcc/tests/simple_test10.c D util/romcc/tests/simple_test11.c D util/romcc/tests/simple_test12.c D util/romcc/tests/simple_test13.c D util/romcc/tests/simple_test14.c D util/romcc/tests/simple_test15.c D util/romcc/tests/simple_test16.c D util/romcc/tests/simple_test17.c D util/romcc/tests/simple_test18.c D util/romcc/tests/simple_test19.c D util/romcc/tests/simple_test2.c D util/romcc/tests/simple_test20.c D util/romcc/tests/simple_test21.c D util/romcc/tests/simple_test22.c D util/romcc/tests/simple_test23.c D util/romcc/tests/simple_test24.c D util/romcc/tests/simple_test25.c D util/romcc/tests/simple_test26.c D util/romcc/tests/simple_test27.c D util/romcc/tests/simple_test28.c D util/romcc/tests/simple_test29.c D util/romcc/tests/simple_test3.c D util/romcc/tests/simple_test30.c D util/romcc/tests/simple_test31.c D util/romcc/tests/simple_test32.c D util/romcc/tests/simple_test33.c D util/romcc/tests/simple_test34.c D util/romcc/tests/simple_test35.c D util/romcc/tests/simple_test36.c D util/romcc/tests/simple_test37.c D util/romcc/tests/simple_test38.c D util/romcc/tests/simple_test39.c D util/romcc/tests/simple_test4.c D util/romcc/tests/simple_test40.c D util/romcc/tests/simple_test41.c D util/romcc/tests/simple_test43.c D util/romcc/tests/simple_test45.c D util/romcc/tests/simple_test46.c D util/romcc/tests/simple_test47.c D util/romcc/tests/simple_test48.c D util/romcc/tests/simple_test49.c D util/romcc/tests/simple_test5.c D util/romcc/tests/simple_test50.c D util/romcc/tests/simple_test51.c D util/romcc/tests/simple_test52.c D util/romcc/tests/simple_test53.c D util/romcc/tests/simple_test54.c D util/romcc/tests/simple_test55.c D util/romcc/tests/simple_test56.c D util/romcc/tests/simple_test57.c D util/romcc/tests/simple_test58.c D util/romcc/tests/simple_test59.c D util/romcc/tests/simple_test6.c D util/romcc/tests/simple_test60.c D util/romcc/tests/simple_test61.c D util/romcc/tests/simple_test62.c D util/romcc/tests/simple_test63.c D util/romcc/tests/simple_test64.c D util/romcc/tests/simple_test65.c D util/romcc/tests/simple_test66.c D util/romcc/tests/simple_test67.c D util/romcc/tests/simple_test68.c D util/romcc/tests/simple_test69.c D util/romcc/tests/simple_test7.c D util/romcc/tests/simple_test70.c D util/romcc/tests/simple_test71.c D util/romcc/tests/simple_test72.c D util/romcc/tests/simple_test73.c D util/romcc/tests/simple_test74.c D util/romcc/tests/simple_test75.c D util/romcc/tests/simple_test76.c D util/romcc/tests/simple_test77.c D util/romcc/tests/simple_test78.c D util/romcc/tests/simple_test79.c D util/romcc/tests/simple_test8.c D util/romcc/tests/simple_test80.c D util/romcc/tests/simple_test81.c D util/romcc/tests/simple_test82.c D util/romcc/tests/simple_test83.c D util/romcc/tests/simple_test84.c D util/romcc/tests/simple_test85.c D util/romcc/tests/simple_test86.c D util/romcc/tests/simple_test87.c D util/romcc/tests/simple_test9.c 147 files changed, 0 insertions(+), 50,038 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/37337/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c9a1b19dbdc32b43875da7d685718bae9d7f5f4 Gerrit-Change-Number: 37337 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: arch/x86: Drop ROMCC_BOOTBLOCK symbol
by Arthur Heymans (Code Review) 27 Dec '19

27 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37336 ) Change subject: arch/x86: Drop ROMCC_BOOTBLOCK symbol ...................................................................... arch/x86: Drop ROMCC_BOOTBLOCK symbol Change-Id: I968c4392849045cd50bfe2c83de44daba38ee245 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/Kconfig M src/console/Kconfig M src/cpu/intel/microcode/Kconfig M src/cpu/x86/Kconfig M src/mainboard/Kconfig M src/security/vboot/Kconfig 7 files changed, 2 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/37336/1 diff --git a/src/Kconfig b/src/Kconfig index 2e06299..75e9449 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1177,9 +1177,6 @@ # src/lib/bootblock.c#main() C entry point. bool -config ROMCC_BOOTBLOCK - bool - ############################################################################### # Set default values for symbols created before mainboards. This allows the # option to be displayed in the general menu, but the default to be loaded in diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index a788bc0..baea9fb 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -23,7 +23,6 @@ bool default n select ARCH_X86 - select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_32 bool @@ -47,7 +46,6 @@ bool default n select ARCH_X86 - select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_64 bool @@ -235,26 +233,6 @@ Add a spin (JMP .) in assembly_entry.S during early romstage to wait for a JTAG debugger to break into the execution sequence. -# Selecting a cbfs prefix from the bootblock is only implemented with romcc -choice - prompt "Bootblock behaviour" - default BOOTBLOCK_SIMPLE - depends on ROMCC_BOOTBLOCK - -config BOOTBLOCK_SIMPLE - bool "Always load fallback" - -config BOOTBLOCK_NORMAL - select CONFIGURABLE_CBFS_PREFIX - bool "Switch to normal if CMOS says so" - -endchoice - -config BOOTBLOCK_SOURCE - string - default "bootblock_simple.c" if BOOTBLOCK_SIMPLE - default "bootblock_normal.c" if BOOTBLOCK_NORMAL - config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" depends on BOOTBLOCK_NORMAL diff --git a/src/console/Kconfig b/src/console/Kconfig index 9151a32..c0f0f2b 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -5,7 +5,7 @@ config BOOTBLOCK_CONSOLE bool "Enable early (bootblock) console output." - depends on !ROMCC_BOOTBLOCK && !NO_BOOTBLOCK_CONSOLE + depends on !NO_BOOTBLOCK_CONSOLE default y help Use console during the bootblock if supported diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index 73afe0b..238aad7 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -1,7 +1,7 @@ config MICROCODE_UPDATE_PRE_RAM bool depends on SUPPORT_CPU_UCODE_IN_CBFS - default y if !ROMCC_BOOTBLOCK + default y help Select this option if you want to update the microcode during the cache as ram setup. diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index efb5fa9..76446a0 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -77,7 +77,6 @@ config SETUP_XIP_CACHE bool - depends on !ROMCC_BOOTBLOCK depends on !NO_XIP_EARLY_STAGES help Select this option to set up an MTRR to cache XIP stages loaded diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 97086b7..c88d317 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -1,9 +1,5 @@ comment "Important: Run 'make distclean' before switching boards" -if ROMCC_BOOTBLOCK -comment "Systems with ROMCC bootblocks will be deprecated soon!" -endif - choice prompt "Mainboard vendor" default VENDOR_EMULATION diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index a829443..e03b51d 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -95,7 +95,6 @@ config VBOOT_STARTS_IN_BOOTBLOCK bool default n - depends on !ROMCC_BOOTBLOCK help Firmware verification happens during the end of or right after the bootblock. This implies that a static VBOOT2_WORK() buffer must be -- To view, visit https://review.coreboot.org/c/coreboot/+/37336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I968c4392849045cd50bfe2c83de44daba38ee245 Gerrit-Change-Number: 37336 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: vendorcode/cavium/bdk/libdram: Add missing <stdlib.h>
by HAOUAS Elyes (Code Review) 27 Dec '19

27 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37378 ) Change subject: vendorcode/cavium/bdk/libdram: Add missing <stdlib.h> ...................................................................... vendorcode/cavium/bdk/libdram: Add missing <stdlib.h> Change-Id: I9ded44422a267e244343502dd5d6ab355e5a788d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/37378/1 diff --git a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c index 291fe85..47eb07d 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c @@ -39,6 +39,7 @@ #include <bdk.h> #include "dram-internal.h" +#include <stdlib.h> #include <string.h> #include <lame_string.h> /* for strtoul */ #include <libbdk-hal/bdk-atomic.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ded44422a267e244343502dd5d6ab355e5a788d Gerrit-Change-Number: 37378 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 18

Change in coreboot[master]: volteer: add initial support for mainboard volteer
by Nick Vaccaro (Code Review) 26 Dec '19

26 Dec '19

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37114 ) Change subject: volteer: add initial support for mainboard volteer ...................................................................... volteer: add initial support for mainboard volteer BUG=b:142961277 BRANCH=master TEST="emerge-volteer coreboot" compiles successfully. Change-Id: Ifbe1499446d0928d43b2e09aa047fbaef15c79c3 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- A src/mainboard/google/volteer/Kconfig A src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/Makefile.inc A src/mainboard/google/volteer/acpi/mainboard.asl A src/mainboard/google/volteer/acpi/mipi_camera.asl A src/mainboard/google/volteer/acpi_tables.c A src/mainboard/google/volteer/board_info.txt A src/mainboard/google/volteer/bootblock.c A src/mainboard/google/volteer/chromeos.c A src/mainboard/google/volteer/chromeos.fmd A src/mainboard/google/volteer/dsdt.asl A src/mainboard/google/volteer/ec.c A src/mainboard/google/volteer/romstage.c A src/mainboard/google/volteer/smihandler.c A src/mainboard/google/volteer/spd/Makefile.inc A src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex A src/mainboard/google/volteer/spd/spd.h A src/mainboard/google/volteer/variants/baseboard/Makefile.inc A src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/baseboard/gpio.c A src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h A src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/volteer/variants/baseboard/mainboard.c A src/mainboard/google/volteer/variants/baseboard/memory.c A src/mainboard/google/volteer/variants/baseboard/nhlt.c A src/mainboard/google/volteer/variants/volteer/Makefile.inc A src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/volteer/include/variant/ec.h A src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h 30 files changed, 2,492 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37114/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig new file mode 100644 index 0000000..229fb6e --- /dev/null +++ b/src/mainboard/google/volteer/Kconfig @@ -0,0 +1,88 @@ +config BOARD_GOOGLE_BASEBOARD_VOLTEER + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_SPI_ACPI + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_LPC + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 + select SOC_INTEL_TIGERLAKE + +if BOARD_GOOGLE_BASEBOARD_VOLTEER + +config DIMM_SPD_SIZE + int + default 512 + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config DRIVER_TPM_SPI_BUS + depends on MAINBOARD_HAS_SPI_TPM_CR50 + default 0x1 + +config GBB_HWID + string + depends on CHROMEOS + default "VOLTEER TEST 8437" if BOARD_GOOGLE_VOLTEER + +config INCLUDE_NHLT_BLOBS_VOLTEER + bool "Include blobs for volteer audio." + select NHLT_RT5682 + select NHLT_MAX98357 + +config MAINBOARD_DIR + string + default "google/volteer" + +config MAINBOARD_FAMILY + string + default "Google_Volteer" if BOARD_GOOGLE_VOLTEER + +config MAINBOARD_PART_NUMBER + string + default "Volteer" if BOARD_GOOGLE_VOLTEER + +config MAX_CPUS + int + default 8 + +config OEM_BIN_FILE + string "OEM ID table" + default "" + +config TPM_TIS_ACPI_INTERRUPT + int + default 21 # GPE0_DW0_21 (GPP_C21) + +config UART_FOR_CONSOLE + default 0 + +config VARIANT_DIR + string + default "volteer" if BOARD_GOOGLE_VOLTEER + +# Select this option to enable camera ACPI support on the variant. +config VARIANT_HAS_CAMERA_ACPI + bool + default n + +config VARIANT_SPECIFIC_OPTIONS_VOLTEER + def_bool n + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + select VBOOT_LID_SWITCH + +endif # BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name new file mode 100644 index 0000000..d74bddc --- /dev/null +++ b/src/mainboard/google/volteer/Kconfig.name @@ -0,0 +1,6 @@ +comment "Volteer" + +config BOARD_GOOGLE_VOLTEER + bool "-> Volteer" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select VARIANT_SPECIFIC_OPTIONS_VOLTEER diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc new file mode 100644 index 0000000..58451eb --- /dev/null +++ b/src/mainboard/google/volteer/Makefile.inc @@ -0,0 +1,37 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c +bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-$(CONFIG_CHROMEOS) += romstage.c + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c + +smm-y += ec.c +smm-y += smihandler.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +subdirs-y += spd diff --git a/src/mainboard/google/volteer/acpi/mainboard.asl b/src/mainboard/google/volteer/acpi/mainboard.asl new file mode 100644 index 0000000..6647ac1 --- /dev/null +++ b/src/mainboard/google/volteer/acpi/mainboard.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if CONFIG(EC_GOOGLE_CHROMEEC) +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} +#endif diff --git a/src/mainboard/google/volteer/acpi/mipi_camera.asl b/src/mainboard/google/volteer/acpi/mipi_camera.asl new file mode 100644 index 0000000..bd2727e --- /dev/null +++ b/src/mainboard/google/volteer/acpi/mipi_camera.asl @@ -0,0 +1,533 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0) +{ + Device (IPU0) + { + Name (_ADR, 0x00050000) // _ADR: Address + Name (_DDN, "Camera and Imaging Subsystem") // _DDN: DOS Device Name + } +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + One + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} + +Scope (_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM0, + Zero, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C5.CAM1, + Zero, + Zero + } + } + } + }) +} + +Scope (\_SB.PCI0.I2C3) +{ + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) // _ON_: Power On + { + If ((STA == Zero)) + { + // Enable CLK0 + MCCT(0,1,1) // Clock 0, enable, 19.2MHz + // Pull PWREN(GPIO B23) high + STXS(GPP_B23) + Sleep(5) + // Pull RST(GPIO C15) low + CTXS(GPP_C15) + Sleep(5) + // Pull RST high + STXS(GPP_C15) + Sleep(5) + Store(1,STA) + } + } + + Method (_OFF, 0, Serialized) // _OFF: Power Off + { + If ((STA == One)) + { + // Pull RST low + CTXS(GPP_C15) + // Pull PWREN low + CTXS(GPP_B23) + // Disable CLK0 + MCCT(0,0,1) // Clock 0, disable, 19.2MHz + // STA = Zero + Store(0,STA) + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (STA) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI8856") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_DDN, "Ov 8856 Camera") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + RCPR + }) + + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + RCPR + }) + + Name (_DSD, Package (0x04) // _DSD: Device-Specific Data + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x325AA000 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } + + Device (VCM0) + { + Name (_HID, "PRP0001") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_DDN, "DW9714 VCM") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + CAM0 + }) + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + RCPR + }) + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + RCPR + }) + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} + +Scope (\_SB.PCI0.I2C5) +{ + PowerResource (FCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) // _ON_: Power On + { + If ((STA == Zero)) + { + // Enable CLK1 + MCCT(1,1,1) // Clock 1, enable, 19.2MHz + // Pull PWREN(GPIO R6) high + STXS(GPP_R6) + Sleep(5) + // Pull RST(GPIO H12) low + CTXS(GPP_H12) + Sleep(5) + // Pull RST high + STXS(GPP_H12) + Sleep(5) + Store(1,STA) + } + } + + Method (_OFF, 0, Serialized) // _OFF: Power Off + { + If ((STA == One)) + { + // Pull RST low + CTXS(GPP_H12) + // Pull PWREN low + CTXS(GPP_R6) + // Disable CLK0 + MCCT(1,0,1) // Clock 1, disable, 19.2MHz + Store(0,STA) + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (STA) + } + } + + Device (CAM1) + { + Name (_HID, "OVTI8856") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_DDN, "Ov 8856 Camera") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + FCPR + }) + + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + FCPR + }) + + Name (_DSD, Package (0x04) // _DSD: Device-Specific Data + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x325AA000 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/google/volteer/acpi_tables.c b/src/mainboard/google/volteer/acpi_tables.c new file mode 100644 index 0000000..3b44754 --- /dev/null +++ b/src/mainboard/google/volteer/acpi_tables.c @@ -0,0 +1 @@ +/* Nothing here */ diff --git a/src/mainboard/google/volteer/board_info.txt b/src/mainboard/google/volteer/board_info.txt new file mode 100644 index 0000000..c41a04b --- /dev/null +++ b/src/mainboard/google/volteer/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Volteer Tigerlake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/volteer/bootblock.c b/src/mainboard/google/volteer/bootblock.c new file mode 100644 index 0000000..12dac03 --- /dev/null +++ b/src/mainboard/google/volteer/bootblock.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c new file mode 100644 index 0000000..c8a884f --- /dev/null +++ b/src/mainboard/google/volteer/chromeos.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, +#ifdef EC_SYNC_GPIO + {EC_SYNC_GPIO, ACTIVE_LOW, gpio_get(EC_SYNC_GPIO), + "EC sync gpio"}, +#endif + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int __weak get_lid_switch(void) +{ + /* Lid always open */ + return gpio_get(GPIO_LID); +} + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd new file mode 100644 index 0000000..60ea3de --- /dev/null +++ b/src/mainboard/google/volteer/chromeos.fmd @@ -0,0 +1,47 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0x1b00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0xf00000 + RW_SECTION_A@0xf00000 0x3e0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3cffc0 + RW_FWID_A@0x3dffc0 0x40 + } + RW_SECTION_B@0x12e0000 0x3e0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3cffc0 + RW_FWID_B@0x3dffc0 0x40 + } + RW_MISC@0x16c0000 0x40000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x38000 0x2000 + RW_NVRAM(PRESERVE)@0x3a000 0x6000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x1700000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl new file mode 100644 index 0000000..0b1b265 --- /dev/null +++ b/src/mainboard/google/volteer/dsdt.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include "variant/ec.h" +#include "variant/gpio.h" + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/tigerlake_dev/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/tigerlake_dev/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/tigerlake_dev/acpi/northbridge.asl> + #include <soc/intel/tigerlake_dev/acpi/southbridge.asl> + } + } + +#if CONFIG(CHROMEOS) + // Chrome OS specific + #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + // Chipset specific sleep states + #include <soc/intel/tigerlake_dev/acpi/sleepstates.asl> +} diff --git a/src/mainboard/google/volteer/ec.c b/src/mainboard/google/volteer/ec.c new file mode 100644 index 0000000..4699806 --- /dev/null +++ b/src/mainboard/google/volteer/ec.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/lpc_lib.h> +#include <variant/ec.h> + +static void ramstage_ec_init(void) +{ + static const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + printk(BIOS_ERR, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} + +static void bootblock_ec_init(void) +{ + uint16_t ec_ioport_base; + size_t ec_ioport_size; + + /* + * Set up LPC decoding for the ChromeEC I/O port ranges: + * - Ports 62/66, 60/64, and 200->208 + * - ChromeEC specific communication I/O ports. + */ + lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64 + | LPC_IOE_LGE_200); + google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size); + lpc_open_pmio_window(ec_ioport_base, ec_ioport_size); +} + +void mainboard_ec_init(void) +{ + if (ENV_RAMSTAGE) + ramstage_ec_init(); + else if (ENV_BOOTBLOCK) + bootblock_ec_init(); +} diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c new file mode 100644 index 0000000..c2fb01af --- /dev/null +++ b/src/mainboard/google/volteer/romstage.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <baseboard/variants.h> +#include <cbfs.h> +#include <console/console.h> +#include <soc/gpio.h> +#include <soc/romstage.h> +#include <string.h> +#include <variant/gpio.h> + +#include <fsp/soc_binding.h> + +static uintptr_t mainboard_get_spd_data(void) +{ + char *spd_file; + size_t spd_file_len; + int spd_index; + const size_t spd_len = CONFIG_DIMM_SPD_SIZE; + const char *spd_bin = "spd.bin"; + + spd_index = variant_memory_sku(); + assert(spd_index >= 0); + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < spd_len) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * spd_len)) + die("Invalid SPD index."); + + spd_index *= spd_len; + + return (uintptr_t)(spd_file + spd_index); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + struct memory_config mconfig; + uintptr_t spd_ptr; + + memset(&mconfig, 0, sizeof(mconfig)); + variant_memory_params(&mconfig); + + if (mconfig.dq_map && mconfig.dq_map_size) + memcpy(&mem_cfg->DqMapCpu2DramMc0Ch0, mconfig.dq_map, + mconfig.dq_map_size); + + if (mconfig.dqs_map && mconfig.dqs_map_size) + memcpy(&mem_cfg->DqsMapCpu2DramMc0Ch0, mconfig.dqs_map, + mconfig.dqs_map_size); + + mem_cfg->RcompResistor = mconfig.rcomp_resistor; + memcpy(&mem_cfg->RcompTarget, mconfig.rcomp_target, + mconfig.rcomp_target_size); + + /* Set 0 for SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1 */ + mem_cfg->SpdAddressTable[0] = 0x0; + mem_cfg->SpdAddressTable[1] = 0x0; + mem_cfg->SpdAddressTable[8] = 0x0; + mem_cfg->SpdAddressTable[9] = 0x0; + + /* CH 0-7 Single Rank Config + MC0 - Controls CH 0-3 -> connected to DIMM 0-1 + MC1 - Controls CH 4-7 -> connected to DIMM 2-3 */ + spd_ptr = mainboard_get_spd_data(); + + if (CONFIG(LPDDR4_MC0_DISABLE)) + printk(BIOS_INFO, "MC0 is disabled\n"); + else { + mem_cfg->MemorySpdPtr000 = spd_ptr; + mem_cfg->MemorySpdPtr010 = spd_ptr; + mem_cfg->MemorySpdPtr020 = spd_ptr; + mem_cfg->MemorySpdPtr030 = spd_ptr; + } + mem_cfg->MemorySpdPtr100 = spd_ptr; + mem_cfg->MemorySpdPtr110 = spd_ptr; + mem_cfg->MemorySpdPtr120 = spd_ptr; + mem_cfg->MemorySpdPtr130 = spd_ptr; + mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + + mem_cfg->DqPinsInterleaved = 0; + + mem_cfg->SkipExtGfxScan = 0; + mem_cfg->LockPTMregs = 0; + mem_cfg->X2ApicOptOut = 0x1; + mem_cfg->UsbTcPortEnPreMem = 0xF; + mem_cfg->VmxEnable = 0x1; + mem_cfg->PchNumRsvdSmbusAddresses = 0; + mem_cfg->IedSize = 0x0; + mem_cfg->MrcSafeConfig = 0x1; + mem_cfg->ChHashMask = 0x30CC; + mem_cfg->SafeMode = 1; + + mem_cfg->DmiGen3RootPortPreset[0] = 0x8; + mem_cfg->DmiGen3RootPortPreset[1] = 0x8; + mem_cfg->DmiGen3RootPortPreset[2] = 0x8; + mem_cfg->DmiGen3RootPortPreset[3] = 0x8; + mem_cfg->DmiGen3RootPortPreset[4] = 0x8; + mem_cfg->DmiGen3RootPortPreset[5] = 0x8; + mem_cfg->DmiGen3RootPortPreset[6] = 0x8; + mem_cfg->DmiGen3RootPortPreset[7] = 0x8; + + mem_cfg->ECT = 0; /* Early Command Training Enabled */ + mem_cfg->RefClk = 0; /* Auto Select CLK freq */ +} diff --git a/src/mainboard/google/volteer/smihandler.c b/src/mainboard/google/volteer/smihandler.c new file mode 100644 index 0000000..a1b2716 --- /dev/null +++ b/src/mainboard/google/volteer/smihandler.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/smm.h> +#include <intelblocks/smihandler.h> +#include <variant/ec.h> + +#if CONFIG(EC_GOOGLE_CHROMEEC) +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} +#endif diff --git a/src/mainboard/google/volteer/spd/Makefile.inc b/src/mainboard/google/volteer/spd/Makefile.inc new file mode 100644 index 0000000..ea1cfa2 --- /dev/null +++ b/src/mainboard/google/volteer/spd/Makefile.inc @@ -0,0 +1,35 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Intel Corporation. +## Copyright (C) 2019 Google, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +ifeq ($(SPD_SOURCES),) + SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) +else + SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +endif + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex b/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex new file mode 100644 index 0000000..e1f27fb --- /dev/null +++ b/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 19 95 08 00 40 00 00 02 21 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/spd/spd.h b/src/mainboard/google/volteer/spd/spd.h new file mode 100644 index 0000000..666b3c5 --- /dev/null +++ b/src/mainboard/google/volteer/spd/spd.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_ch0(void *dq_map_ptr); +void mainboard_fill_dq_map_ch1(void *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/google/volteer/variants/baseboard/Makefile.inc b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc new file mode 100644 index 0000000..d610cc1 --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Google, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c +ramstage-y += mainboard.c + +smm-y += gpio.c + diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..7195605 --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -0,0 +1,288 @@ +chip soc/intel/tigerlake_dev + + device cpu_cluster 0 on + device lapic 0 on end + end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "0xb" # GPP_C + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # FSP configuration + register "SaGv" = "SaGv_Disabled" + register "SmbusEnable" = "0" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Cl + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Co + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera + + # Enable Pch iSCLK + register "pch_isclk" = "1" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + register "PrmrrSize" = "0x10000000" + + register "PcieRpEnable[8]" = "1" + register "PcieClkSrcUsage[0]" = "8" + register "PcieClkSrcClkReq[0]" = "0" + + register "PcieRpEnable[6]" = "1" + register "PcieClkSrcUsage[1]" = "6" + register "PcieClkSrcClkReq[1]" = "1" + + register "SataEnable" = "1" + register "SataMode" = "0" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[0]" = "0" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C6] = PchSerialIoDisabled, + [PchSerialIoIndexI2C7] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI4] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI5] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI6] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + [PchSerialIoIndexGSPI4] = 0, + [PchSerialIoIndexGSPI5] = 0, + [PchSerialIoIndexGSPI6] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + [PchSerialIoIndexGSPI4] = 0, + [PchSerialIoIndexGSPI5] = 0, + [PchSerialIoIndexGSPI6] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + [PchSerialIoIndexUART3] = PchSerialIoDisabled, + [PchSerialIoIndexUART4] = PchSerialIoDisabled, + [PchSerialIoIndexUART5] = PchSerialIoDisabled, + [PchSerialIoIndexUART6] = PchSerialIoDisabled, + }" + + # ISH + register "PchIshSpiEnable" = "0" + register "PchIshSpiCs0Enable" = "0" + register "PchIshUartEnable[0]" = "0" + register "PchIshUartEnable[1]" = "0" + register "PchIshI2cEnable[0]" = "0" + register "PchIshI2cEnable[1]" = "0" + register "PchIshI2cEnable[2]" = "0" + register "PchIshGpEnable[0]" = "0" + register "PchIshGpEnable[1]" = "0" + register "PchIshGpEnable[2]" = "0" + register "PchIshGpEnable[3]" = "0" + register "PchIshGpEnable[4]" = "0" + register "PchIshGpEnable[5]" = "0" + register "PchIshGpEnable[6]" = "0" + register "PchIshGpEnable[7]" = "0" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "0" + + # Enable S0ix + register "s0ix_enable" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #| pch_thermal_trip | PCH Trip Temperature | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 98, + .fall_time_ns = 38, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 98, + .fall_time_ns = 38, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 98, + .fall_time_ns = 38, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 98, + .fall_time_ns = 38, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 98, + .fall_time_ns = 38, + }, + .pch_thermal_trip = 75, + }" + + device domain 0 on + #From EDS(575683) + device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF 0x9A03 + device pci 05.0 on end # IPU 0x9A19 + device pci 06.0 on end # PEG60 0x9A09 + device pci 07.0 on end # TBT_PCIe0 0x9A23 + device pci 07.1 on end # TBT_PCIe1 0x9A25 + device pci 07.2 off end # TBT_PCIe2 0x9A27 + device pci 07.3 off end # TBT_PCIe3 0x9A29 + device pci 08.0 on end # GNA 0x9A11 + device pci 09.0 off end # NPK 0x9A33 + device pci 0a.0 on end # Crash-log SRAM 0x9A0D + device pci 0d.0 on end # USB xHCI 0x9A13 + device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 + device pci 0d.2 off end # TBT DMA0 0x9A1B + device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0e.0 on end # VMD 0x9A0B + + # From PCH EDS(576591) + device pci 10.0 off end # I2C6 0xA0D8 + device pci 10.1 off end # I2C7 0xA0D9 + device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.6 off end # THC0 0xA0D0 + device pci 10.7 off end # THC1 0xA0D1 + + device pci 11.0 off end # UART3 0xA0DA + device pci 11.1 off end # UART4 0xA0DB + device pci 11.2 off end # UART5 0xA0DC + device pci 11.3 off end # UART6 0xA0DD + + device pci 12.0 off end # SensorHUB 0xA0FC + device pci 12.6 off end # GSPI2 0x34FB + + device pci 13.0 off end # GSPI3 0xA0FD + device pci 13.1 off end # GSPI4 0xA0FE + device pci 13.2 off end # GSPI5 0xA0DE + device pci 13.3 off end # GSPI6 0xA0DF + + device pci 14.0 on end # USB3.1 xHCI 0xA0ED + device pci 14.1 on end # USB3.1 xDCI 0xA0EE + device pci 14.2 on end # Shared RAM 0xA0EF + device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + + device pci 15.0 on end # I2C0 0xA0E8 + device pci 15.1 on end # I2C1 0xA0E9 + device pci 15.2 on end # I2C2 0xA0EA + device pci 15.3 on end # I2C3 0xA0EB + + device pci 16.0 on end # HECI1 0xA0E0 + device pci 16.1 off end # HECI2 0xA0E1 + device pci 16.2 off end # CSME 0xA0E2 + device pci 16.3 off end # CSME 0xA0E3 + device pci 16.4 off end # HECI3 0xA0E4 + device pci 16.5 off end # HECI4 0xA0E5 + + device pci 17.0 on end # SATA 0xA0D3 + + device pci 19.0 off end # I2C4 0xA0C5 + device pci 19.1 on end # I2C5 0xA0C6 + device pci 19.2 off end # UART2 0xA0C7 + + device pci 1c.0 on end # RP1 0xA0B8 + device pci 1c.1 off end # RP2 0xA0B9 + device pci 1c.2 off end # RP3 0xA0BA + device pci 1c.3 off end # RP4 0xA0BB + device pci 1c.4 off end # RP5 0xA0BC + device pci 1c.5 off end # RP6 0xA0BD + device pci 1c.6 on end # RP7 0xA0BE + device pci 1c.7 off end # RP8 0xA0BF + + device pci 1d.0 on end # RP9 0xA0B0 + device pci 1d.1 off end # RP10 0xA0B1 + device pci 1d.2 off end # RP11 0xA0B2 + device pci 1d.3 off end # RP12 0xA0B3 + device pci 1d.4 off end # RP13 0xA0B4 + device pci 1d.5 off end # RP14 0xA0B5 + device pci 1d.6 off end # RP15 0xA0B6 + device pci 1d.7 off end # RP16 0xA0B7 + + device pci 1e.0 on end # UART0 0xA0A8 + device pci 1e.1 off end # UART1 0xA0A9 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" + device spi 0 on end + end + end # GSPI0 0xA0AA + device pci 1e.3 on end # GSPI1 0xA0AB + + device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.1 off end # P2SB 0xA0A0 + device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.3 off end # Intel HD audio 0xA0C8-A0CF + device pci 1f.4 off end # SMBus 0xA0A3 + device pci 1f.5 on end # SPI 0xA0A4 + device pci 1f.6 off end # GbE 0x15E1/0x15E2 + device pci 1f.7 off end # TH 0xA0A6 + end +end diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c new file mode 100644 index 0000000..8b26104 --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -0,0 +1,483 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + /* A5 : ESPI_CLK ==> ESPI_CLK */ + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + /* A6 : ESPI_RESET# ==> NC(TP764) */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A9 : I2S2_TXD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_A9, NONE, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A11 : PMC_I2C_SDA ==> SSD_PERST_ODL */ + PAD_CFG_GPO(GPP_A11, 1, DEEP), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14 : USB_OC1# ==> USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B0 : CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : VRALERT# ==> VRALERT_L */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B4 : CPU_GP3 ==> NC */ + /* B5 : ISH_I2C0_CVF_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : ISH_I2C0_CVF_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B12 : SLP_S0# ==> SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> GPP_B14_STRAP */ + PAD_CFG_GPI(GPP_B14, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, PLTRST, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_CFG_GPI(GPP_B23, DN_20K, DEEP), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> EN_USB_CAM_PWR */ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_CFG_GPI(GPP_C2, DN_20K, DEEP), + /* C3 : SML0CLK ==> USB4_SMB_SCL */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : SML0DATA ==> USB4_SMB_SDA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_CFG_GPI(GPP_C5, DN_20K, DEEP), + /* C6 : SML1CLK ==> EC_PCH_INT_ODL */ + PAD_CFG_GPO(GPP_C6, 1, PLTRST), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C8 : UART0_RXD ==> UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : UART0_CTS# ==> CVF_LPSS_INT_L */ + PAD_CFG_GPI(GPP_C11, UP_20K, DEEP), + /* C12 : UART1_RXD ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_C12, NONE, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C14 : UART1_RTS# ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_C14, NONE, DEEP), + /* C15 : UART1_CTS# ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_C15, NONE, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPO(GPP_C20, 1, PLTRST), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_CFG_GPI(GPP_D0, UP_20K, DEEP), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, UP_20K, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, UP_20K, DEEP), + /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ + PAD_CFG_GPI(GPP_D3, UP_20K, DEEP), + /* D4 : IMGCLKOUT0 ==> CAM_CVF_RST_L */ + PAD_CFG_TERM_GPO(GPP_D4, 1, DN_20K, DEEP), + /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> PCH_GSPI2_CVF_CS_L */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF7), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D11 : ISH_SPI_MISO ==> PCH_GSPI2_CVF_MISO */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_D15, NONE, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_CVF_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* D18 : ISH_GP5 ==> CVF_ACE_ISH_INT_L */ + PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1), + /* D19 : I2S_MCLK1 ==> I2S_MCLK1 */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_E1, NONE, DEEP), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ + PAD_CFG_GPI(GPP_E6, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ + /* NOTE - verify this is an output */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E10, NONE, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), + /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ + PAD_CFG_GPO(GPP_E13, 0, DEEP), + /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI(GPP_E15, NONE, DEEP), + /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ + PAD_CFG_TERM_GPO(GPP_E17, 1, DN_20K, DEEP), + /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), + /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF4), + /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E22, NONE, DEEP), + /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E23, NONE, DEEP), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ + PAD_CFG_NF(GPP_F0, DN_20K, DEEP, NF1), + /* F1 : CNV_BRI_RSP ==> NCV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : I2S2_TXD ==> CNV_RGI_DT_STRAP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : I2S2_RXD ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : CNV_RF_RESET# ==> NC */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF2), + /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : GPPF7_STRAP */ + PAD_CFG_GPI(GPP_F7, DN_20K, DEEP), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI(GPP_F8, UP_20K, DEEP), + /* F9 : Reserved ==> NC */ + /* F10 : GPPF10_STRAP */ + PAD_CFG_GPI(GPP_F10, DN_20K, DEEP), + /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_ODL */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F14 : GSXDIN ==> SAR0_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + /* F15 : GSXSRESET# ==> SAR1_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F15, NONE, PLTRST, EDGE_SINGLE), + /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_F17, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + /* F20 : EXT_PWR_GATE# ==> EXT_PWR_GATE_L */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EXT_PWR_GATE2# ==> EXT_PWR_GATE2_L */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : V1P05_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_CFG_GPI(GPP_H0, DN_20K, DEEP), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_CFG_GPI(GPP_H1, DN_20K, DEEP), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_CFG_GPI(GPP_H2, DN_20K, DEEP), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : I2C2_SDA ==> PCH_I2C2_SAR0_WLAN_HDMI_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C2_SCL ==> PCH_I2C2_SAR0_WLAN_HDMI_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SAR1_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SAR1_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */ + /* NOTE - check default of 1 ? */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, RSMRST), + /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> WWAN_CONFIG2 */ + PAD_CFG_GPI(GPP_H14, NONE, DEEP), + /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_H15, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> PCH_CAM_VSYNC */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> EN_MIPI_CAM_PWR */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* H23 : IMGCLKOUT4 ==> WWAN_ESIM_SEL_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : HDA_RST# ==> HDA_RST_L */ + PAD_CFG_NF(GPP_R4, DN_20K, DEEP, NF1), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> DMIC_CLK1 */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + /* S5 : SNDW2_DATA ==> DMIC_DATA1 */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1), + + /* GPD0: BATLOW# ==> BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ + PAD_CFG_GPI(GPD2, NONE, DEEP), + /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> SLP_A_L */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: GPD7_STRAP */ + PAD_CFG_GPI(GPD7, DN_20K, DEEP), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: SLP_S5# ==> SLP_S5_L */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: LANPHYC ==> NC */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, RSMRST), +}; + +const struct pad_config *__weak variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *__weak variant_override_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *__weak variant_early_override_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..ac0d844 --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <variant/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid, power button or mode change event */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..1c4c02d --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_A9 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_B11 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +/* EC wake is LAN_WAKE# */ +#define GPE_EC_WAKE GPD2 + +/* Lid switch */ +#define GPIO_LID GPP_D2 + +/* EC sync gpio */ +#define EC_SYNC_GPIO GPP_C6 + +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_C6_IRQ + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +#endif /* BASEBOARD_GPIO_H */ diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..9f92fe4 --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct pad_config *variant_base_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_override_gpio_table(size_t *num); +const struct pad_config *variant_early_override_gpio_table(size_t *num); +const struct pad_config *variant_sleep_gpio_table(size_t *num, int slp_typ); + +/* + * Callback to get GPIOs to configure in romstage before memory training is + * performed. + */ +const struct pad_config *variant_romstage_gpio_table(size_t *num); + +const struct cros_gpio *variant_cros_gpios(size_t *num); + +/* Config gpio by different sku id */ +const struct pad_config *variant_sku_gpio_table(size_t *num); + +struct memory_config { + const void *dq_map; + size_t dq_map_size; + const void *dqs_map; + size_t dqs_map_size; + u16 rcomp_resistor; + const void *rcomp_target; + size_t rcomp_target_size; +}; + +void variant_memory_params(struct memory_config *p); +int variant_memory_sku(void); +void variant_devtree_update(void); +uint32_t variant_board_sku(void); +void variant_smi_sleep(u8 slp_typ); + +struct nhlt; +void variant_nhlt_init(struct nhlt *nhlt); +void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, + uint32_t *oem_revision); + +struct google_chromeec_event_info; +/* + * Read google_chromeec_event_info structure from variant to set different masks + * on the EC e.g. SCI, S3, S5, S0ix, SMI. + */ +const struct google_chromeec_event_info *variant_get_event_info(void); + +#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/volteer/variants/baseboard/mainboard.c b/src/mainboard/google/volteer/variants/baseboard/mainboard.c new file mode 100644 index 0000000..9055f3b --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/mainboard.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <device/device.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> +#include <smbios.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <variant/gpio.h> + +#define SKU_UNKNOWN 0xFFFFFFFF +#define SKU_MAX 255 + +static uint32_t get_board_sku(void) +{ + static uint32_t sku_id = SKU_UNKNOWN; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + sku_id = SKU_UNKNOWN; + + return sku_id; +} + +const char *smbios_system_sku(void) +{ + static char sku_str[7]; /* sku{0..255} */ + uint32_t sku_id = get_board_sku(); + + if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) { + printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", + __func__, sku_id); + return ""; + } + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + + return sku_str; +} + +static void mainboard_init(void *chip_info) +{ + int boardid; + const struct pad_config *base_pads; + const struct pad_config *override_pads; + size_t base_num, override_num; + + boardid = board_id(); + printk(BIOS_INFO, "Board ID: %d\n", boardid); + + base_pads = variant_base_gpio_table(&base_num); + override_pads = variant_override_gpio_table(&override_num); + + gpio_configure_pads_with_override(base_pads, base_num, + override_pads, override_num); + + mainboard_ec_init(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c new file mode 100644 index 0000000..f6ccc79 --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +/* DQ byte map */ +static const u8 dq_map[8][2][8] = { + //Controller 0 + { { 0, 1, 2, 3, 4, 5, 6, 7 }, // Byte 0 + { 12, 13, 14, 15, 11, 10, 9, 8 } }, // Byte 1 + { { 7, 2, 6, 3, 5, 1, 4, 0 }, // Byte 2 + { 10, 8, 9, 11, 15, 12, 14, 13 } }, // Byte 3 + { { 3, 2, 1, 0, 4, 5, 6, 7 }, // Byte 4 + { 12, 13, 14, 15, 11, 10, 9, 8 } }, // Byte 5 + { { 7, 0, 1, 6, 5, 4, 2, 3 }, // Byte 6 + { 15, 14, 8, 9, 10, 12, 11, 13 } }, // Byte 7 + //Controller 1 + { { 3, 2, 1, 0, 4, 5, 6, 7 }, // Byte 0 ChB! + { 12, 13, 14, 15, 11, 10, 9, 8 } }, // Byte 1 ChB! + { { 3, 4, 2, 5, 0, 6, 1, 7 }, // Byte 2 + { 13, 12, 11, 10, 14, 15, 9, 8 } }, // Byte 3 + { { 3, 2, 1, 0, 7, 4, 5, 6 }, // Byte 4 + { 15, 14, 13, 12, 8, 9, 10, 11 } }, // Byte 5 + { { 3, 4, 2, 5, 1, 0, 7, 6 }, // Byte 6 + { 15, 14, 9, 8, 12, 10, 11, 13 } } // Byte 7 + }; + +/* DQS CPU<>DRAM map */ +static const u8 dqs_map[8][2] = { + // Ch 0 1 2 3 + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, // Controller 0 + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } // Controller 1 +}; + +void __weak variant_memory_params(struct memory_config *mem_config) +{ + mem_config->dq_map = dq_map; + mem_config->dq_map_size = sizeof(dq_map); + mem_config->dqs_map = dqs_map; + mem_config->dqs_map_size = sizeof(dqs_map); +} + +int __weak variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} diff --git a/src/mainboard/google/volteer/variants/baseboard/nhlt.c b/src/mainboard/google/volteer/variants/baseboard/nhlt.c new file mode 100644 index 0000000..cbb11af --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/nhlt.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +void __weak variant_nhlt_init(struct nhlt *nhlt) +{ + /* 2 Channel DMIC array. */ + if (!nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Added 2CH DMIC array.\n"); + + /* 4 Channel DMIC array. */ + if (!nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Added 4CH DMIC arrays.\n"); + + /* + * Headset codec is bi-directional but uses the same configuration + * settings for render and capture endpoints. + */ + if (CONFIG(NHLT_RT5682)) { + /* Realtek for Headset codec */ + if (!nhlt_soc_add_rt5682(nhlt, AUDIO_LINK_SSP2)) + printk(BIOS_ERR, "Added ALC5682 codec.\n"); + } + + if (CONFIG(NHLT_MAX98357)) { + /* MAXIM Smart Amps for left and right speakers. */ + if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); + } +} diff --git a/src/mainboard/google/volteer/variants/volteer/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/Makefile.inc new file mode 100644 index 0000000..c3adabd --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Google, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +## Memory Options +SPD_SOURCES = samsung-K4U6E3S4AA-MGCL # 0b0000 diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..5b51db9 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h new file mode 100644 index 0000000..a6d49aa --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h new file mode 100644 index 0000000..3fa7a0e --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe1499446d0928d43b2e09aa047fbaef15c79c3 Gerrit-Change-Number: 37114 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

1 4

Change in coreboot[master]: mb/google/hatch/akemi: Set touchpad hold time to 400ns
by Peichao Li (Code Review) 26 Dec '19

26 Dec '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37322 ) Change subject: mb/google/hatch/akemi: Set touchpad hold time to 400ns ...................................................................... mb/google/hatch/akemi: Set touchpad hold time to 400ns According to SI team request, need to tune I2C bus 0 data hold time more than 300ns BUG=None TEST=build firmware and measure I2C bus 0 data hold time Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I75e33419cbaef746487de6ee8628d07cf08adaa9 --- M src/mainboard/google/hatch/variants/akemi/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/37322/1 diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index da669e4..937810b 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -57,6 +57,7 @@ .speed = I2C_SPEED_FAST, .rise_time_ns = 50, .fall_time_ns = 15, + .data_hold_time_ns = 400, }, .i2c[1] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/37322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75e33419cbaef746487de6ee8628d07cf08adaa9 Gerrit-Change-Number: 37322 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: soc/intel/cannonlake: Clean up report_cpu_info() function
by Usha P (Code Review) 26 Dec '19

26 Dec '19

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37309 ) Change subject: soc/intel/cannonlake: Clean up report_cpu_info() function ...................................................................... soc/intel/cannonlake: Clean up report_cpu_info() function This patch makes below clean-up for report_cpu_info() function. 1. Remove unused variables. 3. Reuse fill_processor_name. TEST=Succesfully able to boot hatch and verify the cpu_name "CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz" Change-Id: I41c76eb93f0c5229c4a49ab041339b6ad51ad24a Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/report_platform.c 1 file changed, 4 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/37309/1 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 3d46916..eddcbd8 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -18,6 +18,7 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/x86/name.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/mp_init.h> @@ -161,35 +162,14 @@ static void report_cpu_info(void) { - struct cpuid_result cpuidr; - u32 i, index, cpu_id, cpu_feature_flag; - char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ + u32 i, cpu_id, cpu_feature_flag; + char cpu_name[49]; int vt, txt, aes; msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; - u32 p[13]; - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - } else { - int j=0; - - for (i = 2; i <= 4; i++) { - cpuidr = cpuid(index + i); - p[j++] = cpuidr.eax; - p[j++] = cpuidr.ebx; - p[j++] = cpuidr.ecx; - p[j++] = cpuidr.edx; - } - p[12]=0; - cpu_name = (char *)p; - } - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ') - cpu_name++; + fill_processor_name(cpu_name); microcode_ver.lo = 0; microcode_ver.hi = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/37309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41c76eb93f0c5229c4a49ab041339b6ad51ad24a Gerrit-Change-Number: 37309 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/intel/cannonlake: Refactor pch_early_init() code
by Usha P (Code Review) 26 Dec '19

26 Dec '19

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37308 ) Change subject: soc/intel/cannonlake: Refactor pch_early_init() code ...................................................................... soc/intel/cannonlake: Refactor pch_early_init() code This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBUS init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. Renamed the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=Able to build and boot hatch successfully. Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/bootblock.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/include/soc/bootblock.h M src/soc/intel/cannonlake/include/soc/romstage.h M src/soc/intel/cannonlake/romstage/Makefile.inc A src/soc/intel/cannonlake/romstage/pch.c M src/soc/intel/cannonlake/romstage/romstage.c 7 files changed, 36 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/37308/1 diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 9f85397..08c1242 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -74,5 +74,5 @@ */ gpi_clear_int_cfg(); report_platform_info(); - pch_early_init(); + bootblock_pch_init(); } diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 39433a2..a27b507 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,8 +25,6 @@ #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> -#include <intelblocks/smbus.h> -#include <intelblocks/tco.h> #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -35,7 +33,6 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/pm.h> -#include <soc/smbus.h> #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP 0x1400 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 0x0980 @@ -180,7 +177,7 @@ pch_enable_lpc(); } -void pch_early_init(void) +void bootblock_pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, @@ -188,12 +185,6 @@ */ soc_config_acpibase(); - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - - /* Program SMBUS_BASE_ADDRESS and Enable it */ - smbus_common_init(); - /* Set up GPE configuration */ pmc_gpe_init(); diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h index a5c3c32..efc837e 100644 --- a/src/soc/intel/cannonlake/include/soc/bootblock.h +++ b/src/soc/intel/cannonlake/include/soc/bootblock.h @@ -23,7 +23,7 @@ void bootblock_pch_early_init(void); /* Bootblock post console init programming */ -void pch_early_init(void); +void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h index 643105a..ab20ee7 100644 --- a/src/soc/intel/cannonlake/include/soc/romstage.h +++ b/src/soc/intel/cannonlake/include/soc/romstage.h @@ -24,6 +24,7 @@ /* Provide a callback to allow mainboard to override the DRAM part number. */ void mainboard_get_dram_part_num(const char **part_num, size_t *len); void systemagent_early_init(void); +void romstage_pch_init(void); /* Board type */ enum board_type { diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc index 33d9629..ff3d73d 100644 --- a/src/soc/intel/cannonlake/romstage/Makefile.inc +++ b/src/soc/intel/cannonlake/romstage/Makefile.inc @@ -17,3 +17,4 @@ romstage-y += romstage.c romstage-y += fsp_params.c romstage-y += systemagent.c +romstage-y += pch.c diff --git a/src/soc/intel/cannonlake/romstage/pch.c b/src/soc/intel/cannonlake/romstage/pch.c new file mode 100644 index 0000000..388ad77 --- /dev/null +++ b/src/soc/intel/cannonlake/romstage/pch.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/smbus.h> +#include <intelblocks/tco.h> +#include <soc/romstage.h> + +void romstage_pch_init(void) +{ + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); + + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); +} + diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index f782f63..2505683 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -132,6 +132,8 @@ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); + /* Program PCH init */ + romstage_pch_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); -- To view, visit https://review.coreboot.org/c/coreboot/+/37308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe Gerrit-Change-Number: 37308 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: PDCurses: Remove unused code/directories
by Martin Roth (Code Review) 23 Dec '19

23 Dec '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35429 ) Change subject: PDCurses: Remove unused code/directories ...................................................................... PDCurses: Remove unused code/directories There are a number of directories that came in with pdcurses that we don't need as a part of libpayload. Get rid of them. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I3b09104f64254d768d27a3d2e3fba8418e7ba2ca --- D payloads/libpayload/curses/PDCurses/demos/README D payloads/libpayload/curses/PDCurses/demos/firework.c D payloads/libpayload/curses/PDCurses/demos/newdemo.c D payloads/libpayload/curses/PDCurses/demos/ptest.c D payloads/libpayload/curses/PDCurses/demos/rain.c D payloads/libpayload/curses/PDCurses/demos/testcurs.c D payloads/libpayload/curses/PDCurses/demos/tui.c D payloads/libpayload/curses/PDCurses/demos/tui.h D payloads/libpayload/curses/PDCurses/demos/tuidemo.c D payloads/libpayload/curses/PDCurses/demos/worm.c D payloads/libpayload/curses/PDCurses/demos/xmas.c D payloads/libpayload/curses/PDCurses/dos/README D payloads/libpayload/curses/PDCurses/dos/bccdos.lrf D payloads/libpayload/curses/PDCurses/dos/bccdos.mak D payloads/libpayload/curses/PDCurses/dos/gccdos.mak D payloads/libpayload/curses/PDCurses/dos/mscdos.lrf D payloads/libpayload/curses/PDCurses/dos/mscdos.mak D payloads/libpayload/curses/PDCurses/dos/pdcclip.c D payloads/libpayload/curses/PDCurses/dos/pdcdisp.c D payloads/libpayload/curses/PDCurses/dos/pdcdos.h D payloads/libpayload/curses/PDCurses/dos/pdcgetsc.c D payloads/libpayload/curses/PDCurses/dos/pdckbd.c D payloads/libpayload/curses/PDCurses/dos/pdcscrn.c D payloads/libpayload/curses/PDCurses/dos/pdcsetsc.c D payloads/libpayload/curses/PDCurses/dos/pdcutil.c D payloads/libpayload/curses/PDCurses/dos/wccdos16.mak D payloads/libpayload/curses/PDCurses/dos/wccdos4g.mak D payloads/libpayload/curses/PDCurses/os2/README D payloads/libpayload/curses/PDCurses/os2/bccos2.mak D payloads/libpayload/curses/PDCurses/os2/gccos2.mak D payloads/libpayload/curses/PDCurses/os2/iccos2.lrf D payloads/libpayload/curses/PDCurses/os2/iccos2.mak D payloads/libpayload/curses/PDCurses/os2/pdcclip.c D payloads/libpayload/curses/PDCurses/os2/pdcdisp.c D payloads/libpayload/curses/PDCurses/os2/pdcgetsc.c D payloads/libpayload/curses/PDCurses/os2/pdckbd.c D payloads/libpayload/curses/PDCurses/os2/pdcos2.h D payloads/libpayload/curses/PDCurses/os2/pdcscrn.c D payloads/libpayload/curses/PDCurses/os2/pdcsetsc.c D payloads/libpayload/curses/PDCurses/os2/pdcutil.c D payloads/libpayload/curses/PDCurses/os2/wccos2.mak D payloads/libpayload/curses/PDCurses/sdl1/Makefile D payloads/libpayload/curses/PDCurses/sdl1/Makefile.mng D payloads/libpayload/curses/PDCurses/sdl1/README D payloads/libpayload/curses/PDCurses/sdl1/deffont.h D payloads/libpayload/curses/PDCurses/sdl1/deficon.h D payloads/libpayload/curses/PDCurses/sdl1/pdcclip.c D payloads/libpayload/curses/PDCurses/sdl1/pdcdisp.c D payloads/libpayload/curses/PDCurses/sdl1/pdcgetsc.c D payloads/libpayload/curses/PDCurses/sdl1/pdckbd.c D payloads/libpayload/curses/PDCurses/sdl1/pdcscrn.c D payloads/libpayload/curses/PDCurses/sdl1/pdcsdl.h D payloads/libpayload/curses/PDCurses/sdl1/pdcsetsc.c D payloads/libpayload/curses/PDCurses/sdl1/pdcutil.c D payloads/libpayload/curses/PDCurses/sdl1/sdltest.c D payloads/libpayload/curses/PDCurses/win32/README D payloads/libpayload/curses/PDCurses/win32/bccwin32.mak D payloads/libpayload/curses/PDCurses/win32/dmcwin32.mak D payloads/libpayload/curses/PDCurses/win32/gccwin32.mak D payloads/libpayload/curses/PDCurses/win32/lccwin32.mak D payloads/libpayload/curses/PDCurses/win32/mingwin32.mak D payloads/libpayload/curses/PDCurses/win32/pdcclip.c D payloads/libpayload/curses/PDCurses/win32/pdcdisp.c D payloads/libpayload/curses/PDCurses/win32/pdcgetsc.c D payloads/libpayload/curses/PDCurses/win32/pdckbd.c D payloads/libpayload/curses/PDCurses/win32/pdcscrn.c D payloads/libpayload/curses/PDCurses/win32/pdcsetsc.c D payloads/libpayload/curses/PDCurses/win32/pdcurses.ico D payloads/libpayload/curses/PDCurses/win32/pdcurses.rc D payloads/libpayload/curses/PDCurses/win32/pdcutil.c D payloads/libpayload/curses/PDCurses/win32/pdcwin.h D payloads/libpayload/curses/PDCurses/win32/vcwin32.mak D payloads/libpayload/curses/PDCurses/win32/wccwin32.mak D payloads/libpayload/curses/PDCurses/x11/Makefile.aix.in D payloads/libpayload/curses/PDCurses/x11/Makefile.in D payloads/libpayload/curses/PDCurses/x11/README D payloads/libpayload/curses/PDCurses/x11/ScrollBox.c D payloads/libpayload/curses/PDCurses/x11/ScrollBox.h D payloads/libpayload/curses/PDCurses/x11/ScrollBoxP.h D payloads/libpayload/curses/PDCurses/x11/big_icon.xbm D payloads/libpayload/curses/PDCurses/x11/compose.h D payloads/libpayload/curses/PDCurses/x11/little_icon.xbm D payloads/libpayload/curses/PDCurses/x11/ncurses_cfg.h D payloads/libpayload/curses/PDCurses/x11/pdcclip.c D payloads/libpayload/curses/PDCurses/x11/pdcdisp.c D payloads/libpayload/curses/PDCurses/x11/pdcgetsc.c D payloads/libpayload/curses/PDCurses/x11/pdckbd.c D payloads/libpayload/curses/PDCurses/x11/pdcscrn.c D payloads/libpayload/curses/PDCurses/x11/pdcsetsc.c D payloads/libpayload/curses/PDCurses/x11/pdcutil.c D payloads/libpayload/curses/PDCurses/x11/pdcx11.c D payloads/libpayload/curses/PDCurses/x11/pdcx11.h D payloads/libpayload/curses/PDCurses/x11/sb.c D payloads/libpayload/curses/PDCurses/x11/x11.c D payloads/libpayload/curses/PDCurses/x11/xcurses-config.in 95 files changed, 0 insertions(+), 20,512 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/35429/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b09104f64254d768d27a3d2e3fba8418e7ba2ca Gerrit-Change-Number: 35429 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM
by Kyösti Mälkki (Code Review) 21 Dec '19

21 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30856 Change subject: arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM ...................................................................... arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM This was used to enforce 4kiB alignment of _start16bit in romcc bootblock. Platforms requiring this moved away to C_ENVIRONMENT_BOOTBLOCK that globally forces the alignment. Change-Id: I8ca453bbc56ab2aeb127f3e081c69e1b38bb8396 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Kconfig M src/arch/x86/failover.ld M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/x86/16bit/entry16.inc 7 files changed, 5 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/30856/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 242a7cf..c2fc914 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -81,13 +81,6 @@ default n depends on ARCH_X86 && SMP -# Aligns 16bit entry code in bootblock so that hyper-threading CPUs -# can boot AP CPUs to enable their shared caches. -config SIPI_VECTOR_IN_ROM - bool - default n - depends on ARCH_X86 - # Set the rambase for systems that still need it, only 5 chipsets as of # Sep 2018. This value was 0x100000, chosen to match the entry point # of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index b32aa29..eabc9f7 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -23,12 +23,11 @@ TARGET(binary) SECTIONS { - /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs - * with Startup IPI message without RAM. Align .rom to next 4 byte - * boundary anyway, so no pad byte appears between _rom and _start. + /* Align .rom to 4 byte boundary so no pad byte appears + * between _rom and _start. */ .bogus ROMLOC_MIN : { - . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); + . = ALIGN(4); ROMLOC = .; } >rom = 0xff @@ -49,12 +48,7 @@ * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); - - /* Post-check proper SIPI vector. */ - _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff), - "Address mismatch on AP_SIPI_VECTOR"); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); /DISCARD/ : { *(.comment) diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index fda572d..5c579a1 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -23,10 +23,6 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) -#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) -/* Fixed location, ASSERTED in failover.ld if it changes. */ -.set ap_sipi_vector_in_rom, 0xff -#endif #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index f365cf1..2a324fb 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -7,7 +7,6 @@ select SMP select SSE2 select UDELAY_LAPIC - select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8b227bd..6c3d837 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -13,7 +13,6 @@ select CPU_INTEL_MODEL_1067X select MMX select SSE - select SIPI_VECTOR_IN_ROM config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index ca2f7b3..e860ded 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,7 +9,6 @@ select MMX select SSE select UDELAY_TSC - select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK # mPGA604 are usually Intel Netburst CPUs which should have SSE2 diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 2a9f8c5..f110980 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,8 +29,7 @@ #include <arch/rom_segs.h> -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \ - IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM) +#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ca453bbc56ab2aeb127f3e081c69e1b38bb8396 Gerrit-Change-Number: 30856 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 10

Change in coreboot[master]: Documentation/binaries: Add AMD FSP documentation
by Richard Spiegel (Code Review) 20 Dec '19

20 Dec '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34662 ) Change subject: Documentation/binaries: Add AMD FSP documentation ...................................................................... Documentation/binaries: Add AMD FSP documentation Create a document explaining, at a high level, the differences between Intel's FSP and the one developed by AMD. BUG=none. TEST=none. Change-Id: I59a5d34df93cd0ff647e2ccfdbf8700b4df00a59 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- A Documentation/binaries/AMD_FSP_family_17h.md A Documentation/binaries/index.md 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34662/1 diff --git a/Documentation/binaries/AMD_FSP_family_17h.md b/Documentation/binaries/AMD_FSP_family_17h.md new file mode 100644 index 0000000..b46beb3 --- /dev/null +++ b/Documentation/binaries/AMD_FSP_family_17h.md @@ -0,0 +1,41 @@ +# FSP implementation differences between Intel and AMD + +## Introduction +Starting with family 17h, AMD is developing an "_As Close As Possible_" FSP +binary. However, some premisses are different for family 17h and beyond, +making it necessary to have some FSP implementation differences. Some other +implementation differences were more of an engineering decision. + +The family 17h deviation from older AMD and Intel CPU/SOC are: +* The memory is initialized by the PSP (similar to Intel's ME) ARM. +* There's _**no support**_ for cache as RAM. +* Reset vector is not the old 0xFFFFFFF0. + +This document is a "work in progress", documenting the differences at a +high level. This document will be updated as more information becomes +available. + +## Differences caused by differences in premisses +1. **No FSP-T** +Because family 17h does not support CAR, there's no FSP-T. +2. **FSP-M only reports memory** +Because memory is inittialized by the PSP, FSP-M only reports the final +memory configuration. +3. **FSP-M is loaded to DRAM** +PSP can be made to load a section of the flash into RAM before releasing +the reset, thus FSP-M can be made to run directly from memory. +4. **FSP-M can be made position independent** +Because it's loaded to memory and does not uses CAR, FSP-M can be made PIC +(Position Independent Code). + +## Differences by engineering decision +1. **Memory fragmentation** +Though FSP still fragments memory, it has added control for flexibility +of where the chunks will reside. +2. **UPD interface** +UPD interface uses native intergers and don't need to be packed by compiler. +3. **UPD with no UEFI dependencies** +UPD interface can be made C99 or C11 compatible with no hard dependencies +to UEFI. +4. **Platform specific code** +Similar to AGESA, FSP will make call back to platform specific code. diff --git a/Documentation/binaries/index.md b/Documentation/binaries/index.md new file mode 100644 index 0000000..9093bf7 --- /dev/null +++ b/Documentation/binaries/index.md @@ -0,0 +1,8 @@ +# binaries-specific documentation + +This section contains documentation about any binary used by coreboot + +## Video + +## Platform initialization +- [AMD FSP](AMD_FSP_family_17h.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/34662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59a5d34df93cd0ff647e2ccfdbf8700b4df00a59 Gerrit-Change-Number: 34662 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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