coreboot-gerrit November 2019

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Change in coreboot[master]: src: Remove unused 'include <halt.h>'
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35124 ) Change subject: src: Remove unused 'include <halt.h>' ...................................................................... src: Remove unused 'include <halt.h>' Change-Id: Ic25022bdba15219f79cfe172dc2512c3e18bca70 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/qualcomm/sdm845/aop_load_reset.c M src/southbridge/intel/ibexpeak/smihandler.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/35124/1 diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index 02217f9..e89e132 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -16,7 +16,6 @@ #include <string.h> #include <arch/cache.h> #include <cbfs.h> -#include <halt.h> #include <console/console.h> #include <timestamp.h> #include <soc/mmu.h> diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index a254bd7..e84b4b95 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -23,7 +23,6 @@ #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> #include <elog.h> -#include <halt.h> #include <pc80/mc146818rtc.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <southbridge/intel/common/finalize.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/35124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic25022bdba15219f79cfe172dc2512c3e18bca70 Gerrit-Change-Number: 35124 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: arch/x86: Drop ROMCC sources Kconfig options
by Arthur Heymans (Code Review) 19 Dec '19

19 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37339 ) Change subject: arch/x86: Drop ROMCC sources Kconfig options ...................................................................... arch/x86: Drop ROMCC sources Kconfig options Change-Id: Ia0405fdd448cb31b3c6ca3b3d76e49e9f430bf74 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Kconfig 1 file changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/37339/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index baea9fb..aef71bc 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -157,12 +157,6 @@ Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait for a JTAG debugger to break into the execution sequence. -config BOOTBLOCK_MAINBOARD_INIT - string - -config BOOTBLOCK_NORTHBRIDGE_INIT - string - config BOOTBLOCK_RESETS string @@ -175,9 +169,6 @@ default "src/mainboard/$(MAINBOARDDIR)/cmos.default" depends on HAVE_CMOS_DEFAULT -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - config IOAPIC_INTERRUPTS_ON_FSB bool default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS -- To view, visit https://review.coreboot.org/c/coreboot/+/37339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0405fdd448cb31b3c6ca3b3d76e49e9f430bf74 Gerrit-Change-Number: 37339 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: Drop ROMCC code and header guards
by Arthur Heymans (Code Review) 19 Dec '19

19 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37334 ) Change subject: Drop ROMCC code and header guards ...................................................................... Drop ROMCC code and header guards Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/assembly_entry.S M src/arch/x86/c_start.S M src/arch/x86/include/arch/acpi.h D src/arch/x86/include/arch/bootblock_romcc.h M src/arch/x86/include/arch/cpu.h M src/arch/x86/include/arch/hlt.h M src/arch/x86/include/arch/io.h M src/arch/x86/include/arch/mmio.h D src/arch/x86/include/arch/pci_mmio_cfg_romcc.h M src/arch/x86/include/arch/pci_ops.h M src/commonlib/include/commonlib/cbfs_serialized.h M src/commonlib/include/commonlib/helpers.h M src/console/die.c M src/console/post.c M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/romstage.c M src/cpu/intel/microcode/microcode.c M src/cpu/x86/16bit/entry16.inc M src/drivers/pc80/rtc/mc146818rtc_boot.c M src/include/console/console.h M src/include/console/uart.h M src/include/cpu/amd/mtrr.h M src/include/cpu/x86/cache.h M src/include/cpu/x86/cr.h M src/include/cpu/x86/msr.h M src/include/cpu/x86/mtrr.h M src/include/cpu/x86/tsc.h M src/include/device/device.h M src/include/device/mmio.h M src/include/device/pci_mmio_cfg.h M src/include/device/pci_ops.h M src/include/endian.h M src/include/halt.h M src/include/lib.h M src/include/pc80/mc146818rtc.h M src/include/stdbool.h M src/include/stddef.h M src/include/stdint.h M src/include/string.h M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/ibexpeak/pch.h M src/vendorcode/eltan/security/verified_boot/vboot_check.c 44 files changed, 11 insertions(+), 393 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/37334/1 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 9d6f5a4..fef5ce9 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -13,8 +13,6 @@ #include <rules.h> -#if !CONFIG(ROMCC_BOOTBLOCK) - /* * This path is for stages that are post bootblock. The gdt is reloaded * to accommodate platforms that are executing out of CAR. In order to @@ -60,26 +58,3 @@ /* Expect to never return. */ 1: jmp 1b - -#else - -/* This file assembles the start of the romstage program by the order of the - * includes. Thus, it's extremely important that one pays very careful - * attention to the order of the includes. */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/32bit/entry32.inc> -#include <cpu/x86/fpu_enable.inc> -#if CONFIG(SSE) -#include <cpu/x86/sse_enable.inc> -#endif - -/* - * The assembly.inc is generated based on the requirements of the mainboard. - * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be - * processed by ROMCC and added. In non-ROMCC boards the chipsets' - * cache-as-ram setup files would be here. - */ -#include <generated/assembly.inc> - -#endif diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index bd99c21..8872439 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -148,7 +148,7 @@ .data /* This is the gdt for GCC part of coreboot. - * It is different from the gdt in ROMCC/ASM part of coreboot + * It is different from the gdt in ASM part of coreboot * which is defined in entry32.inc * * When the machine is initially started, we use a very simple diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 479067f..68475c1 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -45,7 +45,7 @@ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) #include <commonlib/helpers.h> #include <device/device.h> #include <uuid.h> diff --git a/src/arch/x86/include/arch/bootblock_romcc.h b/src/arch/x86/include/arch/bootblock_romcc.h deleted file mode 100644 index 827e40e..0000000 --- a/src/arch/x86/include/arch/bootblock_romcc.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/lapic/boot_cpu.c> - -#ifdef CONFIG_BOOTBLOCK_RESETS -#include CONFIG_BOOTBLOCK_RESETS -#endif - -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#endif - -#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT -#include CONFIG_BOOTBLOCK_MAINBOARD_INIT -#else -static void bootblock_mainboard_init(void) -{ -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT - bootblock_northbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT - bootblock_southbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_CPU_INIT - bootblock_cpu_init(); -#endif -} -#endif diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 50d636b..c8cf8c7 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -218,9 +218,6 @@ return CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON); } -#ifndef __ROMCC__ -/* romcc does not support anonymous structs. */ - struct device; struct cpu_device_id { @@ -288,13 +285,11 @@ #define asmlinkage __attribute__((regparm(0))) /* - * When not using a romcc bootblock the car_stage_entry() is the symbol - * jumped to for each stage after bootblock using cache-as-ram. + * The car_stage_entry() is the symbol jumped to for each stage + * after bootblock using cache-as-ram. */ asmlinkage void car_stage_entry(void); -#endif - /* * Get processor id using cpuid eax=1 * return value in EAX register diff --git a/src/arch/x86/include/arch/hlt.h b/src/arch/x86/include/arch/hlt.h index 7b18f55..a3f5c85 100644 --- a/src/arch/x86/include/arch/hlt.h +++ b/src/arch/x86/include/arch/hlt.h @@ -14,16 +14,9 @@ #ifndef ARCH_HLT_H #define ARCH_HLT_H -#if defined(__ROMCC__) -static void hlt(void) -{ - __builtin_hlt(); -} -#else static __always_inline void hlt(void) { asm("hlt"); } -#endif #endif /* ARCH_HLT_H */ diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index d39bbb3..43cfc1b 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -21,39 +21,6 @@ * inb/inw/inl/outb/outw/outl and the "string versions" of the same * (insb/insw/insl/outsb/outsw/outsl). */ -#if defined(__ROMCC__) -static inline void outb(uint8_t value, uint16_t port) -{ - __builtin_outb(value, port); -} - -static inline void outw(uint16_t value, uint16_t port) -{ - __builtin_outw(value, port); -} - -static inline void outl(uint32_t value, uint16_t port) -{ - __builtin_outl(value, port); -} - - -static inline uint8_t inb(uint16_t port) -{ - return __builtin_inb(port); -} - - -static inline uint16_t inw(uint16_t port) -{ - return __builtin_inw(port); -} - -static inline uint32_t inl(uint16_t port) -{ - return __builtin_inl(port); -} -#else static inline void outb(uint8_t value, uint16_t port) { __asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port)); @@ -89,7 +56,6 @@ __asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port)); return value; } -#endif /* __ROMCC__ */ static inline void outsb(uint16_t port, const void *addr, unsigned long count) { diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h index f271a97..efdbe27 100644 --- a/src/arch/x86/include/arch/mmio.h +++ b/src/arch/x86/include/arch/mmio.h @@ -34,13 +34,11 @@ return *((volatile uint32_t *)(addr)); } -#ifndef __ROMCC__ static __always_inline uint64_t read64( const volatile void *addr) { return *((volatile uint64_t *)(addr)); } -#endif static __always_inline void write8(volatile void *addr, uint8_t value) @@ -60,12 +58,10 @@ *((volatile uint32_t *)(addr)) = value; } -#ifndef __ROMCC__ static __always_inline void write64(volatile void *addr, uint64_t value) { *((volatile uint64_t *)(addr)) = value; } -#endif #endif /* __ARCH_MMIO_H__ */ diff --git a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h b/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h deleted file mode 100644 index 36a88f1..0000000 --- a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PCI_MMIO_CFG_ROMCC_H -#define _PCI_MMIO_CFG_ROMCC_H - -#include <stdint.h> -#include <device/mmio.h> -#include <device/pci_type.h> - - -static __always_inline -uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); - return read8(addr); -} - -static __always_inline -uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); - return read16(addr); -} - -static __always_inline -uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); - return read32(addr); -} - -static __always_inline -void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); - write8(addr, value); -} - -static __always_inline -void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); - write16(addr, value); -} - -static __always_inline -void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); - write32(addr, value); -} - -#endif /* _PCI_MMIO_CFG_ROMCC_H */ diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index 4278ed0..e706216 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -15,12 +15,6 @@ #define ARCH_I386_PCI_OPS_H #include <arch/pci_io_cfg.h> - -#if defined(__ROMCC__) -/* Must come before <device/pci_mmio_cfg.h> */ -#include <arch/pci_mmio_cfg_romcc.h> -#endif - #include <device/pci_mmio_cfg.h> #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h index a4708e8..d3a18c6 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/include/commonlib/cbfs_serialized.h @@ -187,11 +187,6 @@ uint32_t alignment; } __packed; -/* - * ROMCC does not understand uint64_t, so we hide future definitions as they are - * unlikely to be ever needed from ROMCC - */ -#ifndef __ROMCC__ /*** Component sub-headers ***/ @@ -236,6 +231,4 @@ uint32_t len; } __packed; -#endif /* __ROMCC__ */ - #endif /* _CBFS_SERIALIZED_H_ */ diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index ca3b3c5..f07b6c2 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -41,13 +41,10 @@ var_a op var_b ? var_a : var_b; \ }) -#ifdef __ROMCC__ /* romcc doesn't support __builtin_choose_expr() */ -#define __CMP(a, b, op) __CMP_UNSAFE(a, b, op) -#else + #define __CMP(a, b, op) __builtin_choose_expr( \ __builtin_constant_p(a) && __builtin_constant_p(b), \ __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) -#endif #ifndef MIN #define MIN(a, b) __CMP(a, b, <) @@ -108,12 +105,8 @@ #define GHz (1000 * MHz) #ifndef offsetof -#ifdef __ROMCC__ -#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) -#else #define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) #endif -#endif #define check_member(structure, member, offset) _Static_assert( \ offsetof(struct structure, member) == offset, \ diff --git a/src/console/die.c b/src/console/die.c index 76c456d..e57c4e4 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -15,8 +15,6 @@ #include <console/console.h> #include <halt.h> -#ifndef __ROMCC__ - /* * The method should be overwritten in mainboard directory to signal that a * fatal error had occurred. On boards that do share the same EC and where the @@ -39,4 +37,3 @@ die_notify(); halt(); } -#endif diff --git a/src/console/post.c b/src/console/post.c index 64aa2a5..8c28ceb 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -24,8 +24,6 @@ /* Write POST information */ -/* someday romcc will be gone. */ -#ifndef __ROMCC__ /* Some mainboards have very nice features beyond just a simple display. * They can override this function. */ @@ -33,11 +31,6 @@ { } -#else -/* This just keeps the number of #ifs to a minimum */ -#define mainboard_post(x) -#endif - #if CONFIG(CMOS_POST) DECLARE_SPIN_LOCK(cmos_post_lock) diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 5a668c4..4dee0a8 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -28,11 +28,8 @@ _cache_as_ram_setup: bootblock_pre_c_entry: - -#if !CONFIG(ROMCC_BOOTBLOCK) movl $cache_as_ram, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ -#endif cache_as_ram: post_code(0x20) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1f8eb9a..bd6a5a9 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -71,19 +71,6 @@ /* We do not return here. */ } -#if CONFIG(ROMCC_BOOTBLOCK) -/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - timestamp_init(base_timestamp); - timestamp_add_now(TS_START_ROMSTAGE); - romstage_main(bist); -} -#endif - - /* We don't carry BIST from bootblock in a good location to read from. * Any error should have been reported in bootblock already. */ diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 80470bf..90138be 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -15,11 +15,7 @@ #include <stdint.h> #include <stddef.h> -#if !defined(__ROMCC__) #include <cbfs.h> -#else -#include <arch/cbfs.h> -#endif #include <arch/cpu.h> #include <console/console.h> #include <cpu/x86/msr.h> @@ -141,22 +137,11 @@ unsigned int x86_model, x86_family; msr_t msr; -#ifdef __ROMCC__ - struct cbfs_file *microcode_file; - - microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); - if (!microcode_file) - return NULL; - - ucode_updates = CBFS_SUBHEADER(microcode_file); - microcode_len = ntohl(microcode_file->len); -#else ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, CBFS_TYPE_MICROCODE, &microcode_len); if (ucode_updates == NULL) return NULL; -#endif /* CPUID sets MSR 0x8B if a microcode update has been loaded. */ msr.lo = 0; @@ -201,8 +186,7 @@ microcode_len -= update_size; } - /* ROMCC doesn't like NULL. */ - return (void *)0; + return NULL; } void intel_update_microcode_from_cbfs(void) diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index e0babd5..f409db0 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,8 +29,6 @@ #include <arch/rom_segs.h> -#if !CONFIG(ROMCC_BOOTBLOCK) || \ - CONFIG(SIPI_VECTOR_IN_ROM) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. */ diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index 0ac06b3..aa3e0f1 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -12,11 +12,7 @@ */ #include <stdint.h> -#ifdef __ROMCC__ -#include <arch/cbfs.h> -#else #include <cbfs.h> -#endif #include <pc80/mc146818rtc.h> #if CONFIG(USE_OPTION_TABLE) #include <option_table.h> @@ -60,12 +56,8 @@ CONFIG(STATIC_OPTION_TABLE)) { size_t length = 128; const unsigned char *cmos_default = -#ifdef __ROMCC__ - walkcbfs("cmos.default"); -#else cbfs_boot_map_with_leak("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT, &length); -#endif if (cmos_default) { size_t i; cmos_disable_rtc(); diff --git a/src/include/console/console.h b/src/include/console/console.h index 607c968..583420c 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -26,8 +26,6 @@ #define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER) #define RAM_SPEW (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER) -#ifndef __ROMCC__ - #include <console/vtxprintf.h> void post_code(u8 value); @@ -101,11 +99,4 @@ int do_vprintk(int msg_level, const char *fmt, va_list args); -#else - -static inline void romcc_printk(void) { } -#define printk(...) romcc_printk() - -#endif /* !__ROMCC__ */ - #endif /* CONSOLE_CONSOLE_H_ */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index aed67c2..162b110 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -55,7 +55,6 @@ uintptr_t uart_platform_base(int idx); -#if !defined(__ROMCC__) static inline void *uart_platform_baseptr(int idx) { return (void *)uart_platform_base(idx); @@ -100,6 +99,4 @@ } #endif -#endif /* __ROMCC__ */ - #endif /* CONSOLE_UART_H */ diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index edbf7bb..906a7c0 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -38,7 +38,7 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) -#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__) #include <cpu/x86/msr.h> diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 713ca32..0331e27 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -23,28 +23,11 @@ #if !defined(__ASSEMBLER__) -/* - * Need two versions because ROMCC chokes on certain clobbers: - * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: - * 0x1559920 asm Internal compiler error: lhs 1 regcm == 0 - */ - -#if defined(__GNUC__) - static inline void wbinvd(void) { asm volatile ("wbinvd" ::: "memory"); } -#else - -static inline void wbinvd(void) -{ - asm volatile ("wbinvd"); -} - -#endif - static inline void invd(void) { asm volatile("invd" ::: "memory"); diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h index 0f14d54..0339aa3 100644 --- a/src/include/cpu/x86/cr.h +++ b/src/include/cpu/x86/cr.h @@ -20,12 +20,7 @@ #include <stdint.h> -/* ROMCC apparently chokes certain clobber registers. */ -#if defined(__ROMCC__) -#define COMPILER_BARRIER -#else #define COMPILER_BARRIER "memory" -#endif #ifdef __x86_64__ #define CRx_TYPE uint64_t diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 2710e7f..63cb8bd 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -81,21 +81,6 @@ #ifndef __ASSEMBLER__ #include <types.h> -#if defined(__ROMCC__) - -typedef __builtin_msr_t msr_t; - -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} - -static void wrmsr(unsigned long index, msr_t msr) -{ - __builtin_wrmsr(index, msr.lo, msr.hi); -} - -#else typedef struct msr_struct { unsigned int lo; @@ -154,7 +139,6 @@ } #endif /* CONFIG_SOC_SETS_MSRS */ -#endif /* __ROMCC__ */ /* Helpers for interpreting MC[i]_STATUS */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 29256c8..0e7a2d1 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -53,7 +53,7 @@ #define MTRR_FIX_4K_F0000 0x26e #define MTRR_FIX_4K_F8000 0x26f -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #include <stdint.h> #include <stddef.h> @@ -140,9 +140,9 @@ "1:" : "=r" (r) : "mr" (x)); return r; } -#endif /* !defined(__ASSEMBLER__) && !defined(__ROMCC__) */ +#endif /* !defined(__ASSEMBLER__) -/* Align up/down to next power of 2, suitable for ROMCC and assembler +/* Align up/down to next power of 2, suitable for assembler too. Range of result 256kB to 128MB is good enough here. */ #define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \ (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index c18f878..6943b93 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -28,7 +28,6 @@ return res; } -#if !defined(__ROMCC__) /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. * This code is used to prevent use of libgcc's umoddi3. */ @@ -42,7 +41,6 @@ tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); } -/* Too many registers for ROMCC */ static inline unsigned long long rdtscll(void) { unsigned long long val; @@ -58,7 +56,6 @@ { return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; } -#endif /* Provided by CPU/chipset code for the TSC rate in MHz. */ unsigned long tsc_freq_mhz(void); diff --git a/src/include/device/device.h b/src/include/device/device.h index abcd0a4..e391291 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -2,13 +2,6 @@ #define DEVICE_H -/* - * NOTICE: Header is ROMCC tentative. - * This header is incompatible with ROMCC and its inclusion leads to 'odd' - * build failures. - */ -#if !defined(__ROMCC__) - #include <device/resource.h> #include <device/path.h> #include <device/pci_type.h> @@ -330,6 +323,4 @@ void scan_generic_bus(struct device *bus); void scan_static_bus(struct device *bus); -#endif /* !defined(__ROMCC__) */ - #endif /* DEVICE_H */ diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index 6596cf8..c2a6b83 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -19,7 +19,6 @@ #include <endian.h> #include <types.h> -#ifndef __ROMCC__ /* * Reads a transfer buffer from 32-bit FIFO registers. fifo_stride is the * distance in bytes between registers (e.g. pass 4 for a normal array of 32-bit @@ -177,6 +176,4 @@ #define READ32_BITFIELD(addr, name) \ EXTRACT_BITFIELD(read32(addr), name) -#endif /* !__ROMCC__ */ - #endif /* __DEVICE_MMIO_H__ */ diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 30945f4..aa15970 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -20,7 +20,6 @@ #include <device/mmio.h> #include <device/pci_type.h> -#if !defined(__ROMCC__) /* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we * prevent some sub-optimal constant folding. */ @@ -110,8 +109,6 @@ return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; } -#endif /* !defined(__ROMCC__) */ - #if CONFIG(MMCONF_SUPPORT) #if CONFIG_MMCONF_BASE_ADDRESS == 0 diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 9d64f03..805c087 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -23,7 +23,6 @@ #include <device/pci_type.h> #include <arch/pci_ops.h> -#ifndef __ROMCC__ void __noreturn pcidev_die(void); static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev) @@ -37,7 +36,6 @@ pcidev_die(); return pcidev_bdf(dev); } -#endif #if defined(__SIMPLE_DEVICE__) #define ENV_PCI_SIMPLE_DEVICE 1 @@ -184,7 +182,6 @@ u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last); u16 pci_s_find_capability(pci_devfn_t dev, u16 cap); -#ifndef __ROMCC__ static __always_inline u16 pci_find_next_capability(const struct device *dev, u16 cap, u16 last) { @@ -196,6 +193,5 @@ { return pci_s_find_capability(PCI_BDF(dev), cap); } -#endif #endif /* PCI_OPS_H */ diff --git a/src/include/endian.h b/src/include/endian.h index 8dc1854..72fb72d 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -84,7 +84,6 @@ #define clrbits_8(addr, clear) clrsetbits_8(addr, clear, 0) #define setbits_8(addr, set) setbits_8(addr, 0, set) -#ifndef __ROMCC__ /* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */ #define DEFINE_ENDIAN_DEC(endian, width) \ static inline uint##width##_t endian##width##dec(const void *p) \ @@ -174,6 +173,5 @@ { return le64_to_cpu(little_endian_64bits); } -#endif #endif diff --git a/src/include/halt.h b/src/include/halt.h index 117c6c0..e2aa11c 100644 --- a/src/include/halt.h +++ b/src/include/halt.h @@ -17,14 +17,10 @@ #ifndef __HALT_H__ #define __HALT_H__ -#ifdef __ROMCC__ -#include <lib/halt.c> -#else /** * halt the system reliably */ void __noreturn halt(void); -#endif /* __ROMCC__ */ /* Power off the system. */ void poweroff(void); diff --git a/src/include/lib.h b/src/include/lib.h index 098d62d..d1bbe93 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -57,14 +57,12 @@ */ size_t hexstrtobin(const char *str, uint8_t *buf, size_t len); -#if !defined(__ROMCC__) /* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } /* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(1) == 0, __ffs(0) == -1, __ffs(1<<31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } -#endif /* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 6fa5e46..d1ade20 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -178,7 +178,6 @@ cmos_write((value >> (i << 3)) & 0xff, offset + i); } -#if !defined(__ROMCC__) void cmos_init(bool invalid); void cmos_check_update_date(void); @@ -187,9 +186,6 @@ unsigned int read_option_lowlevel(unsigned int start, unsigned int size, unsigned int def); -#else /* defined(__ROMCC__) */ -#include <drivers/pc80/rtc/mc146818rtc_romcc.c> -#endif /* !defined(__ROMCC__) */ #define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, \ CMOS_VLEN_ ##name, (default)) diff --git a/src/include/stdbool.h b/src/include/stdbool.h index 2eeb70e..d7f9e64 100644 --- a/src/include/stdbool.h +++ b/src/include/stdbool.h @@ -5,11 +5,8 @@ #include <stdint.h> -#ifdef __ROMCC__ -typedef uint8_t bool; -#else + typedef _Bool bool; -#endif #define true 1 #define false 0 diff --git a/src/include/stddef.h b/src/include/stddef.h index a2c9c50..e318309 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -47,12 +47,10 @@ #define MAYBE_STATIC_BSS #endif -#ifndef __ROMCC__ /* Provide a pointer to address 0 that thwarts any "accessing this is * undefined behaviour and do whatever" trickery in compilers. * Use when you _really_ need to read32(zeroptr) (ie. read address 0). */ extern char zeroptr[]; -#endif #endif /* STDDEF_H */ diff --git a/src/include/stdint.h b/src/include/stdint.h index 67b0b0b..b534add 100644 --- a/src/include/stdint.h +++ b/src/include/stdint.h @@ -28,17 +28,14 @@ typedef signed int int32_t; typedef unsigned int uint32_t; -#ifndef __ROMCC__ typedef signed long long int64_t; typedef unsigned long long uint64_t; -#endif /* Types for 'void *' pointers */ typedef signed long intptr_t; typedef unsigned long uintptr_t; /* Ensure that the widths are all correct */ -#ifndef __ROMCC__ _Static_assert(sizeof(int8_t) == 1, "Size of int8_t is incorrect"); _Static_assert(sizeof(uint8_t) == 1, "Size of uint8_t is incorrect"); @@ -53,13 +50,10 @@ _Static_assert(sizeof(intptr_t) == sizeof(void *), "Size of intptr_t is incorrect"); _Static_assert(sizeof(uintptr_t) == sizeof(void *), "Size of uintptr_t is incorrect"); -#endif /* Maximum width integer types */ -#ifndef __ROMCC__ typedef int64_t intmax_t; typedef uint64_t uintmax_t; -#endif /* Convenient typedefs */ typedef int8_t s8; @@ -71,10 +65,8 @@ typedef int32_t s32; typedef uint32_t u32; -#ifndef __ROMCC__ typedef int64_t s64; typedef uint64_t u64; -#endif /* Limits of integer types */ #define INT8_MIN ((int8_t)0x80) @@ -89,16 +81,12 @@ #define INT32_MAX ((int32_t)0x7FFFFFFF) #define UINT32_MAX ((uint32_t)0xFFFFFFFF) -#ifndef __ROMCC__ #define INT64_MIN ((int64_t)0x8000000000000000) #define INT64_MAX ((int64_t)0x7FFFFFFFFFFFFFFF) #define UINT64_MAX ((uint64_t)0xFFFFFFFFFFFFFFFF) -#endif -#ifndef __ROMCC__ #define INTMAX_MIN INT64_MIN #define INTMAX_MAX INT64_MAX #define UINTMAX_MAX UINT64_MAX -#endif #endif /* STDINT_H */ diff --git a/src/include/string.h b/src/include/string.h index d3f09ff..bcfc111 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -4,9 +4,7 @@ #include <stddef.h> #include <stdlib.h> -#if !defined(__ROMCC__) #include <console/vtxprintf.h> -#endif /* Stringify a token */ #ifndef STRINGIFY @@ -19,10 +17,8 @@ void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); void *memchr(const void *s, int c, size_t n); -#if !defined(__ROMCC__) int snprintf(char *buf, size_t size, const char *fmt, ...); int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); -#endif char *strdup(const char *s); char *strconcat(const char *s1, const char *s2); size_t strnlen(const char *src, size_t max); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 127fb61..089d458 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -90,10 +90,8 @@ int oc_pin; }; -#ifndef __ROMCC__ void pch_enable(struct device *dev); extern const struct southbridge_usb_port mainboard_usb_ports[14]; -#endif void early_usb_init(const struct southbridge_usb_port *portmap); diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 77931cb..d35b215 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,10 +19,8 @@ #if !defined(__ACPI__) -#ifndef __ROMCC__ #include <device/device.h> void i82371eb_enable(struct device *dev); -#endif void i82371eb_hard_reset(void); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3d27faa..0516a7a 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -34,10 +34,8 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#ifndef __ROMCC__ #include <device/device.h> void i82801gx_enable(struct device *dev); -#endif void enable_smbus(void); void i82801gx_lpc_setup(void); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 9ee76f2..5785ef1 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -89,11 +89,9 @@ void early_usb_init(const struct southbridge_usb_port *portmap); -#ifndef __ROMCC__ extern const struct southbridge_usb_port mainboard_usb_ports[14]; #include <device/device.h> void pch_enable(struct device *dev); -#endif #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index bc502c9..461a847 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -276,13 +276,6 @@ { printk(BIOS_SPEW, "%s: processing early items\n", __func__); - if (CONFIG(ROMCC_BOOTBLOCK) && - CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST)) { - printk(BIOS_SPEW, "%s: check the manifest\n", __func__); - if (verified_boot_check_manifest() != 0) - die("invalid manifest"); - } - if (CONFIG(VENDORCODE_ELTAN_MBOOT)) { printk(BIOS_DEBUG, "mb_measure returned 0x%x\n", mb_measure(vboot_platform_is_resuming())); -- To view, visit https://review.coreboot.org/c/coreboot/+/37334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Gerrit-Change-Number: 37334 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: src/vendorcode: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33682 Change subject: src/vendorcode: Use 'include <stdlib.h>' when appropriate ...................................................................... src/vendorcode: Use 'include <stdlib.h>' when appropriate Change-Id: I70029700bfb297ac06561056da730731a2ca1e8b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c M src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c M src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c M src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c 4 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33682/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c index 8e348d0..8616fb6 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c @@ -12,6 +12,7 @@ #include <bdk.h> #include <libbdk-hal/bdk-config.h> +#include <stdlib.h> #include <string.h> #include <assert.h> #include <lame_string.h> diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c index f7d631f..c6017b2 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c @@ -37,7 +37,9 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include <bdk.h> +#include <stdlib.h> #include <string.h> + #include "libbdk-arch/bdk-csrs-gser.h" #include "libbdk-arch/bdk-csrs-gsern.h" #include "libbdk-hal/if/bdk-if.h" diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c index 0df70eb..ed003dc 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c @@ -36,8 +36,11 @@ * QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ + #include <bdk.h> #include <string.h> +#include <stdlib.h> + #include "libbdk-arch/bdk-csrs-ap.h" #include "libbdk-arch/bdk-csrs-pccpf.h" #include "libbdk-hal/bdk-ecam.h" diff --git a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c index 385acee..e3fc993 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c @@ -40,6 +40,7 @@ #include "dram-internal.h" #include <string.h> +#include <stdlib.h> #include <lame_string.h> /* for strtoul */ #include <libbdk-hal/bdk-atomic.h> #include <libbdk-hal/bdk-clock.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70029700bfb297ac06561056da730731a2ca1e8b Gerrit-Change-Number: 33682 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: vendorcode/cavium/bdk/libbdk-hal/device: Add missing <stdlib.h>
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37380 ) Change subject: vendorcode/cavium/bdk/libbdk-hal/device: Add missing <stdlib.h> ...................................................................... vendorcode/cavium/bdk/libbdk-hal/device: Add missing <stdlib.h> Change-Id: I64876a2b6cffdabf3e365fc07017adb14f086ecc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37380/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c index 0df70eb..21e43a4 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c @@ -37,6 +37,7 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include <bdk.h> +#include <stdlib.h> #include <string.h> #include "libbdk-arch/bdk-csrs-ap.h" #include "libbdk-arch/bdk-csrs-pccpf.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/37380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64876a2b6cffdabf3e365fc07017adb14f086ecc Gerrit-Change-Number: 37380 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: vendorcode/cavium/bdk/libbdk-hal: Add missing <stdlib.h>
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37377 ) Change subject: vendorcode/cavium/bdk/libbdk-hal: Add missing <stdlib.h> ...................................................................... vendorcode/cavium/bdk/libbdk-hal: Add missing <stdlib.h> Change-Id: Id52603c525cce1bead423d188e23f6efd50511a9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/37377/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c index e078e74..cc6a5dd 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c @@ -12,6 +12,7 @@ #include <bdk.h> #include <libbdk-hal/bdk-config.h> +#include <stdlib.h> #include <string.h> #include <assert.h> #include <lame_string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id52603c525cce1bead423d188e23f6efd50511a9 Gerrit-Change-Number: 37377 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: src: Remove unused 'include <bootblock_common.h>
by HAOUAS Elyes (Code Review) 18 Dec '19

18 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37271 ) Change subject: src: Remove unused 'include <bootblock_common.h> ...................................................................... src: Remove unused 'include <bootblock_common.h> Change-Id: I9eedae837634beb5a545d97fdf9c1810faba5138 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/emulation/qemu-power8/bootblock.c M src/mainboard/google/cheza/mainboard.c M src/mainboard/google/mistral/mainboard.c M src/mainboard/google/trogdor/mainboard.c M src/soc/intel/apollolake/fspcar.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/skylake/fspcar.c 7 files changed, 2 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/37271/1 diff --git a/src/mainboard/emulation/qemu-power8/bootblock.c b/src/mainboard/emulation/qemu-power8/bootblock.c index ec30c87..d59ab37 100644 --- a/src/mainboard/emulation/qemu-power8/bootblock.c +++ b/src/mainboard/emulation/qemu-power8/bootblock.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <bootblock_common.h> #include <console/console.h> #include <program_loading.h> diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c index 7a19d32..804906a 100644 --- a/src/mainboard/google/cheza/mainboard.c +++ b/src/mainboard/google/cheza/mainboard.c @@ -14,7 +14,6 @@ */ #include <device/device.h> -#include <bootblock_common.h> #include <gpio.h> #include <soc/usb.h> diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index d50758c..e36a1c7 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -14,7 +14,6 @@ */ #include <device/device.h> -#include <bootblock_common.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/usb.h> diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index ce03ce1..4df87e5 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -14,7 +14,6 @@ */ #include <device/device.h> -#include <bootblock_common.h> #include <arch/mmio.h> #include <gpio.h> #include <timestamp.h> diff --git a/src/soc/intel/apollolake/fspcar.c b/src/soc/intel/apollolake/fspcar.c index a284116..40bacd7 100644 --- a/src/soc/intel/apollolake/fspcar.c +++ b/src/soc/intel/apollolake/fspcar.c @@ -13,7 +13,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <bootblock_common.h> + #include <FsptUpd.h> const FSPT_UPD temp_ram_init_params = { diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 96218f4..6294b8a 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <arch/cbfs.h> #include <arch/romstage.h> -#include <bootblock_common.h> #include <bootmode.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c index 0d27f57..4e8b5e7 100644 --- a/src/soc/intel/skylake/fspcar.c +++ b/src/soc/intel/skylake/fspcar.c @@ -13,7 +13,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <bootblock_common.h> + #include <FsptUpd.h> const FSPT_UPD temp_ram_init_params = { -- To view, visit https://review.coreboot.org/c/coreboot/+/37271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9eedae837634beb5a545d97fdf9c1810faba5138 Gerrit-Change-Number: 37271 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: AGESA: Fix discovery of IO APICs number
by Krystian Hebel (Code Review) 18 Dec '19

18 Dec '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34589 ) Change subject: AGESA: Fix discovery of IO APICs number ...................................................................... AGESA: Fix discovery of IO APICs number Number of IO APICs are hardcoded. This fix reads this number from the default values obtained by creating a structure for a parameter block of an AGESA. While it is possible to modify NumberOfIoApics in callouts, every platform currently in the tree goes with the default value. Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: Ib3ddfe606720143659e57fbbca7f7a3e655a7664 --- M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c 4 files changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/34589/1 diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 750d192..7964f4e 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -297,6 +297,23 @@ return (final < AGESA_FATAL) ? 0 : -1; } +int amd_get_ioapic_num(void) { + AMD_INTERFACE_PARAMS aip; + AMD_EARLY_PARAMS *params; + int ret; + + agesa_locate_image(&aip.StdHeader); + + amd_create_struct(&aip, AMD_INIT_EARLY, NULL, 0); + + params = (AMD_EARLY_PARAMS *)aip.NewStructPtr; + ret = params->PlatformConfig.NumberOfIoApics; + + amd_release_struct(&aip); + + return ret; +} + #if ENV_RAMSTAGE static void amd_bs_ramstage_init(void *arg) diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index 17819e9..97eba2f 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -39,6 +39,8 @@ void amd_initmmio(void); void amd_initenv(void); +int amd_get_ioapic_num(void); + void *GetHeapBase(void); void EmptyHeap(void); diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c6457a3..e9a1e05 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -870,7 +870,7 @@ * for their APIC id and therefore must reside at 0..15 */ - u8 plat_num_io_apics = 3; /* FIXME */ + u8 plat_num_io_apics = amd_get_ioapic_num(); if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 928d9d2..b3b68f9 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -896,7 +896,7 @@ * for their APIC id and therefore must reside at 0..15 */ - u8 plat_num_io_apics = 3; /* FIXME */ + u8 plat_num_io_apics = amd_get_ioapic_num(); if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; -- To view, visit https://review.coreboot.org/c/coreboot/+/34589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3ddfe606720143659e57fbbca7f7a3e655a7664 Gerrit-Change-Number: 34589 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

7 14

Change in coreboot[master]: mb/emulate/qemu-q35: Drop unused romcc-related Kconfig
by Arthur Heymans (Code Review) 17 Dec '19

17 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37338 ) Change subject: mb/emulate/qemu-q35: Drop unused romcc-related Kconfig ...................................................................... mb/emulate/qemu-q35: Drop unused romcc-related Kconfig Change-Id: Ib4adbd3f6e850ced1cb93e47ce4f45249dc032c5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-q35/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/37338/1 diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 3a9bb6f..ee430d0 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -47,10 +47,6 @@ string default "QEMU x86 q35/ich9" -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/emulation/qemu-q35/bootblock.c" - config MMCONF_BASE_ADDRESS hex default 0xb0000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/37338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4adbd3f6e850ced1cb93e47ce4f45249dc032c5 Gerrit-Change-Number: 37338 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: TEST-ONLY: add support anx7625 driver
by jitao shi (Code Review) 17 Dec '19

17 Dec '19

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35623 ) Change subject: TEST-ONLY: add support anx7625 driver ...................................................................... TEST-ONLY: add support anx7625 driver Change-Id: I02ef29798b0257632e0750f09a4390b3d0226367 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- A src/drivers/analogix/anx7625/Kconfig A src/drivers/analogix/anx7625/Makefile.inc A src/drivers/analogix/anx7625/anx7625.c A src/drivers/analogix/anx7625/anx7625.h M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Makefile.inc A src/mainboard/google/kukui/panel_anx7625.c 7 files changed, 1,423 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35623/1 diff --git a/src/drivers/analogix/anx7625/Kconfig b/src/drivers/analogix/anx7625/Kconfig new file mode 100644 index 0000000..afe0338 --- /dev/null +++ b/src/drivers/analogix/anx7625/Kconfig @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2019 Analogix Semiconductor. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config DRIVER_ANALOGIX_ANX7625 + bool + default n + help + Analogix anx7625 MIPI DSI to eDP Converter diff --git a/src/drivers/analogix/anx7625/Makefile.inc b/src/drivers/analogix/anx7625/Makefile.inc new file mode 100644 index 0000000..9a46338 --- /dev/null +++ b/src/drivers/analogix/anx7625/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2019 Analogix Semiconductor. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += anx7625.c diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c new file mode 100644 index 0000000..676872b --- /dev/null +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -0,0 +1,948 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Analogix Semiconductor. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <device/i2c_simple.h> +#include <edid.h> +#include <console/console.h> +#include <timer.h> +#include <string.h> + +#include "anx7625.h" + +/* + * there is a sync issue while access I2C register between AP(CPU) and + * internal firmware(OCM), to avoid the race condition, AP should access + * the reserved slave address before slave address occurs changes. + */ +static int i2c_access_workaround(uint8_t bus, uint8_t saddr) +{ + uint8_t offset; + static uint8_t saddr_backup = 0; + int ret = 0; + + if (saddr != saddr_backup) { + saddr_backup = saddr; + + if (saddr == TCPC_INTERFACE_ADDR) + offset = RSVD_00_ADDR; + else if (saddr == TX_P0_ADDR) + offset = RSVD_D1_ADDR; + else if (saddr == TX_P1_ADDR) + offset = RSVD_60_ADDR; + else if (saddr == RX_P0_ADDR) + offset = RSVD_39_ADDR; + else if (saddr == RX_P1_ADDR) + offset = RSVD_7F_ADDR; + else + offset = RSVD_00_ADDR; + + ret = i2c_writeb(bus, saddr, offset, 0x00); + if (ret < 0) + printk(BIOS_INFO, "failed to access i2c %x\n:%x", + saddr, offset); + } + + return ret; +} + +static int anx7625_reg_read(uint8_t bus, uint8_t saddr, + uint8_t offset, uint8_t *val) +{ + int ret; + + i2c_access_workaround(bus, saddr); + + ret = i2c_readb(bus, saddr, offset, val); + if (ret < 0) { + printk(BIOS_INFO, "read i2c failed id=%x:%x\n", + saddr, offset); + return ret; + } + + return *val; +} + +static int anx7625_reg_block_read(uint8_t bus, uint8_t saddr, + uint8_t reg_addr, uint8_t len, uint8_t *buf) +{ + int ret; + + i2c_access_workaround(bus, saddr); + + ret = i2c_read_bytes(bus, saddr, reg_addr, buf, len); + if (ret < 0) + printk(BIOS_INFO, "read i2c block failed id=%x:%x\n", + saddr, reg_addr); + + return ret; +} + +static int anx7625_reg_write(uint8_t bus, uint8_t saddr, + uint8_t reg_addr, uint8_t reg_val) +{ + int ret; + + i2c_access_workaround(bus, saddr); + + ret = i2c_writeb(bus, saddr, reg_addr, reg_val); + + if (ret < 0) + printk(BIOS_INFO, "failed to write i2c id=%x\n:%x", + saddr, reg_addr); + + return ret; +} + +static int anx7625_write_or(uint8_t bus, uint8_t saddr, + uint8_t offset, uint8_t mask) +{ + uint8_t val; + int ret; + + ret = anx7625_reg_read(bus, saddr, offset, &val); + + return (ret < 0) ? ret : anx7625_reg_write(bus, saddr, + offset, (val | (mask))); +} + +static int anx7625_write_and(uint8_t bus, uint8_t saddr, + uint8_t offset, uint8_t mask) +{ + int ret; + uint8_t val; + + ret = anx7625_reg_read(bus, saddr, offset, &val); + + return (ret < 0) ? ret : anx7625_reg_write(bus, saddr, + offset, (val & (mask))); +} + +static int wait_aux_op_finish(uint8_t bus) +{ + uint8_t val; + int ret; + int loop; + + ret = -1; + for (loop = 0; loop < 150; loop++) { + mdelay(2); + anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, &val); + if (!(val & AP_AUX_CTRL_OP_EN)) { + ret = 0; + break; + } + } + + if (ret != 0) { + printk(BIOS_INFO, "wait aux operation failed.\n"); + } else { + ret = anx7625_reg_read(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, &val); + if ((ret < 0) || (val & 0x0F)) { + printk(BIOS_INFO, "aux status %02x\n", val); + ret = -1; + } + } + + return ret; +} + +static unsigned long gcd(unsigned long a, unsigned long b) +{ + unsigned long iterations = 0L; + + if (a == 0) + return b; + + while (b != 0) { + if (a > b) + a = a - b; + else + b = b - a; + iterations++; + } + + return a; +} + +/* reduction of fraction a/b */ +static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) +{ + unsigned long gcd_num; + unsigned long tmp_a, tmp_b; + u32 i = 1; + + gcd_num = gcd(*a, *b); + *a /= gcd_num; + *b /= gcd_num; + + tmp_a = *a; + tmp_b = *b; + + while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { + i++; + *a = tmp_a / i; + *b = tmp_b / i; + } + + /* + * in the end, make a, b larger to have higher ODFC PLL + * output frequency accuracy + */ + while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { + *a <<= 1; + *b <<= 1; + } + + *a >>= 1; + *b >>= 1; +} + +static int anx7625_calculate_m_n(u32 pixelclock, + unsigned long *m, unsigned long *n, uint8_t *post_divider) +{ + if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { + /* pixel clock frequency is too high */ + printk(BIOS_INFO, "pixelclock too high, act(%d), maximum(%lu)\n", + pixelclock, + PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); + return 1; + } + + if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { + /* pixel clock frequency is too low */ + printk(BIOS_INFO, "pixelclock too low, act(%d), maximum(%lu)\n", + pixelclock, + PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); + return 1; + } + + *post_divider = 1; + + for (*post_divider = 1; + pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) + *post_divider += 1; + + if (*post_divider > POST_DIVIDER_MAX) { + for (*post_divider = 1; + (pixelclock < + (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) + *post_divider += 1; + + if (*post_divider > POST_DIVIDER_MAX) { + printk(BIOS_INFO, "cannot find property post_divider(%d)\n", + *post_divider); + return 1; + } + } + + /* patch to improve the accuracy */ + if (*post_divider == 7) { + /* 27,000,000 is not divisible by 7 */ + *post_divider = 8; + } else if (*post_divider == 11) { + /* 27,000,000 is not divisible by 11 */ + *post_divider = 12; + } else if ((*post_divider == 13) || (*post_divider == 14)) { + /*27,000,000 is not divisible by 13 or 14*/ + *post_divider = 15; + } + + if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { + printk(BIOS_INFO, "act clock(%u) large than maximum(%lu)\n", + pixelclock * (*post_divider), + PLL_OUT_FREQ_ABS_MAX); + return 1; + } + + + *m = pixelclock * 599 / 600; + *n = XTAL_FRQ / (*post_divider); + + anx7625_reduction_of_a_fraction(m, n); + + return 0; +} + +static int anx7625_odfc_config(uint8_t bus, uint8_t post_divider) +{ + int ret; + + /* config input reference clock frequency 27MHz/19.2MHz */ + ret = anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_16, + ~(REF_CLK_27000kHz << MIPI_FREF_D_IND)); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_16, + (REF_CLK_27000kHz << MIPI_FREF_D_IND)); + /* post divider */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_8, 0x0f); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_8, + post_divider << 4); + + /* add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7, + ~MIPI_PLL_VCO_TUNE_REG_VAL); + + /* reset ODFC PLL */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7, + ~MIPI_PLL_RESET_N); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7, + MIPI_PLL_RESET_N); + + if (ret < 0) + printk(BIOS_INFO, "IO error.\n"); + + return ret; +} + +static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt) +{ + unsigned long m, n; + u16 htotal; + int ret; + uint8_t post_divider = 0; + + ret = anx7625_calculate_m_n(dt->pixelclock * 1000, + &m, &n, &post_divider); + + if (ret != 0) { + printk(BIOS_INFO, "cannot get property m n value.\n"); + return -1; + } + + printk(BIOS_INFO, "compute M(%lu), N(%lu), divider(%d).\n", + m, n, post_divider); + + /* configure pixel clock */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, PIXEL_CLOCK_L, + (dt->pixelclock / 1000) & 0xFF); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, PIXEL_CLOCK_H, + (dt->pixelclock / 1000) >> 8); + /* lane count */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, + MIPI_LANE_CTRL_0, 0xfc); + + ret |= anx7625_write_or(bus, RX_P1_ADDR, + MIPI_LANE_CTRL_0, 3); + + /* Htotal */ + htotal = dt->hactive + dt->hfront_porch + + dt->hback_porch + dt->hsync_len; + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); + /* Hactive */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_ACTIVE_PIXELS_L, dt->hactive & 0xFF); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_ACTIVE_PIXELS_H, dt->hactive >> 8); + /* HFP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_FRONT_PORCH_L, dt->hfront_porch); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_FRONT_PORCH_H, + dt->hfront_porch >> 8); + /* HWS */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_SYNC_WIDTH_L, dt->hsync_len); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_SYNC_WIDTH_H, dt->hsync_len >> 8); + /* HBP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_BACK_PORCH_L, dt->hback_porch); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_BACK_PORCH_H, dt->hback_porch >> 8); + /* Vactive */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, ACTIVE_LINES_L, + dt->vactive); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, ACTIVE_LINES_H, + dt->vactive >> 8); + /* VFP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + VERTICAL_FRONT_PORCH, dt->vfront_porch); + /* VWS */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + VERTICAL_SYNC_WIDTH, dt->vsync_len); + /* VBP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + VERTICAL_BACK_PORCH, dt->vback_porch); + /* M value */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_M_NUM_7_0, (m & 0xff)); + /* N value */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_PLL_N_NUM_7_0, + (n & 0xff)); + /* diff */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_DIGITAL_ADJ_1, 0x37); + + ret |= anx7625_odfc_config(bus, post_divider - 1); + + if (ret < 0) + printk(BIOS_INFO, "mipi dsi setup IO error.\n"); + + return ret; +} + +static int anx7625_swap_dsi_lane3(uint8_t bus) +{ + int ret; + uint8_t val; + + /* swap MIPI-DSI data lane 3 P and N */ + ret = anx7625_reg_read(bus, RX_P1_ADDR, MIPI_SWAP, &val); + if (ret < 0) { + printk(BIOS_INFO, "IO error : access MIPI_SWAP.\n"); + return -1; + } + + val |= (1 << MIPI_SWAP_CH3); + return anx7625_reg_write(bus, RX_P1_ADDR, MIPI_SWAP, val); +} + +static int anx7625_api_dsi_config(uint8_t bus, struct display_timing *dt) + +{ + int val, ret; + + /* swap MIPI-DSI data lane 3 P and N */ + ret = anx7625_swap_dsi_lane3(bus); + if (ret < 0) { + printk(BIOS_INFO, "IO error : swap dsi lane 3 failed.\n"); + return ret; + } + + /* DSI clock settings */ + val = (0 << MIPI_HS_PWD_CLK) | + (0 << MIPI_HS_RT_CLK) | + (0 << MIPI_PD_CLK) | + (1 << MIPI_CLK_RT_MANUAL_PD_EN) | + (1 << MIPI_CLK_HS_MANUAL_PD_EN) | + (0 << MIPI_CLK_DET_DET_BYPASS) | + (0 << MIPI_CLK_MISS_CTRL) | + (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); + ret = anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PHY_CONTROL_3, val); + + /* + * Decreased HS prepare tg delay from 160ns to 80ns work with + * a) Dragon board 810 series (Qualcomm AP) + * b) Moving Pixel DSI source (PG3A pattern generator + + * P332 D-PHY Probe) default D-PHY tg + * 5ns/step + */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_TIME_HS_PRPR, 0x10); + + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_18, + SELECT_DSI<<MIPI_DPI_SELECT); /* enable DSI mode*/ + + ret |= anx7625_dsi_video_config(bus, dt); + if (ret < 0) { + printk(BIOS_INFO, "dsi video tg config failed\n"); + return ret; + } + + /* toggle m, n ready */ + ret = anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_6, + ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); + mdelay(1); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_6, + MIPI_M_NUM_READY | MIPI_N_NUM_READY); + + /* configure integer stable register */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_VIDEO_STABLE_CNT, 0x02); + /* power on MIPI RX */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_LANE_CTRL_10, 0x00); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_LANE_CTRL_10, 0x80); + + if (ret < 0) + printk(BIOS_INFO, "IO error : mipi dsi enable init failed.\n"); + + return ret; +} + +static int anx7625_dsi_config(uint8_t bus, struct display_timing *dt) +{ + int ret; + + printk(BIOS_INFO, "config dsi.\n"); + + /* DSC disable */ + ret = anx7625_write_and(bus, RX_P0_ADDR, + R_DSC_CTRL_0, ~DSC_EN); + + ret |= anx7625_api_dsi_config(bus, dt); + + if (ret < 0) { + printk(BIOS_INFO, "IO error : api dsi config error.\n"); + } else { + /* set MIPI RX EN */ + ret = anx7625_write_or(bus, RX_P0_ADDR, + AP_AV_STATUS, AP_MIPI_RX_EN); + /* clear mute flag */ + ret |= anx7625_write_and(bus, RX_P0_ADDR, + AP_AV_STATUS, ~AP_MIPI_MUTE); + if (ret < 0) + printk(BIOS_INFO, "IO error : enable mipi rx failed.\n"); + else + printk(BIOS_INFO, "success to config DSI\n"); + } + + return ret; +} + +static int sp_tx_rst_aux(uint8_t bus) +{ + int ret; + + ret = anx7625_write_or(bus, TX_P2_ADDR, RST_CTRL2, + AUX_RST); + ret |= anx7625_write_and(bus, TX_P2_ADDR, RST_CTRL2, + ~AUX_RST); + return ret; +} + +static int sp_tx_aux_wr(uint8_t bus, uint8_t offset) +{ + int ret; + + ret = anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, offset); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_COMMAND, 0x04); + ret |= anx7625_write_or(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); + return (ret | wait_aux_op_finish(bus)); +} + +static int sp_tx_aux_rd(uint8_t bus, uint8_t len_cmd) +{ + int ret; + + ret = anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_COMMAND, len_cmd); + ret |= anx7625_write_or(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); + return (ret | wait_aux_op_finish(bus)); +} + +static int sp_tx_get_edid_block(uint8_t bus) +{ + int ret = 0; + uint8_t val = 0; + + sp_tx_aux_wr(bus, 0x7e); + sp_tx_aux_rd(bus, 0x01); + ret = anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_BUFF_START, &val); + if (ret < 0) { + printk(BIOS_INFO, "IO error : access AUX BUFF.\n"); + return -1; + } + + printk(BIOS_INFO, " EDID Block = %d\n", val + 1); + + if (val > 3) + val = 1; + + return val; +} + +static int edid_read(uint8_t bus, + uint8_t offset, uint8_t *pblock_buf) +{ + uint8_t c, cnt = 0; + + c = 0; + for (cnt = 0; cnt < 3; cnt++) { + sp_tx_aux_wr(bus, offset); + /* set I2C read com 0x01 mot = 0 and read 16 bytes */ + c = sp_tx_aux_rd(bus, 0xf1); + + if (c == 1) { + sp_tx_rst_aux(bus); + printk(BIOS_INFO, "edid read failed, reset!\n"); + cnt++; + } else { + anx7625_reg_block_read(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, + MAX_DPCD_BUFFER_SIZE, pblock_buf); + return 0; + } + } + + return 1; + +} + +static int segments_edid_read(uint8_t bus, + uint8_t segment, uint8_t *buf, uint8_t offset) +{ + uint8_t c, cnt = 0; + int ret; + + /* write address only */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_ADDR_7_0, 0x30); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_COMMAND, 0x04); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, + AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); + + ret |= wait_aux_op_finish(bus); + /* write segment address */ + ret |= sp_tx_aux_wr(bus, segment); + /* data read */ + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_ADDR_7_0, 0x50); + if (ret < 0) { + printk(BIOS_INFO, "IO error : aux initial failed.\n"); + return ret; + } + + for (cnt = 0; cnt < 3; cnt++) { + sp_tx_aux_wr(bus, offset); + /* set I2C read com 0x01 mot = 0 and read 16 bytes */ + c = sp_tx_aux_rd(bus, 0xf1); + + if (c == 1) { + ret = sp_tx_rst_aux(bus); + printk(BIOS_INFO, "segment read failed, reset!\n"); + cnt++; + } else { + ret = anx7625_reg_block_read(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, + MAX_DPCD_BUFFER_SIZE, buf); + return ret; + } + } + + return ret; +} + +static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf) +{ + uint8_t offset, edid_pos; + int count, blocks_num; + uint8_t pblock_buf[MAX_DPCD_BUFFER_SIZE]; + uint8_t i, j; + uint8_t g_edid_break = 0; + int ret; + + /* address initial */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_ADDR_7_0, 0x50); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_ADDR_15_8, 0); + ret |= anx7625_write_and(bus, RX_P0_ADDR, + AP_AUX_ADDR_19_16, 0xf0); + if (ret < 0) { + printk(BIOS_INFO, "access aux channel IO error.\n"); + return -1; + } + + blocks_num = sp_tx_get_edid_block(bus); + if (blocks_num < 0) + return blocks_num; + + count = 0; + + do { + switch (count) { + case 0: + case 1: + for (i = 0; i < 8; i++) { + offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; + g_edid_break = edid_read(bus, offset, + pblock_buf); + + if (g_edid_break == 1) + break; + + memcpy(&pedid_blocks_buf[offset], + pblock_buf, + MAX_DPCD_BUFFER_SIZE); + } + + break; + case 2: + offset = 0x00; + + for (j = 0; j < 8; j++) { + edid_pos = (j + count * 8) * + MAX_DPCD_BUFFER_SIZE; + + if (g_edid_break == 1) + break; + + segments_edid_read(bus, count / 2, + pblock_buf, offset); + memcpy(&pedid_blocks_buf[edid_pos], + pblock_buf, + MAX_DPCD_BUFFER_SIZE); + offset = offset + 0x10; + } + + break; + case 3: + offset = 0x80; + + for (j = 0; j < 8; j++) { + edid_pos = (j + count * 8) * + MAX_DPCD_BUFFER_SIZE; + if (g_edid_break == 1) + break; + + segments_edid_read(bus, count / 2, + pblock_buf, offset); + memcpy(&pedid_blocks_buf[edid_pos], + pblock_buf, + MAX_DPCD_BUFFER_SIZE); + offset = offset + 0x10; + } + + break; + default: + break; + } + + count++; + + } while (blocks_num >= count); + + /* reset aux channel */ + sp_tx_rst_aux(bus); + + return blocks_num; +} + +static void anx7625_power_on(void) +{ +#ifdef ANXGPIO + /* power on pin enable */ + gpio_set_value(gpio_p_on, 1); + mdelay(10); + /* power reset pin enable */ + gpio_set_value(gpio_reset, 1); + mdelay(10); +#endif + printk(BIOS_INFO, "Anx7625 power on !\n"); +} + +static void anx7625_power_standby(void) +{ +#ifdef ANXGPIO + gpio_set_value(gpio_reset, 0); + mdelay(1); + gpio_set_value(gpio_p_on, 0); + mdelay(1); +#endif + printk(BIOS_INFO, "anx7625 power down\n"); +} + +static void anx7625_disable_pd_protocol(uint8_t bus) +{ + int ret; + + /* reset main ocm */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, 0x88, 0x40); + /* Disable PD */ + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AV_STATUS, AP_DISABLE_PD); + /* release main ocm */ + ret |= anx7625_reg_write(bus, RX_P0_ADDR, 0x88, 0x00); + + if (ret < 0) + printk(BIOS_INFO, "disable PD feature failed.\n"); + else + printk(BIOS_INFO, "disable PD feature succeeded.\n"); +} + +#define FLASH_LOAD_STA 0x05 +#define FLASH_LOAD_STA_CHK (1<<7) +static void anx7625_power_on_init(uint8_t bus) +{ + int retry_count, i; + int ret = 0; + uint8_t val; + + for (retry_count = 0; retry_count < 3; retry_count++) { + anx7625_power_on(); + + anx7625_reg_write(bus, RX_P0_ADDR, XTAL_FRQ_SEL, XTAL_FRQ_27M); + + for (i = 0; i < OCM_LOADING_TIME; i++) { + /* check interface workable */ + ret = anx7625_reg_read(bus, RX_P0_ADDR, + FLASH_LOAD_STA, &val); + if (ret < 0) { + printk(BIOS_INFO, "IO error : access flash load.\n"); + return; + } + if ((val & FLASH_LOAD_STA_CHK) == FLASH_LOAD_STA_CHK) { + printk(BIOS_INFO, "interface initialization\n"); + anx7625_disable_pd_protocol(bus); + + anx7625_reg_read(bus, RX_P0_ADDR, + OCM_FW_VERSION, &val); + + printk(BIOS_INFO, "Firmware ver %02x:", val); + anx7625_reg_read(bus, RX_P0_ADDR, + OCM_FW_REVERSION, &val); + printk(BIOS_INFO, "%02x\n", val); + return; + } + mdelay(1); + } + anx7625_power_standby(); + } +} + +static void anx7625_start_dp_work(uint8_t bus) +{ + int ret; + uint8_t val; + + /* not support HDCP */ + ret = anx7625_write_and(bus, RX_P1_ADDR, 0xee, 0x9f); + + /* try auth flag */ + ret |= anx7625_write_or(bus, RX_P1_ADDR, 0xec, 0x10); + /* interrupt for DRM */ + ret |= anx7625_write_or(bus, RX_P1_ADDR, 0xff, 0x01); + if (ret < 0) + return; + + ret = anx7625_reg_read(bus, RX_P1_ADDR, 0x86, &val); + if (ret < 0) + return; + + printk(BIOS_INFO, "Secure OCM version=%02x\n", val); +} + +static int anx7625_hpd_change_detect(uint8_t bus) +{ + int ret; + uint8_t status; + + ret = anx7625_reg_read(bus, RX_P0_ADDR, + SYSTEM_STSTUS, &status); + if (ret < 0) { + printk(BIOS_INFO, "IO error : clear interrupt status.\n"); + return ret; + } + + if (status & HPD_STATUS) { + anx7625_start_dp_work(bus); + printk(BIOS_INFO, "hpd received 0x7e:0x45=%x\n", status); + return 1; + } + return 0; +} + +static void anx7625_parse_edid(struct edid *edid, struct display_timing *dt) +{ + dt->pixelclock = edid->mode.pixel_clock; + + dt->hactive = edid->mode.ha; + dt->hsync_len = edid->mode.hspw; + dt->hback_porch = edid->mode.hbl - edid->mode.hso - + edid->mode.hborder - edid->mode.hspw; + dt->hfront_porch = edid->mode.hso - edid->mode.hborder; + + dt->vactive = edid->mode.va; + dt->vsync_len = edid->mode.vspw; + dt->vfront_porch = edid->mode.vso - edid->mode.vborder; + dt->vback_porch = edid->mode.vbl - edid->mode.vso - + edid->mode.vspw - edid->mode.vborder; + + printk(BIOS_INFO, "pixelclock(%d).\n", dt->pixelclock); + printk(BIOS_INFO, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", + dt->hactive, + dt->hsync_len, + dt->hfront_porch, + dt->hback_porch); + printk(BIOS_INFO, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", + dt->vactive, + dt->vsync_len, + dt->vfront_porch, + dt->vback_porch); +} + +int anx7625_dp_start(uint8_t bus, struct edid *edid) +{ + int ret; + struct display_timing dt; + + anx7625_parse_edid(edid, &dt); + + ret = anx7625_dsi_config(bus, &dt); + if (ret < 0) + printk(BIOS_INFO, "MIPI phy setup error.\n"); + else + printk(BIOS_INFO, "MIPI phy setup OK.\n"); + + return ret; +} + +int anx7625_dp_get_edid(uint8_t bus, struct edid *out) +{ + int block_num; + int ret; + u8 edid[ONE_BLOCK_SIZE * 4]; + + block_num = sp_tx_edid_read(bus, edid); + if (block_num < 0) { + printk(BIOS_INFO, "Failed to get eDP EDID.\n"); + return -1; + } + + ret = decode_edid(edid, (block_num + 1) * ONE_BLOCK_SIZE, out); + if (ret != EDID_CONFORMANT) { + printk(BIOS_INFO, "Failed to decode EDID.\n"); + return -1; + } + + return 0; +} + +int anx7625_init(uint8_t bus) +{ + int cnt; + + anx7625_power_on_init(bus); + + for (cnt = 0; cnt < 50; cnt++) { + mdelay(10); + if (anx7625_hpd_change_detect(bus)) + return 0; + } + + return -1; +} + diff --git a/src/drivers/analogix/anx7625/anx7625.h b/src/drivers/analogix/anx7625/anx7625.h new file mode 100644 index 0000000..d2391a6 --- /dev/null +++ b/src/drivers/analogix/anx7625/anx7625.h @@ -0,0 +1,363 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright(c) 2016, Analogix Semiconductor. All rights reserved. + * + */ + + +#include <edid.h> +#include <types.h> + +#ifndef __ANX7625_H__ +#define __ANX7625_H__ + +#ifndef LOG_TAG +#define LOG_TAG "anx7625dp" +#endif + +#define ANX7625_DRV_VERSION "0.1.04" + +/* Loading OCM re-trying times */ +#define OCM_LOADING_TIME 10 + +/********* ANX7625 Register **********/ +#define ANXI2CSIM +#ifdef ANXI2CSIM +#define TX_P0_ADDR 0x38 +#define TX_P1_ADDR 0x3D +#define TX_P2_ADDR 0x39 +#define RX_P0_ADDR 0x3F +#define RX_P1_ADDR 0x42 +#define RX_P2_ADDR 0x2A +#define TCPC_INTERFACE_ADDR 0x2C +#else +#define TX_P0_ADDR 0x70 +#define TX_P1_ADDR 0x7A +#define TX_P2_ADDR 0x72 +#define RX_P0_ADDR 0x7e +#define RX_P1_ADDR 0x84 +#define RX_P2_ADDR 0x54 +#define TCPC_INTERFACE_ADDR 0x58 +#endif + +#define RSVD_00_ADDR 0x00 +#define RSVD_D1_ADDR 0xD1 +#define RSVD_60_ADDR 0x60 +#define RSVD_39_ADDR 0x39 +#define RSVD_7F_ADDR 0x7F + +/* anx7625 clock frequency in Hz */ +#define XTAL_FRQ (27*1000000) + +#define POST_DIVIDER_MIN 1 +#define POST_DIVIDER_MAX 16 +#define PLL_OUT_FREQ_MIN 520000000UL +#define PLL_OUT_FREQ_MAX 730000000UL +#define PLL_OUT_FREQ_ABS_MIN 300000000UL +#define PLL_OUT_FREQ_ABS_MAX 800000000UL +#define MAX_UNSIGNED_24BIT 16777215UL + +/***************************************************************/ +/* Register definition of device address 0x58 */ + +#define PRODUCT_ID_L 0x02 +#define PRODUCT_ID_H 0x03 + +#define INTR_ALERT_1 0xCC +#define INTR_SOFTWARE_INT (1<<3) +#define INTR_RECEIVED_MSG (1<<5) + +#define SYSTEM_STSTUS 0x45 +#define INTERFACE_CHANGE_INT 0x44 +#define HPD_STATUS_CHANGE 0x80 +#define HPD_STATUS 0x80 + +/******** END of I2C Address 0x58 ********/ + +/***************************************************************/ +/* Register definition of device address 0x70 */ +#define I2C_ADDR_70_DPTX 0x70 + +#define SP_TX_LINK_BW_SET_REG 0xA0 +#define SP_TX_LANE_COUNT_SET_REG 0xA1 + +#define M_VID_0 0xC0 +#define M_VID_1 0xC1 +#define M_VID_2 0xC2 +#define N_VID_0 0xC3 +#define N_VID_1 0xC4 +#define N_VID_2 0xC5 + +/***************************************************************/ +/* Register definition of device address 0x72 */ +#define AUX_RST 0x04 +#define RST_CTRL2 0x07 + +#define SP_TX_TOTAL_LINE_STA_L 0x24 +#define SP_TX_TOTAL_LINE_STA_H 0x25 +#define SP_TX_ACT_LINE_STA_L 0x26 +#define SP_TX_ACT_LINE_STA_H 0x27 +#define SP_TX_V_F_PORCH_STA 0x28 +#define SP_TX_V_SYNC_STA 0x29 +#define SP_TX_V_B_PORCH_STA 0x2A +#define SP_TX_TOTAL_PIXEL_STA_L 0x2B +#define SP_TX_TOTAL_PIXEL_STA_H 0x2C +#define SP_TX_ACT_PIXEL_STA_L 0x2D +#define SP_TX_ACT_PIXEL_STA_H 0x2E +#define SP_TX_H_F_PORCH_STA_L 0x2F +#define SP_TX_H_F_PORCH_STA_H 0x30 +#define SP_TX_H_SYNC_STA_L 0x31 +#define SP_TX_H_SYNC_STA_H 0x32 +#define SP_TX_H_B_PORCH_STA_L 0x33 +#define SP_TX_H_B_PORCH_STA_H 0x34 + +#define SP_TX_VID_CTRL 0x84 +#define SP_TX_BPC_MASK 0xE0 +#define SP_TX_BPC_6 0x00 +#define SP_TX_BPC_8 0x20 +#define SP_TX_BPC_10 0x40 +#define SP_TX_BPC_12 0x60 + +#define VIDEO_BIT_MATRIX_12 0x4c + +#define AUDIO_CHANNEL_STATUS_1 0xd0 +#define AUDIO_CHANNEL_STATUS_2 0xd1 +#define AUDIO_CHANNEL_STATUS_3 0xd2 +#define AUDIO_CHANNEL_STATUS_4 0xd3 +#define AUDIO_CHANNEL_STATUS_5 0xd4 +#define AUDIO_CHANNEL_STATUS_6 0xd5 +#define TDM_SLAVE_MODE 0x10 +#define I2S_SLAVE_MODE 0x08 + +#define AUDIO_CONTROL_REGISTER 0xe6 +#define TDM_TIMING_MODE 0x08 + +#define I2C_ADDR_72_DPTX 0x72 + +#define VIDEO_CONTROL_0 0x08 + +#define ACTIVE_LINES_L 0x14 +#define ACTIVE_LINES_H 0x15 /* note: bit[7:6] are reserved */ +#define VERTICAL_FRONT_PORCH 0x16 +#define VERTICAL_SYNC_WIDTH 0x17 +#define VERTICAL_BACK_PORCH 0x18 + +#define HORIZONTAL_TOTAL_PIXELS_L 0x19 +#define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* note: bit[7:6] are reserved */ +#define HORIZONTAL_ACTIVE_PIXELS_L 0x1B +#define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* note: bit[7:6] are reserved */ +#define HORIZONTAL_FRONT_PORCH_L 0x1D +#define HORIZONTAL_FRONT_PORCH_H 0x1E /* note: bit[7:4] are reserved */ +#define HORIZONTAL_SYNC_WIDTH_L 0x1F +#define HORIZONTAL_SYNC_WIDTH_H 0x20 /* note: bit[7:4] are reserved */ +#define HORIZONTAL_BACK_PORCH_L 0x21 +#define HORIZONTAL_BACK_PORCH_H 0x22 /* note: bit[7:4] are reserved */ + +/******** END of I2C Address 0x72 *********/ +/***************************************************************/ +/* Register definition of device address 0x7e */ + +#define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E + +#define XTAL_FRQ_SEL 0x3F +/* bit field positions */ +#define XTAL_FRQ_SEL_POS 5 +/* bit field values */ +#define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS) +#define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS) + +#define R_DSC_CTRL_0 0x40 +#define READ_STATUS_EN 7 +#define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */ +#define DSC_BIST_DONE 1 /* bit[5:1]: 1=DSC MBIST pass */ +#define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */ + +#define OCM_FW_VERSION 0x31 +#define OCM_FW_REVERSION 0x32 + +#define AP_AUX_ADDR_7_0 0x11 +#define AP_AUX_ADDR_15_8 0x12 +#define AP_AUX_ADDR_19_16 0x13 + +/* note: bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ +#define AP_AUX_CTRL_STATUS 0x14 +#define AP_AUX_CTRL_OP_EN 0x10 +#define AP_AUX_CTRL_ADDRONLY 0x20 + +#define AP_AUX_BUFF_START 0x15 +#define PIXEL_CLOCK_L 0x25 +#define PIXEL_CLOCK_H 0x26 + +#define AP_AUX_COMMAND 0x27 /* com+len */ +/* bit 0&1: 3D video structure */ +/* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ +#define AP_AV_STATUS 0x28 +#define AP_VIDEO_CHG (1<<2) +#define AP_AUDIO_CHG (1<<3) +#define AP_MIPI_MUTE (1<<4) /* 1:MIPI input mute, 0: ummute */ +#define AP_MIPI_RX_EN (1<<5) /* 1: MIPI RX input in 0: no RX in */ +#define AP_DISABLE_PD (1<<6) +#define AP_DISABLE_DISPLAY (1<<7) +/***************************************************************/ +/* Register definition of device address 0x84 */ +#define MIPI_PHY_CONTROL_3 0x03 +#define MIPI_HS_PWD_CLK 7 +#define MIPI_HS_RT_CLK 6 +#define MIPI_PD_CLK 5 +#define MIPI_CLK_RT_MANUAL_PD_EN 4 +#define MIPI_CLK_HS_MANUAL_PD_EN 3 +#define MIPI_CLK_DET_DET_BYPASS 2 +#define MIPI_CLK_MISS_CTRL 1 +#define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0 + +#define MIPI_LANE_CTRL_0 0x05 +#define MIPI_TIME_HS_PRPR 0x08 + +/* After MIPI RX protocol layer received this many video frames, */ +/* protocol layer starts to reconstruct video stream from PHY */ +#define MIPI_VIDEO_STABLE_CNT 0x0A + +#define MIPI_LANE_CTRL_10 0x0F +#define MIPI_DIGITAL_ADJ_1 0x1B + +#define MIPI_PLL_M_NUM_23_16 0x1E +#define MIPI_PLL_M_NUM_15_8 0x1F +#define MIPI_PLL_M_NUM_7_0 0x20 +#define MIPI_PLL_N_NUM_23_16 0x21 +#define MIPI_PLL_N_NUM_15_8 0x22 +#define MIPI_PLL_N_NUM_7_0 0x23 + +#define MIPI_DIGITAL_PLL_6 0x2A +/* bit[7:6]: VCO band control, only effective */ +/* when MIPI_PLL_FORCE_BAND_EN (0x84:0x2B[6]) is 1 */ +#define MIPI_M_NUM_READY 0x10 +#define MIPI_N_NUM_READY 0x08 +#define STABLE_INTEGER_CNT_EN 0x04 +#define MIPI_PLL_TEST_BIT 0 +/* bit[1:0]: test point output select - */ +/* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ + +#define MIPI_DIGITAL_PLL_7 0x2B +#define MIPI_PLL_FORCE_N_EN 7 +#define MIPI_PLL_FORCE_BAND_EN 6 + +#define MIPI_PLL_VCO_TUNE_REG 4 +/* bit[5:4]: VCO metal capacitance - */ +/* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ +#define MIPI_PLL_VCO_TUNE_REG_VAL 0x30 + +#define MIPI_PLL_PLL_LDO_BIT 2 +/* bit[3:2]: vco_v2i power - */ +/* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ +#define MIPI_PLL_RESET_N 0x02 +#define MIPI_FRQ_FORCE_NDET 0 + +#define MIPI_ALERT_CLR_0 0x2D +#define HS_link_error_clear 7 +/* This bit itself is S/C, and it clears 0x84:0x31[7] */ + +#define MIPI_ALERT_OUT_0 0x31 +#define check_sum_err_hs_sync 7 +/* This bit is cleared by 0x84:0x2D[7] */ + +#define MIPI_DIGITAL_PLL_8 0x33 +#define MIPI_POST_DIV_VAL 4 +/* n means divided by (n+1), n = 0~15 */ +#define MIPI_EN_LOCK_FRZ 3 +#define MIPI_FRQ_COUNTER_RST 2 +#define MIPI_FRQ_SET_REG_8 1 +/* bit 0 is reserved */ + +#define MIPI_DIGITAL_PLL_9 0x34 + +#define MIPI_DIGITAL_PLL_16 0x3B +#define MIPI_FRQ_FREEZE_NDET 7 +#define MIPI_FRQ_REG_SET_ENABLE 6 +#define MIPI_REG_FORCE_SEL_EN 5 +#define MIPI_REG_SEL_DIV_REG 4 +#define MIPI_REG_FORCE_PRE_DIV_EN 3 +/* bit 2 is reserved */ +#define MIPI_FREF_D_IND 1 +#define REF_CLK_27000kHz 1 +#define REF_CLK_19200kHz 0 +#define MIPI_REG_PLL_PLL_TEST_ENABLE 0 + +#define MIPI_DIGITAL_PLL_18 0x3D +#define FRQ_COUNT_RB_SEL 7 +#define REG_FORCE_POST_DIV_EN 6 +#define MIPI_DPI_SELECT 5 +#define SELECT_DSI 1 +#define SELECT_DPI 0 +#define REG_BAUD_DIV_RATIO 0 + +#define H_BLANK_L 0x3E +/* for DSC only */ +#define H_BLANK_H 0x3F +/* for DSC only; note: bit[7:6] are reserved */ +#define MIPI_SWAP 0x4A +#define MIPI_SWAP_CH0 7 +#define MIPI_SWAP_CH1 6 +#define MIPI_SWAP_CH2 5 +#define MIPI_SWAP_CH3 4 +#define MIPI_SWAP_CLK 3 +/* bit[2:0] are reserved */ + +/******** END of I2C Address 0x84 *********/ + +/* DPCD regs */ +#define DPCD_DPCD_REV 0x00 +#define DPCD_MAX_LINK_RATE 0x01 +#define DPCD_MAX_LANE_COUNT 0x02 + +/********* ANX7625 Register End **********/ + +/***************** Display *****************/ +enum AudioFs { + AUDIO_FS_441K = 0x00, + AUDIO_FS_48K = 0x02, + AUDIO_FS_32K = 0x03, + AUDIO_FS_882K = 0x08, + AUDIO_FS_96K = 0x0a, + AUDIO_FS_1764K = 0x0c, + AUDIO_FS_192K = 0x0e +}; + +enum AudioWdLen { + AUDIO_W_LEN_16_20MAX = 0x02, + AUDIO_W_LEN_18_20MAX = 0x04, + AUDIO_W_LEN_17_20MAX = 0x0c, + AUDIO_W_LEN_19_20MAX = 0x08, + AUDIO_W_LEN_20_20MAX = 0x0a, + AUDIO_W_LEN_20_24MAX = 0x03, + AUDIO_W_LEN_22_24MAX = 0x05, + AUDIO_W_LEN_21_24MAX = 0x0d, + AUDIO_W_LEN_23_24MAX = 0x09, + AUDIO_W_LEN_24_24MAX = 0x0b +}; + +#define I2S_CH_2 0x01 +#define TDM_CH_4 0x03 +#define TDM_CH_6 0x05 +#define TDM_CH_8 0x07 + +#define MAX_DPCD_BUFFER_SIZE 16 + +#define ONE_BLOCK_SIZE 128 +#define FOUR_BLOCK_SIZE (128*4) + +struct display_timing { + unsigned int pixelclock; + unsigned int hactive; + unsigned int hfront_porch; + unsigned int hback_porch; + unsigned int hsync_len; + unsigned int vactive; + unsigned int vfront_porch; + unsigned int vback_porch; + unsigned int vsync_len; +}; + +int anx7625_dp_start(uint8_t bus, struct edid *edid); +int anx7625_dp_get_edid(uint8_t bus, struct edid *out); +int anx7625_init(uint8_t bus); +#endif /* __ANX7625_H__ */ diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 2828918..bab96ad 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -42,7 +42,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER - select DRIVER_PARADE_PS8640 if BOARD_GOOGLE_JACUZZI + select DRIVER_ANALOGIX_ANX7625 if BOARD_GOOGLE_JACUZZI select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE config MAINBOARD_DIR diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 2e8a79a..7839422 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -30,4 +30,6 @@ ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c ramstage-$(CONFIG_DRIVER_PARADE_PS8640) += panel_ps8640.c +ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += panel_anx7625.c + ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c new file mode 100644 index 0000000..10cbf5c --- /dev/null +++ b/src/mainboard/google/kukui/panel_anx7625.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <drivers/analogix/anx7625/anx7625.h> +#include <edid.h> +#include <gpio.h> +#include <soc/i2c.h> +#include <string.h> + +#include "panel.h" + + +static void power_on_anx7625(void) +{ + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); + gpio_output(GPIO_PP1200_MIPIBRDG_EN, 1); //1.0 + gpio_output(GPIO_VDDIO_MIPIBRDG_EN, 1); //3.3 + gpio_output(GPIO_PP1800_LCM_EN, 1); //1.8 + mdelay(2); + gpio_output(GPIO_MIPIBRDG_PWRDN_L_1V8, 1); + mdelay(10); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 1); + gpio_output(GPIO_PP3300_LCM_EN, 1); +} + +static void dummy_power_on(void) +{ + /* The panel has been already powered on when getting panel information + * so we should do nothing here. + */ +} + +static struct panel_serializable_data anx7625_data = { + .orientation = LB_FB_ORIENTATION_NORMAL, + .init = { INIT_END_CMD }, +}; + +static struct panel_description anx7625_panel = { + .s = &anx7625_data, + .power_on = dummy_power_on, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + /* To read panel EDID, we have to first power on anx7625. */ + power_on_anx7625(); + + u8 i2c_bus = 4; + mtk_i2c_bus_init(i2c_bus); + + anx7625_init(i2c_bus); + struct edid *edid = &anx7625_data.edid; + if (anx7625_dp_get_edid(i2c_bus, edid)) { + printk(BIOS_ERR, "Can't get panel's edid\n"); + return NULL; + } + anx7625_dp_start(i2c_bus, edid); + return &anx7625_panel; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02ef29798b0257632e0750f09a4390b3d0226367 Gerrit-Change-Number: 35623 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019