coreboot-gerrit November 2019

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Change in ...coreboot[master]: cpu/x86/pae/pgtbl: Use CRx_TYPE type for CRx
by HAOUAS Elyes (Code Review) 13 Dec '19

13 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33964 Change subject: cpu/x86/pae/pgtbl: Use CRx_TYPE type for CRx ...................................................................... cpu/x86/pae/pgtbl: Use CRx_TYPE type for CRx Change-Id: I8108398071a6ff7bceb90741581522023a786afd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/pae/pgtbl.c M src/include/cpu/x86/pae.h 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/33964/1 diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index f54a1c3..5d23ce5 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -76,7 +76,7 @@ struct pde pdp[512]; } __packed; -void paging_enable_pae_cr3(uintptr_t cr3) +void paging_enable_pae_cr3(CRx_TYPE cr3) { /* Load the page table address */ write_cr3(cr3); @@ -198,7 +198,7 @@ /* Get pointer to PD that's not identity mapped */ pd = &pgtbl_buf->pd[((uintptr_t)vmem_addr) >> PDE_IDX_SHIFT]; - paging_enable_pae_cr3((uintptr_t)pdp); + paging_enable_pae_cr3((CRx_TYPE)pdp); do { const size_t len = MIN(length, s2MiB - offset); @@ -279,7 +279,7 @@ | ((i & 0x3ff) << 21) | 0xE3; pd[i].addr_hi = (window >> 1); } - paging_enable_pae_cr3((uintptr_t)pdp); + paging_enable_pae_cr3((CRx_TYPE)pdp); } mapped_window[index] = window; } @@ -376,7 +376,7 @@ return -1; } - paging_enable_pae_cr3((uintptr_t)_pdpt); + paging_enable_pae_cr3((CRx_TYPE)_pdpt); return 0; } diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index 72bae53..6464503 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -22,7 +22,7 @@ /* Enable paging with cr3 value for page directory pointer table as well as PAE option in cr4. */ -void paging_enable_pae_cr3(uintptr_t cr3); +void paging_enable_pae_cr3(CRx_TYPE cr3); /* Enable paging as well as PAE option in cr4. */ void paging_enable_pae(void); /* Disable paging as well as PAE option in cr4. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8108398071a6ff7bceb90741581522023a786afd Gerrit-Change-Number: 33964 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/sandybridge/raminit_common.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 13 Dec '19

13 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33005 Change subject: nb/sandybridge/raminit_common.c: Remove variable set but not used ...................................................................... nb/sandybridge/raminit_common.c: Remove variable set but not used Change-Id: I109353775fe4ecce6a05ef88781939243f398d17 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/33005/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5347c5c..b8ad3c0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1824,7 +1824,7 @@ static void adjust_high_timB(ramctr_timing * ctrl) { - int channel, slotrank, lane, old; + int channel, slotrank, lane; MCHBAR32(0x3400) = 0x200; FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); @@ -1898,15 +1898,18 @@ 0x100 * channel + 4); res |= ((u64) MCHBAR32(lane_registers[lane] + 0x100 * channel + 8)) << 32; - old = ctrl->timings[channel][slotrank].lanes[lane].timB; - ctrl->timings[channel][slotrank].lanes[lane].timB += - get_timB_high_adjust(res) * 64; printram("High adjust %d:%016llx\n", lane, res); - printram("Bval+: %d, %d, %d, %x -> %x\n", channel, - slotrank, lane, old, + printram("Bval+: %d, %d, %d, %x", channel, + slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane]. timB); + ctrl->timings[channel][slotrank].lanes[lane].timB += + get_timB_high_adjust(res) * 64; + printram(" -> %x\n", + ctrl->timings[channel][slotrank].lanes[lane]. + timB); + } } MCHBAR32(0x3400) = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/33005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I109353775fe4ecce6a05ef88781939243f398d17 Gerrit-Change-Number: 33005 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: SMBIOS (Type 17): Update the string for Intel persistent memory
by HAOUAS Elyes (Code Review) 13 Dec '19

13 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35895 ) Change subject: SMBIOS (Type 17): Update the string for Intel persistent memory ...................................................................... SMBIOS (Type 17): Update the string for Intel persistent memory Change-Id: I0cd49ffd05bba4ea29550659ac56ea991b697592 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/smbios.h 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/35895/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index eb947dc..94b4208 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -97,13 +97,13 @@ #define MEMORY_TYPE_DETAIL_UNBUFFERED (1 << 14) #define MEMORY_TYPE_DETAIL_LRDIMM (1 << 15) -#define MEMORY_TECHNOLOGY_OTHER 0x01 -#define MEMORY_TECHNOLOGY_UNKNOWN 0x02 -#define MEMORY_TECHNOLOGY_DRAM 0x03 -#define MEMORY_TECHNOLOGY_NVDIMM_N 0x04 -#define MEMORY_TECHNOLOGY_NVDIMM_F 0x05 -#define MEMORY_TECHNOLOGY_NVDIMM_P 0x06 -#define MEMORY_TECHNOLOGY_INTEL_PERSISTENT 0x07 +#define MEMORY_TECHNOLOGY_OTHER 0x01 +#define MEMORY_TECHNOLOGY_UNKNOWN 0x02 +#define MEMORY_TECHNOLOGY_DRAM 0x03 +#define MEMORY_TECHNOLOGY_NVDIMM_N 0x04 +#define MEMORY_TECHNOLOGY_NVDIMM_F 0x05 +#define MEMORY_TECHNOLOGY_NVDIMM_P 0x06 +#define MEMORY_TECHNOLOGY_INTEL_OPTANE_PERSISTENT 0x07 #define MEMORY_OPERATING_MODE_CAP_OTHER (1 << 1) #define MEMORY_OPERATING_MODE_CAP_UNKNOWN (1 << 2) -- To view, visit https://review.coreboot.org/c/coreboot/+/35895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd49ffd05bba4ea29550659ac56ea991b697592 Gerrit-Change-Number: 35895 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: mb/pcengines/apu1: initialize serial port in bootblock
by Michał Żygowski (Code Review) 13 Dec '19

13 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37332 ) Change subject: mb/pcengines/apu1: initialize serial port in bootblock ...................................................................... mb/pcengines/apu1: initialize serial port in bootblock TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d --- A src/mainboard/pcengines/apu1/bootblock.c M src/mainboard/pcengines/apu1/romstage.c 2 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37332/1 diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c new file mode 100644 index 0000000..5a3d97c --- /dev/null +++ b/src/mainboard/pcengines/apu1/bootblock.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> + +#define SIO_PORT 0x2e +#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) + + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index 89bf304..134382f 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -61,5 +61,4 @@ void board_BeforeAgesa(struct sysinfo *cb) { early_lpc_init(); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d Gerrit-Change-Number: 37332 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: [test] -Wconversion option
by HAOUAS Elyes (Code Review) 12 Dec '19

12 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37340 ) Change subject: [test] -Wconversion option ...................................................................... [test] -Wconversion option Change-Id: Id1b60359d940f76550e93ecf984c8566f2ddfac4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/37340/1 diff --git a/Makefile.inc b/Makefile.inc index dc5272e..f2a94a3 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -410,7 +410,7 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla +CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla -Wconversion CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/37340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1b60359d940f76550e93ecf984c8566f2ddfac4 Gerrit-Change-Number: 37340 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: [WIP] AGESA, binaryPI: Remove generic device for SPD eeproms
by Kyösti Mälkki (Code Review) 12 Dec '19

12 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35102 ) Change subject: [WIP] AGESA, binaryPI: Remove generic device for SPD eeproms ...................................................................... [WIP] AGESA, binaryPI: Remove generic device for SPD eeproms Change-Id: Ieab695022d0dd2f2671f9058db97bdd6fb29a10d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/bettong/devicetree.cb M src/mainboard/amd/gardenia/devicetree.cb M src/mainboard/amd/inagua/devicetree.cb M src/mainboard/amd/lamar/devicetree.cb M src/mainboard/amd/olivehill/devicetree.cb M src/mainboard/amd/olivehillplus/devicetree.cb M src/mainboard/amd/parmer/devicetree.cb M src/mainboard/amd/persimmon/devicetree.cb M src/mainboard/amd/thatcher/devicetree.cb M src/mainboard/amd/torpedo/devicetree.cb M src/mainboard/asrock/e350m1/devicetree.cb M src/mainboard/asrock/imb-a180/devicetree.cb M src/mainboard/asus/am1i-a/devicetree.cb M src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb M src/mainboard/biostar/am1ml/devicetree.cb M src/mainboard/elmex/pcm205400/devicetree.cb M src/mainboard/hp/abm/devicetree.cb M src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb M src/mainboard/jetway/nf81-t56n-lf/devicetree.cb M src/mainboard/lenovo/g505s/devicetree.cb M src/mainboard/lippert/frontrunner-af/devicetree.cb M src/mainboard/lippert/toucan-af/devicetree.cb M src/mainboard/msi/ms7721/devicetree.cb 25 files changed, 0 insertions(+), 156 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35102/1 diff --git a/src/mainboard/amd/bettong/devicetree.cb b/src/mainboard/amd/bettong/devicetree.cb index 84aaf41..e318b6d 100644 --- a/src/mainboard/amd/bettong/devicetree.cb +++ b/src/mainboard/amd/bettong/devicetree.cb @@ -43,12 +43,6 @@ device pci 11.0 on end # SATA device pci 12.0 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM #device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d diff --git a/src/mainboard/amd/gardenia/devicetree.cb b/src/mainboard/amd/gardenia/devicetree.cb index e9946ad..beee845 100644 --- a/src/mainboard/amd/gardenia/devicetree.cb +++ b/src/mainboard/amd/gardenia/devicetree.cb @@ -41,9 +41,6 @@ device pci 11.0 on end # SATA device pci 12.0 on end # EHCI device pci 14.0 on # SM - chip drivers/generic/generic # dimm 0-0-0 - device i2c 51 on end - end end # SM device pci 14.3 on end # LPC 0x790e device pci 14.7 on end # SD diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index 578c654..cc28124 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -38,12 +38,6 @@ device pci 13.0 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/amd/lamar/devicetree.cb b/src/mainboard/amd/lamar/devicetree.cb index d7f3f05..e57a6c6 100644 --- a/src/mainboard/amd/lamar/devicetree.cb +++ b/src/mainboard/amd/lamar/devicetree.cb @@ -54,18 +54,6 @@ device pci 13.0 on end # 0x7807 USB OHCI device pci 13.2 on end # 0x7808 USB EHCI device pci 14.0 on # 0x780B SMBus - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # 0x780C IDE device pci 14.2 on end # 0x780D HDA diff --git a/src/mainboard/amd/olivehill/devicetree.cb b/src/mainboard/amd/olivehill/devicetree.cb index bf8d476..a7933ce 100644 --- a/src/mainboard/amd/olivehill/devicetree.cb +++ b/src/mainboard/amd/olivehill/devicetree.cb @@ -41,12 +41,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb index 430b17b..4b47642d 100644 --- a/src/mainboard/amd/olivehillplus/devicetree.cb +++ b/src/mainboard/amd/olivehillplus/devicetree.cb @@ -42,12 +42,6 @@ device pci 12.0 on end # EHCI #0 device pci 13.0 on end # EHCI #1 device pci 14.0 on # SMBus - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SMbus device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index e619def..7e0fc2c 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -44,12 +44,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index 323e7f2..40ea282 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -37,12 +37,6 @@ device pci 13.0 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index 4ae1ba9..a55fa25 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -44,12 +44,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/amd/torpedo/devicetree.cb b/src/mainboard/amd/torpedo/devicetree.cb index 2adfb27..00923ea 100644 --- a/src/mainboard/amd/torpedo/devicetree.cb +++ b/src/mainboard/amd/torpedo/devicetree.cb @@ -42,12 +42,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.1 on end # IDE device pci 14.2 on end # HDA diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index e374c41..5d368fa 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -39,12 +39,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/asrock/imb-a180/devicetree.cb b/src/mainboard/asrock/imb-a180/devicetree.cb index 2c4a4aa..3ade19b 100644 --- a/src/mainboard/asrock/imb-a180/devicetree.cb +++ b/src/mainboard/asrock/imb-a180/devicetree.cb @@ -42,12 +42,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.2 on end # HDA 0x4383 device pci 14.3 on diff --git a/src/mainboard/asus/am1i-a/devicetree.cb b/src/mainboard/asus/am1i-a/devicetree.cb index 53114c1..763761a 100644 --- a/src/mainboard/asus/am1i-a/devicetree.cb +++ b/src/mainboard/asus/am1i-a/devicetree.cb @@ -43,12 +43,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb index 349a845..c95fe84 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb @@ -47,12 +47,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end end # SM device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb index af0e4cc..3e39ef3 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb @@ -47,12 +47,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end end # SM device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 238ab51..e261505 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -38,18 +38,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 52 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 2 - device i2c 51 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 3 - device i2c 53 on end # 7-bit SPD address - end end # SM device pci 14.1 off end # unused device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/biostar/am1ml/devicetree.cb b/src/mainboard/biostar/am1ml/devicetree.cb index 400653d..e6adc0a 100644 --- a/src/mainboard/biostar/am1ml/devicetree.cb +++ b/src/mainboard/biostar/am1ml/devicetree.cb @@ -42,12 +42,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.1 on end # there is no legacy ide device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/elmex/pcm205400/devicetree.cb b/src/mainboard/elmex/pcm205400/devicetree.cb index 405f3e0..d11529b 100644 --- a/src/mainboard/elmex/pcm205400/devicetree.cb +++ b/src/mainboard/elmex/pcm205400/devicetree.cb @@ -37,12 +37,6 @@ device pci 13.0 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 off end # HDA 0x4383 diff --git a/src/mainboard/hp/abm/devicetree.cb b/src/mainboard/hp/abm/devicetree.cb index c7a7510..2786f78 100644 --- a/src/mainboard/hp/abm/devicetree.cb +++ b/src/mainboard/hp/abm/devicetree.cb @@ -41,9 +41,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end end # SM device pci 14.2 off end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb index ad59974..35ccca7 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb +++ b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb @@ -41,12 +41,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end end # SM device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 6289438..faed1c5 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -38,12 +38,6 @@ device pci 13.0 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 99f42d6..5be9111 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -45,12 +45,6 @@ device pci 13.0 on end # FCH USB OHCI Controller device pci 13.2 on end # FCH USB EHCI Controller device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end end # SM device pci 14.2 on end # FCH Azalia Controller device pci 14.3 on # FCH LPC Bridge [1022:780e] diff --git a/src/mainboard/lippert/frontrunner-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/devicetree.cb index b72059a..5e84fcb 100644 --- a/src/mainboard/lippert/frontrunner-af/devicetree.cb +++ b/src/mainboard/lippert/frontrunner-af/devicetree.cb @@ -37,12 +37,6 @@ device pci 13.0 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 off end - end end # SM device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/lippert/toucan-af/devicetree.cb b/src/mainboard/lippert/toucan-af/devicetree.cb index cb9aa8e..25d84db 100644 --- a/src/mainboard/lippert/toucan-af/devicetree.cb +++ b/src/mainboard/lippert/toucan-af/devicetree.cb @@ -38,12 +38,6 @@ device pci 13.0 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 off end - end end # SM device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/msi/ms7721/devicetree.cb b/src/mainboard/msi/ms7721/devicetree.cb index d3991f1..1c73404 100644 --- a/src/mainboard/msi/ms7721/devicetree.cb +++ b/src/mainboard/msi/ms7721/devicetree.cb @@ -46,12 +46,6 @@ device pci 13.0 on end # USB OHCI device pci 13.2 on end # USB EHCI device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end end # SM device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # Azalia (Audio) -- To view, visit https://review.coreboot.org/c/coreboot/+/35102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieab695022d0dd2f2671f9058db97bdd6fb29a10d Gerrit-Change-Number: 35102 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/mediatek/mt8183: TX RX window donot fast K for High frequency
by huayang duan (Code Review) 12 Dec '19

12 Dec '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36921 ) Change subject: soc/mediatek/mt8183: TX RX window donot fast K for High frequency ...................................................................... soc/mediatek/mt8183: TX RX window donot fast K for High frequency TX RX window can do fast calibraton at lower frquency, like 1600Mbps, 2400Mbps, but High frequency can't do fast calibraton. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I00d563ece4cf91ef5e8e12b6cf7f777849375a24 --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/36921/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c old mode 100644 new mode 100755 index 16f2878..414133a --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -1788,7 +1788,7 @@ u8 fsp = get_freq_fsq(freq_group); u8 vref_range = !fsp; - bool bypass_tx = !fsp; + bool bypass_tx_rx = !fsp; dramc_get_vref_prop(rank, type, fsp, &vref_scan_enable, &vref_begin, &vref_end); @@ -1826,9 +1826,9 @@ vref_step = 2; } - if (fast_calib && bypass_tx && + if (fast_calib && bypass_tx_rx && (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM)) { - dramc_set_tx_best_dly(chn, rank, true, vref_dly.perbit_dly, + dramc_set_tx_best_dly(chn, rank, bypass_tx_rx, vref_dly.perbit_dly, type, freq_group, dq_precal_result, dly_cell_unit, params, fast_calib); @@ -1872,7 +1872,7 @@ RX_DQ, FIRST_DQ_DELAY); } - if (fast_calib && + if (fast_calib && bypass_tx_rx && (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG)) { dramc_dbg("bypass RX params\n"); for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00d563ece4cf91ef5e8e12b6cf7f777849375a24 Gerrit-Change-Number: 36921 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

7 17

Change in coreboot[master]: [WIP]drivers/aspeed: Add AST2500 support
by Patrick Rudolph (Code Review) 12 Dec '19

12 Dec '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34793 ) Change subject: [WIP]drivers/aspeed: Add AST2500 support ...................................................................... [WIP]drivers/aspeed: Add AST2500 support Untested on AST2500. Code for AST2400 still works. TODO: Adjust Copyright. Copy code from GNU/Linux kernel to coreboot to add AST2500 support. Change-Id: I25bd34dd52a0acd3e04fc5818e011215ef907fad Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/aspeed/common/ast_dp501.c M src/drivers/aspeed/common/ast_dram_tables.h M src/drivers/aspeed/common/ast_drv.h M src/drivers/aspeed/common/ast_post.c M src/drivers/aspeed/common/ast_tables.h 5 files changed, 656 insertions(+), 170 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/34793/1 diff --git a/src/drivers/aspeed/common/ast_dp501.c b/src/drivers/aspeed/common/ast_dp501.c index 2e8b897..4b867c0 100644 --- a/src/drivers/aspeed/common/ast_dp501.c +++ b/src/drivers/aspeed/common/ast_dp501.c @@ -145,7 +145,7 @@ return false; } -bool ast_launch_m68k(struct drm_device *dev) +static bool ast_launch_m68k(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; u32 i, data, len = 0; @@ -159,7 +159,10 @@ if (ast->dp501_fw_addr) { fw_addr = ast->dp501_fw_addr; len = 32*1024; - } else if (ast->dp501_fw) { + } else { + if (!ast->dp501_fw) + return false; + fw_addr = (u8 *)ast->dp501_fw->data; len = ast->dp501_fw->size; } @@ -224,11 +227,7 @@ /* Read Link Capability */ offset = 0xf014; - data = ast_mindwm(ast, boot_address + offset); - linkcap[0] = (data & 0xff000000) >> 24; - linkcap[1] = (data & 0x00ff0000) >> 16; - linkcap[2] = (data & 0x0000ff00) >> 8; - linkcap[3] = (data & 0x000000ff); + *(u32 *)linkcap = ast_mindwm(ast, boot_address + offset); if (linkcap[2] == 0) { linkrate = linkcap[0]; linklanes = linkcap[1]; diff --git a/src/drivers/aspeed/common/ast_dram_tables.h b/src/drivers/aspeed/common/ast_dram_tables.h index 1d46ca6..986b2c9 100644 --- a/src/drivers/aspeed/common/ast_dram_tables.h +++ b/src/drivers/aspeed/common/ast_dram_tables.h @@ -158,4 +158,66 @@ { 0xffff, 0xffffffff }, }; +/* + * AST2500 DRAM settings modules + */ +#define REGTBL_NUM 17 +#define REGIDX_010 0 +#define REGIDX_014 1 +#define REGIDX_018 2 +#define REGIDX_020 3 +#define REGIDX_024 4 +#define REGIDX_02C 5 +#define REGIDX_030 6 +#define REGIDX_214 7 +#define REGIDX_2E0 8 +#define REGIDX_2E4 9 +#define REGIDX_2E8 10 +#define REGIDX_2EC 11 +#define REGIDX_2F0 12 +#define REGIDX_2F4 13 +#define REGIDX_2F8 14 +#define REGIDX_RFC 15 +#define REGIDX_PLL 16 + +static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = { + 0x64604D38, /* 0x010 */ + 0x29690599, /* 0x014 */ + 0x00000300, /* 0x018 */ + 0x00000000, /* 0x020 */ + 0x00000000, /* 0x024 */ + 0x02181E70, /* 0x02C */ + 0x00000040, /* 0x030 */ + 0x00000024, /* 0x214 */ + 0x02001300, /* 0x2E0 */ + 0x0E0000A0, /* 0x2E4 */ + 0x000E001B, /* 0x2E8 */ + 0x35B8C105, /* 0x2EC */ + 0x08090408, /* 0x2F0 */ + 0x9B000800, /* 0x2F4 */ + 0x0E400A00, /* 0x2F8 */ + 0x9971452F, /* tRFC */ + 0x000071C1 /* PLL */ + }; + + static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = { + 0x63604E37, /* 0x010 */ + 0xE97AFA99, /* 0x014 */ + 0x00019000, /* 0x018 */ + 0x08000000, /* 0x020 */ + 0x00000400, /* 0x024 */ + 0x00000410, /* 0x02C */ + 0x00000101, /* 0x030 */ + 0x00000024, /* 0x214 */ + 0x03002900, /* 0x2E0 */ + 0x0E0000A0, /* 0x2E4 */ + 0x000E001C, /* 0x2E8 */ + 0x35B8C106, /* 0x2EC */ + 0x08080607, /* 0x2F0 */ + 0x9B000900, /* 0x2F4 */ + 0x0E400A00, /* 0x2F8 */ + 0x99714545, /* tRFC */ + 0x000071C1 /* PLL */ + }; + #endif diff --git a/src/drivers/aspeed/common/ast_drv.h b/src/drivers/aspeed/common/ast_drv.h index 53640f1..e2904c2 100644 --- a/src/drivers/aspeed/common/ast_drv.h +++ b/src/drivers/aspeed/common/ast_drv.h @@ -44,6 +44,7 @@ AST2150, AST2300, AST2400, + AST2500, AST1180, }; @@ -60,6 +61,7 @@ #define AST_DRAM_1Gx32 3 #define AST_DRAM_2Gx16 6 #define AST_DRAM_4Gx16 7 +#define AST_DRAM_8Gx16 8 struct ast_fbdev; @@ -213,11 +215,10 @@ u32 ast_mindwm(struct ast_private *ast, u32 r); void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); /* ast dp501 */ -int ast_load_dp501_microcode(struct drm_device *dev); void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); -bool ast_launch_m68k(struct drm_device *dev); bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); u8 ast_get_dp501_max_clk(struct drm_device *dev); void ast_init_3rdtx(struct drm_device *dev); +void ast_release_firmware(struct drm_device *dev); #endif diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index 5f935b9..dc825b5 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -34,7 +34,8 @@ #include "ast_drv.h" #include "ast_dram_tables.h" -static void ast_init_dram_2300(struct drm_device *dev); +static void ast_post_chip_2300(struct drm_device *dev); +static void ast_post_chip_2500(struct drm_device *dev); void ast_enable_vga(struct drm_device *dev) { @@ -61,13 +62,9 @@ /* TODO 1180 */ } else { ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT); - if (ch) { - ast_open_key(ast); - ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff); - return ch & 0x04; - } + return !!(ch & 0x01); } - return 0; + return false; } static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff }; @@ -86,10 +83,11 @@ uint8_t revision = data & 0xff; /* reset scratch */ - for (i = 0x81; i <= 0x8f; i++) + for (i = 0x81; i <= 0x9f; i++) ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); - if (ast->chip == AST2300 || ast->chip == AST2400) { + if (ast->chip == AST2300 || ast->chip == AST2400 || + ast->chip == AST2500) { if (revision >= 0x20) ext_reg_info = extreginfo_ast2300; else @@ -113,7 +111,8 @@ /* Enable RAMDAC for A1 */ reg = 0x04; - if (ast->chip == AST2300 || ast->chip == AST2400) + if (ast->chip == AST2300 || ast->chip == AST2400 || + ast->chip == AST2500) reg |= 0x20; ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); } @@ -394,12 +393,14 @@ pci_write_config_dword(ast->dev->pdev, 0x04, reg); ast_enable_vga(dev); - ast_enable_mmio(dev); ast_open_key(ast); + ast_enable_mmio(dev); ast_set_def_ext_reg(dev); - if (ast->chip == AST2300 || ast->chip == AST2400) - ast_init_dram_2300(dev); + if (ast->chip == AST2500) + ast_post_chip_2500(dev); + else if (ast->chip == AST2300 || ast->chip == AST2400) + ast_post_chip_2300(dev); else ast_init_dram_reg(dev); @@ -459,87 +460,72 @@ 0x7C61D253 }; -static int mmc_test_burst(struct ast_private *ast, u32 datagen) +static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl) { u32 data, timeout; ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3)); - timeout = 0; - do { - data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; - if (data & 0x2000) { - return 0; - } - if (++timeout > TIMEOUT) { - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - return 0; - } - } while (!data); - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - return 1; -} - -static int mmc_test_burst2(struct ast_private *ast, u32 datagen) -{ - u32 data, timeout; - - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3)); - timeout = 0; - do { - data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; - if (++timeout > TIMEOUT) { - ast_moutdwm(ast, 0x1e6e0070, 0x0); - return -1; - } - } while (!data); - data = ast_mindwm(ast, 0x1e6e0078); - data = (data | (data >> 16)) & 0xffff; - ast_moutdwm(ast, 0x1e6e0070, 0x0); - return data; -} - -static int mmc_test_single(struct ast_private *ast, u32 datagen) -{ - u32 data, timeout; - - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3)); + ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); timeout = 0; do { data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; if (data & 0x2000) - return 0; + return false; if (++timeout > TIMEOUT) { - ast_moutdwm(ast, 0x1e6e0070, 0x0); - return 0; + ast_moutdwm(ast, 0x1e6e0070, 0x00000000); + return false; } } while (!data); ast_moutdwm(ast, 0x1e6e0070, 0x0); - return 1; + return true; } -static int mmc_test_single2(struct ast_private *ast, u32 datagen) +static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl) { u32 data, timeout; ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3)); + ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); timeout = 0; do { data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; if (++timeout > TIMEOUT) { ast_moutdwm(ast, 0x1e6e0070, 0x0); - return -1; + return 0xffffffff; } } while (!data); data = ast_mindwm(ast, 0x1e6e0078); data = (data | (data >> 16)) & 0xffff; - ast_moutdwm(ast, 0x1e6e0070, 0x0); + ast_moutdwm(ast, 0x1e6e0070, 0x00000000); return data; } + +static bool mmc_test_burst(struct ast_private *ast, u32 datagen) +{ + return mmc_test(ast, datagen, 0xc1); +} + +static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen) +{ + return mmc_test2(ast, datagen, 0x41); +} + +static bool mmc_test_single(struct ast_private *ast, u32 datagen) +{ + return mmc_test(ast, datagen, 0xc5); +} + +static u32 mmc_test_single2(struct ast_private *ast, u32 datagen) +{ + return mmc_test2(ast, datagen, 0x05); +} + +static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen) +{ + return mmc_test(ast, datagen, 0x85); +} + static int cbr_test(struct ast_private *ast) { u32 data; @@ -615,16 +601,16 @@ return data2; } -static u32 cbr_test3(struct ast_private *ast) +static bool cbr_test3(struct ast_private *ast) { if (!mmc_test_burst(ast, 0)) - return 0; + return false; if (!mmc_test_single(ast, 0)) - return 0; - return 1; + return false; + return true; } -static u32 cbr_scan3(struct ast_private *ast) +static bool cbr_scan3(struct ast_private *ast) { u32 patcnt, loop; @@ -635,9 +621,9 @@ break; } if (loop == 2) - return 0; + return false; } - return 1; + return true; } static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param) @@ -1661,7 +1647,7 @@ } -static void ast_init_dram_2300(struct drm_device *dev) +static void ast_post_chip_2300(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; struct ast2300_dram_param param; @@ -1746,11 +1732,409 @@ } /* wait ready */ - timeout = 0; do { reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); - timeout++; - } while (((reg & 0x40) == 0) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT)); - if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) - dev_err(dev->pdev, "Timeout while waiting for register\n"); + } while ((reg & 0x40) == 0); +} + +static bool cbr_test_2500(struct ast_private *ast) +{ + ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); + ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); + if (!mmc_test_burst(ast, 0)) + return false; + if (!mmc_test_single_2500(ast, 0)) + return false; + return true; +} + +static bool ddr_test_2500(struct ast_private *ast) +{ + ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); + ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); + if (!mmc_test_burst(ast, 0)) + return false; + if (!mmc_test_burst(ast, 1)) + return false; + if (!mmc_test_burst(ast, 2)) + return false; + if (!mmc_test_burst(ast, 3)) + return false; + if (!mmc_test_single_2500(ast, 0)) + return false; + return true; +} + +static void ddr_init_common_2500(struct ast_private *ast) +{ + ast_moutdwm(ast, 0x1E6E0034, 0x00020080); + ast_moutdwm(ast, 0x1E6E0008, 0x2003000F); + ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF); + ast_moutdwm(ast, 0x1E6E0040, 0x88448844); + ast_moutdwm(ast, 0x1E6E0044, 0x24422288); + ast_moutdwm(ast, 0x1E6E0048, 0x22222222); + ast_moutdwm(ast, 0x1E6E004C, 0x22222222); + ast_moutdwm(ast, 0x1E6E0050, 0x80000000); + ast_moutdwm(ast, 0x1E6E0208, 0x00000000); + ast_moutdwm(ast, 0x1E6E0218, 0x00000000); + ast_moutdwm(ast, 0x1E6E0220, 0x00000000); + ast_moutdwm(ast, 0x1E6E0228, 0x00000000); + ast_moutdwm(ast, 0x1E6E0230, 0x00000000); + ast_moutdwm(ast, 0x1E6E02A8, 0x00000000); + ast_moutdwm(ast, 0x1E6E02B0, 0x00000000); + ast_moutdwm(ast, 0x1E6E0240, 0x86000000); + ast_moutdwm(ast, 0x1E6E0244, 0x00008600); + ast_moutdwm(ast, 0x1E6E0248, 0x80000000); + ast_moutdwm(ast, 0x1E6E024C, 0x80808080); +} + +static void ddr_phy_init_2500(struct ast_private *ast) +{ + u32 data, pass, timecnt; + + pass = 0; + ast_moutdwm(ast, 0x1E6E0060, 0x00000005); + while (!pass) { + for (timecnt = 0; timecnt < TIMEOUT; timecnt++) { + data = ast_mindwm(ast, 0x1E6E0060) & 0x1; + if (!data) + break; + } + if (timecnt != TIMEOUT) { + data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000; + if (!data) + pass = 1; + } + if (!pass) { + ast_moutdwm(ast, 0x1E6E0060, 0x00000000); + udelay(10); /* delay 10 us */ + ast_moutdwm(ast, 0x1E6E0060, 0x00000005); + } + } + + ast_moutdwm(ast, 0x1E6E0060, 0x00000006); +} + +/* + * Check DRAM Size + * 1Gb : 0x80000000 ~ 0x87FFFFFF + * 2Gb : 0x80000000 ~ 0x8FFFFFFF + * 4Gb : 0x80000000 ~ 0x9FFFFFFF + * 8Gb : 0x80000000 ~ 0xBFFFFFFF + */ +static void check_dram_size_2500(struct ast_private *ast, u32 tRFC) +{ + u32 reg_04, reg_14; + + reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc; + reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00; + + ast_moutdwm(ast, 0xA0100000, 0x41424344); + ast_moutdwm(ast, 0x90100000, 0x35363738); + ast_moutdwm(ast, 0x88100000, 0x292A2B2C); + ast_moutdwm(ast, 0x80100000, 0x1D1E1F10); + + /* Check 8Gbit */ + if (ast_mindwm(ast, 0xA0100000) == 0x41424344) { + reg_04 |= 0x03; + reg_14 |= (tRFC >> 24) & 0xFF; + /* Check 4Gbit */ + } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) { + reg_04 |= 0x02; + reg_14 |= (tRFC >> 16) & 0xFF; + /* Check 2Gbit */ + } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) { + reg_04 |= 0x01; + reg_14 |= (tRFC >> 8) & 0xFF; + } else { + reg_14 |= tRFC & 0xFF; + } + ast_moutdwm(ast, 0x1E6E0004, reg_04); + ast_moutdwm(ast, 0x1E6E0014, reg_14); +} + +static void enable_cache_2500(struct ast_private *ast) +{ + u32 reg_04, data; + + reg_04 = ast_mindwm(ast, 0x1E6E0004); + ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000); + + do + data = ast_mindwm(ast, 0x1E6E0004); + while (!(data & 0x80000)); + ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400); +} + +static void set_mpll_2500(struct ast_private *ast) +{ + u32 addr, data, param; + + /* Reset MMC */ + ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); + ast_moutdwm(ast, 0x1E6E0034, 0x00020080); + for (addr = 0x1e6e0004; addr < 0x1e6e0090;) { + ast_moutdwm(ast, addr, 0x0); + addr += 4; + } + ast_moutdwm(ast, 0x1E6E0034, 0x00020000); + + ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); + data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000; + if (data) { + /* CLKIN = 25MHz */ + param = 0x930023E0; + ast_moutdwm(ast, 0x1E6E2160, 0x00011320); + } else { + /* CLKIN = 24MHz */ + param = 0x93002400; + } + ast_moutdwm(ast, 0x1E6E2020, param); + udelay(100); +} + +static void reset_mmc_2500(struct ast_private *ast) +{ + ast_moutdwm(ast, 0x1E78505C, 0x00000004); + ast_moutdwm(ast, 0x1E785044, 0x00000001); + ast_moutdwm(ast, 0x1E785048, 0x00004755); + ast_moutdwm(ast, 0x1E78504C, 0x00000013); + mdelay(100); + ast_moutdwm(ast, 0x1E785054, 0x00000077); + ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); +} + +static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table) +{ + + ast_moutdwm(ast, 0x1E6E0004, 0x00000303); + ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); + ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); + ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); + ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ + ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ + ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ + ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ + + /* DDR PHY Setting */ + ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE); + ast_moutdwm(ast, 0x1E6E0204, 0x00001001); + ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); + ast_moutdwm(ast, 0x1E6E0210, 0x20000000); + ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); + ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); + ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); + ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); + ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); + ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); + ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); + ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); + ast_moutdwm(ast, 0x1E6E0290, 0x00100008); + ast_moutdwm(ast, 0x1E6E02C0, 0x00000006); + + /* Controller Setting */ + ast_moutdwm(ast, 0x1E6E0034, 0x00020091); + + /* Wait DDR PHY init done */ + ddr_phy_init_2500(ast); + + ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); + ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); + ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); + + check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); + enable_cache_2500(ast); + ast_moutdwm(ast, 0x1E6E001C, 0x00000008); + ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); +} + +static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table) +{ + u32 data, data2, pass, retrycnt; + u32 ddr_vref, phy_vref; + u32 min_ddr_vref = 0, min_phy_vref = 0; + u32 max_ddr_vref = 0, max_phy_vref = 0; + + ast_moutdwm(ast, 0x1E6E0004, 0x00000313); + ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); + ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); + ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); + ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ + ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ + ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ + ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ + + /* DDR PHY Setting */ + ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE); + ast_moutdwm(ast, 0x1E6E0204, 0x09002000); + ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); + ast_moutdwm(ast, 0x1E6E0210, 0x20000000); + ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); + ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); + ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); + ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); + ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); + ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); + ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); + ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); + ast_moutdwm(ast, 0x1E6E0290, 0x00100008); + ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C); + ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E); + + /* Controller Setting */ + ast_moutdwm(ast, 0x1E6E0034, 0x0001A991); + + /* Train PHY Vref first */ + pass = 0; + + for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) { + max_phy_vref = 0x0; + pass = 0; + ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06); + for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) { + ast_moutdwm(ast, 0x1E6E000C, 0x00000000); + ast_moutdwm(ast, 0x1E6E0060, 0x00000000); + ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8)); + /* Fire DFI Init */ + ddr_phy_init_2500(ast); + ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); + if (cbr_test_2500(ast)) { + pass++; + data = ast_mindwm(ast, 0x1E6E03D0); + data2 = data >> 8; + data = data & 0xff; + if (data > data2) + data = data2; + if (max_phy_vref < data) { + max_phy_vref = data; + min_phy_vref = phy_vref; + } + } else if (pass > 0) + break; + } + } + ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8)); + + /* Train DDR Vref next */ + pass = 0; + + for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) { + min_ddr_vref = 0xFF; + max_ddr_vref = 0x0; + pass = 0; + for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) { + ast_moutdwm(ast, 0x1E6E000C, 0x00000000); + ast_moutdwm(ast, 0x1E6E0060, 0x00000000); + ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); + /* Fire DFI Init */ + ddr_phy_init_2500(ast); + ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); + if (cbr_test_2500(ast)) { + pass++; + if (min_ddr_vref > ddr_vref) + min_ddr_vref = ddr_vref; + if (max_ddr_vref < ddr_vref) + max_ddr_vref = ddr_vref; + } else if (pass != 0) + break; + } + } + + ast_moutdwm(ast, 0x1E6E000C, 0x00000000); + ast_moutdwm(ast, 0x1E6E0060, 0x00000000); + ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1; + ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); + + /* Wait DDR PHY init done */ + ddr_phy_init_2500(ast); + + ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); + ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); + ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); + + check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); + enable_cache_2500(ast); + ast_moutdwm(ast, 0x1E6E001C, 0x00000008); + ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); +} + +static bool ast_dram_init_2500(struct ast_private *ast) +{ + u32 data; + u32 max_tries = 5; + + do { + if (max_tries-- == 0) + return false; + set_mpll_2500(ast); + reset_mmc_2500(ast); + ddr_init_common_2500(ast); + + data = ast_mindwm(ast, 0x1E6E2070); + if (data & 0x01000000) + ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table); + else + ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table); + } while (!ddr_test_2500(ast)); + + ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41); + + /* Patch code */ + data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF; + ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000); + + return true; +} + +void ast_post_chip_2500(struct drm_device *dev) +{ + struct ast_private *ast = dev->dev_private; + u32 temp; + u8 reg; + + reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); + if ((reg & 0x80) == 0) {/* vga only */ + /* Clear bus lock condition */ + ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); + ast_moutdwm(ast, 0x1e600084, 0x00010000); + ast_moutdwm(ast, 0x1e600088, 0x00000000); + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); + ast_write32(ast, 0xf004, 0x1e6e0000); + ast_write32(ast, 0xf000, 0x1); + ast_write32(ast, 0x12000, 0x1688a8a8); + while (ast_read32(ast, 0x12000) != 0x1) + ; + + ast_write32(ast, 0x10000, 0xfc600309); + while (ast_read32(ast, 0x10000) != 0x1) + ; + + /* Slow down CPU/AHB CLK in VGA only mode */ + temp = ast_read32(ast, 0x12008); + temp |= 0x73; + ast_write32(ast, 0x12008, temp); + + /* Reset USB port to patch USB unknown device issue */ + ast_moutdwm(ast, 0x1e6e2090, 0x20000000); + temp = ast_mindwm(ast, 0x1e6e2094); + temp |= 0x00004000; + ast_moutdwm(ast, 0x1e6e2094, temp); + temp = ast_mindwm(ast, 0x1e6e2070); + if (temp & 0x00800000) { + ast_moutdwm(ast, 0x1e6e207c, 0x00800000); + mdelay(100); + ast_moutdwm(ast, 0x1e6e2070, 0x00800000); + } + + if (!ast_dram_init_2500(ast)) + printk(BIOS_ERR, "AST: DRAM init failed !\n"); + + temp = ast_mindwm(ast, 0x1e6e2040); + ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); + } + + /* wait ready */ + do { + reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); + } while ((reg & 0x40) == 0); } diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index 6c20f36..d665dd5 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -47,68 +47,99 @@ #define SyncPN (PVSync | NHSync) #define SyncNP (NVSync | PHSync) #define SyncNN (NVSync | NHSync) +#define AST2500PreCatchCRT 0x00004000 /* DCLK Index */ -#define VCLK25_175 0x00 -#define VCLK28_322 0x01 -#define VCLK31_5 0x02 -#define VCLK36 0x03 -#define VCLK40 0x04 -#define VCLK49_5 0x05 -#define VCLK50 0x06 -#define VCLK56_25 0x07 -#define VCLK65 0x08 -#define VCLK75 0x09 -#define VCLK78_75 0x0A -#define VCLK94_5 0x0B -#define VCLK108 0x0C -#define VCLK135 0x0D -#define VCLK157_5 0x0E -#define VCLK162 0x0F -/* #define VCLK193_25 0x10 */ -#define VCLK154 0x10 -#define VCLK83_5 0x11 -#define VCLK106_5 0x12 -#define VCLK146_25 0x13 -#define VCLK148_5 0x14 -#define VCLK71 0x15 -#define VCLK88_75 0x16 -#define VCLK119 0x17 -#define VCLK85_5 0x18 -#define VCLK97_75 0x19 -#define VCLK118_25 0x1A +#define VCLK25_175 0x00 +#define VCLK28_322 0x01 +#define VCLK31_5 0x02 +#define VCLK36 0x03 +#define VCLK40 0x04 +#define VCLK49_5 0x05 +#define VCLK50 0x06 +#define VCLK56_25 0x07 +#define VCLK65 0x08 +#define VCLK75 0x09 +#define VCLK78_75 0x0A +#define VCLK94_5 0x0B +#define VCLK108 0x0C +#define VCLK135 0x0D +#define VCLK157_5 0x0E +#define VCLK162 0x0F +/* #define VCLK193_25 0x10 */ +#define VCLK154 0x10 +#define VCLK83_5 0x11 +#define VCLK106_5 0x12 +#define VCLK146_25 0x13 +#define VCLK148_5 0x14 +#define VCLK71 0x15 +#define VCLK88_75 0x16 +#define VCLK119 0x17 +#define VCLK85_5 0x18 +#define VCLK97_75 0x19 +#define VCLK118_25 0x1A -static struct ast_vbios_dclk_info dclk_table[] = { - {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ - {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ - {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ - {0x76, 0x63, 0x01}, /* 03: VCLK36 */ - {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ - {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ - {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ - {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ - {0x80, 0x64, 0x00}, /* 08: VCLK65 */ - {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ - {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ - {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ - {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ - {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ - {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ - {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ - {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ - {0xa7, 0x78, 0x80}, /* 11: VCLK83.5 */ - {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ - {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ - {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ - {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ - {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ - {0x77, 0x58, 0x80}, /* 17: VCLK119 */ - {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ - {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ - {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */ +static const struct ast_vbios_dclk_info dclk_table[] = { + {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ + {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ + {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ + {0x76, 0x63, 0x01}, /* 03: VCLK36 */ + {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ + {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ + {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ + {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ + {0x80, 0x64, 0x00}, /* 08: VCLK65 */ + {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ + {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ + {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ + {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ + {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ + {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ + {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ + {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ + {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ + {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ + {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ + {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ + {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ + {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ + {0x77, 0x58, 0x80}, /* 17: VCLK119 */ + {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ + {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ + {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */ }; -static struct ast_vbios_stdtable vbios_stdtable[] = { +static const struct ast_vbios_dclk_info dclk_table_ast2500[] = { + {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ + {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ + {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ + {0x76, 0x63, 0x01}, /* 03: VCLK36 */ + {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ + {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ + {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ + {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ + {0x80, 0x64, 0x00}, /* 08: VCLK65 */ + {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ + {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ + {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ + {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ + {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ + {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ + {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ + {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ + {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ + {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ + {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ + {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ + {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ + {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ + {0x58, 0x01, 0x42}, /* 17: VCLK119 */ + {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ + {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ + {0x44, 0x20, 0x43}, /* 1A: VCLK118_25 */ +}; + +static const struct ast_vbios_stdtable vbios_stdtable[] = { /* MD_2_3_400 */ { 0x67, @@ -181,7 +212,7 @@ }, }; -static struct ast_vbios_enhtable res_640x480[] = { +static const struct ast_vbios_enhtable res_640x480[] = { { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175, /* 60Hz */ (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E }, { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ @@ -194,7 +225,7 @@ (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, }; -static struct ast_vbios_enhtable res_800x600[] = { +static const struct ast_vbios_enhtable res_800x600[] = { {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */ (SyncPP | Charx8Dot), 56, 1, 0x30 }, {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60Hz */ @@ -210,7 +241,7 @@ }; -static struct ast_vbios_enhtable res_1024x768[] = { +static const struct ast_vbios_enhtable res_1024x768[] = { {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */ (SyncNN | Charx8Dot), 60, 1, 0x31 }, {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75, /* 70Hz */ @@ -223,7 +254,7 @@ (SyncPP | Charx8Dot), 0xFF, 4, 0x31 }, }; -static struct ast_vbios_enhtable res_1280x1024[] = { +static const struct ast_vbios_enhtable res_1280x1024[] = { {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108, /* 60Hz */ (SyncPP | Charx8Dot), 60, 1, 0x32 }, {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135, /* 75Hz */ @@ -234,7 +265,7 @@ (SyncPP | Charx8Dot), 0xFF, 3, 0x32 }, }; -static struct ast_vbios_enhtable res_1600x1200[] = { +static const struct ast_vbios_enhtable res_1600x1200[] = { {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* 60Hz */ (SyncPP | Charx8Dot), 60, 1, 0x33 }, {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* end */ @@ -242,34 +273,39 @@ }; /* 16:9 */ -static struct ast_vbios_enhtable res_1360x768[] = { - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ +static const struct ast_vbios_enhtable res_1360x768[] = { + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 }, - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */ - (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 }, + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* end */ + (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 0xFF, 1, 0x39 }, }; -static struct ast_vbios_enhtable res_1600x900[] = { - {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ +static const struct ast_vbios_enhtable res_1600x900[] = { + {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x3A }, + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A }, }; -static struct ast_vbios_enhtable res_1920x1080[] = { +static const struct ast_vbios_enhtable res_1920x1080[] = { {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x38 }, {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x38 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 0xFF, 1, 0x38 }, }; /* 16:10 */ -static struct ast_vbios_enhtable res_1280x800[] = { +static const struct ast_vbios_enhtable res_1280x800[] = { {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x35 }, {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 }, {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ @@ -277,29 +313,33 @@ }; -static struct ast_vbios_enhtable res_1440x900[] = { +static const struct ast_vbios_enhtable res_1440x900[] = { {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x36 }, {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 }, {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 }, }; -static struct ast_vbios_enhtable res_1680x1050[] = { +static const struct ast_vbios_enhtable res_1680x1050[] = { {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x37 }, {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 }, {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 }, }; -static struct ast_vbios_enhtable res_1920x1200[] = { +static const struct ast_vbios_enhtable res_1920x1200[] = { {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB*/ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 }, - {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x34 }, + {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB */ + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 0xFF, 1, 0x34 }, }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25bd34dd52a0acd3e04fc5818e011215ef907fad Gerrit-Change-Number: 34793 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Use ACPI timer config from soc common code
by Meera Ravindranath (Code Review) 12 Dec '19

12 Dec '19

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36064 ) Change subject: soc/intel/cannonlake: Use ACPI timer config from soc common code ...................................................................... soc/intel/cannonlake: Use ACPI timer config from soc common code Replace the usage of structure member "PMTimerDisabled" of struct "soc_intel_cannonlake_config" in soc code with ACPI timer config defined under soc/intel/common/block/timer/Kconfig. BUG=none TEST=none Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c 6 files changed, 4 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36064/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7382209..d7c975f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -56,8 +56,6 @@ # putting it under register "common_soc_config" in overridetree.cb file. register "common_soc_config.pch_thermal_trip" = "77" - register "PmTimerDisabled" = "1" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 6846594..22a8a40 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -179,7 +179,7 @@ const struct soc_intel_cannonlake_config *config; config = config_of_soc(); - if (!config->PmTimerDisabled) { + if (CONFIG_USE_ACPI_PM_TIMER) { fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->pm_tmr_len = 4; fadt->x_pm_tmr_blk.space_id = 1; diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b937699..29ce25a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -267,7 +267,6 @@ * 0x02000000 - 32MiB and beyond */ uint32_t PrmrrSize; - uint8_t PmTimerDisabled; /* * SLP_S3 Minimum Assertion Width Policy diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index c58b9ad..bfb6bd1 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -390,7 +390,7 @@ config = config_of_soc(); /* Enable PM timer emulation only if ACPI PM timer is disabled */ - if (!config->PmTimerDisabled) + if (CONFIG_USE_ACPI_PM_TIMER) return; /* * The derived frequency is calculated as follows: diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 115b732..3ffc942 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -86,7 +86,7 @@ */ config = config_of_soc(); pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { + if (!CONFIG_USE_ACPI_PM_TIMER) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); reg8 |= (1 << 1); write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index b580620..2dd85ed 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -380,7 +380,7 @@ params->SataPwrOptEnable = config->satapwroptimize; /* Disable PCH ACPI timer */ - params->EnableTcoTimer = !config->PmTimerDisabled; + params->EnableTcoTimer = CONFIG_USE_ACPI_PM_TIMER; /* Apply minimum assertion width settings if non-zero */ if (config->PchPmSlpS3MinAssert) -- To view, visit https://review.coreboot.org/c/coreboot/+/36064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348 Gerrit-Change-Number: 36064 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP, DONOTMERGE] soc/intel: (try to) run clang-format
by Angel Pons (Code Review) 11 Dec '19

11 Dec '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35090 ) Change subject: [WIP, DONOTMERGE] soc/intel: (try to) run clang-format ...................................................................... [WIP, DONOTMERGE] soc/intel: (try to) run clang-format Change-Id: I4a1e646d81da329479d6179ed1a42879b5d10fee Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/uart.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/cannonlake/uart.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/icelake/uart.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/uart.c M src/soc/intel/skylake/vr_config.c 37 files changed, 2,180 insertions(+), 2,595 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/35090/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a1e646d81da329479d6179ed1a42879b5d10fee Gerrit-Change-Number: 35090 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019