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Change in coreboot[master]: mb/lenovo/l520/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 09 Dec '19

09 Dec '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37296 ) Change subject: mb/lenovo/l520/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/l520/devicetree: Use subsystemid inheritance Change-Id: I90774e22fb7765f44b6cd4fa05b535236b782023 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/l520/devicetree.cb 1 file changed, 39 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/37296/1 diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 024b8f8..29b7598 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -15,7 +15,7 @@ register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" - device cpu_cluster 0x0 on + device cpu_cluster 0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" register "c1_battery" = "1" @@ -28,15 +28,13 @@ end end - device domain 0x0 on - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x17aa 0x21dd - end - device pci 01.0 on # PCIe Bridge for discrete graphics - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x17aa 0x21dd - end + device domain 0 on + subsystemid 0x17aa 0x21dd inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "1" @@ -54,57 +52,28 @@ register "spi_uvscc" = "0" register "spi_lvscc" = "0x2005" - device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x17aa 0x21dd - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 off # Management Engine KT - end - device pci 19.0 off # Intel Gigabit Ethernet - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x17aa 0x21dd - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x17aa 0x21dd - end - device pci 1c.0 on # PCIe Port #1 - subsystemid 0x17aa 0x21dd - end - device pci 1c.1 on # PCIe Port #2 - subsystemid 0x17aa 0x21dd - end - device pci 1c.2 on # PCIe Port #3 - subsystemid 0x17aa 0x21dd - end - device pci 1c.3 on # PCIe Port #4 - subsystemid 0x17aa 0x21dd - end - device pci 1c.4 on # PCIe Port #5 - subsystemid 0x17aa 0x21dd - end - device pci 1c.5 on # PCIe Port #6 - subsystemid 0x17aa 0x21dd - end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x17aa 0x21dd - end - device pci 1e.0 off # PCI bridge - end + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x17aa 0x21dd chip ec/lenovo/pmh7 register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy end chip ec/lenovo/h8 register "config0" = "0xa7" @@ -136,35 +105,22 @@ io 0x66 = 0x1604 end end - end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x17aa 0x21dd - end + end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBus - subsystemid 0x17aa 0x21dd chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip - device i2c 54 on - end - device i2c 55 on - end - device i2c 56 on - end - device i2c 57 on - end - device i2c 5c on - end - device i2c 5d on - end - device i2c 5e on - end - device i2c 5f on - end + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end end - end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90774e22fb7765f44b6cd4fa05b535236b782023 Gerrit-Change-Number: 37296 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/lenovo/t420s/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 09 Dec '19

09 Dec '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37285 ) Change subject: mb/lenovo/t420s/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/t420s/devicetree: Use subsystemid inheritance Change-Id: Ia77f0ce89b2234b9c164bb326d76bef98949832a Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t420s/devicetree.cb 1 file changed, 13 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/37285/1 diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index aa6cc68..d4c69dc 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + # IGD Displays register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" @@ -36,9 +37,9 @@ register "pci_mmio_size" = "2048" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21d2 - end # host bridge + subsystemid 0x17aa 0x21d2 inherit + + device pci 00.0 on end # host bridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] device pci 02.0 on subsystemid 0x17aa 0x21d3 @@ -69,6 +70,7 @@ register "c2_latency" = "101" # c2 not supported + # device specific SPI configuration register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" @@ -79,36 +81,23 @@ device pci 19.0 on subsystemid 0x17aa 0x21ce end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21d2 - end # USB Enhanced Host Controller #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21d2 - end # High Definition Audio Controller + device pci 1a.0 on end # USB Enhanced Host Controller #2 + device pci 1b.0 on end # High Definition Audio Controller device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21d2 - end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 on - subsystemid 0x17aa 0x21d2 smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) - device pci 1c.6 on - subsystemid 0x17aa 0x21d2 - end # PCIe Port #7 NEC Corporation uPD720200A USB 3.0 Host Controller + device pci 1c.6 on end # PCIe Port #7 NEC Corporation uPD720200A USB 3.0 Host Controller device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21d2 - end # USB Enhanced Host Controller #1 + device pci 1d.0 on end # USB Enhanced Host Controller #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on - subsystemid 0x17aa 0x21d2 chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -168,11 +157,8 @@ register "has_thinker1" = "1" end end # LPC Controller - device pci 1f.2 on - subsystemid 0x17aa 0x21d2 - end # 6 port SATA AHCI Controller + device pci 1f.2 on end # 6 port SATA AHCI Controller device pci 1f.3 on - subsystemid 0x17aa 0x21d2 # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -186,9 +172,7 @@ end end # SMBus Controller device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21d2 - end # Thermal + device pci 1f.6 on end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia77f0ce89b2234b9c164bb326d76bef98949832a Gerrit-Change-Number: 37285 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: mb/lenovo/t420/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 09 Dec '19

09 Dec '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37284 ) Change subject: mb/lenovo/t420/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/t420/devicetree: Use subsystemid inheritance Change-Id: Ia321f2b974539ac1684173d767dd9eb64060364a Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t420/devicetree.cb 1 file changed, 14 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/37284/1 diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 6deff60..53bd16f 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -37,13 +37,11 @@ register "pci_mmio_size" = "2048" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21ce - end # host bridge + subsystemid 0x17aa 0x21ce inherit + + device pci 00.0 on end # host bridge device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x21ce - end # Integrated Graphics Controller + device pci 02.0 on end # Integrated Graphics Controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -67,6 +65,7 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" # c2 not supported # device specific SPI configuration @@ -77,46 +76,30 @@ device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT - device pci 19.0 on - subsystemid 0x17aa 0x21ce - end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21ce - end # USB Enhanced Host Controller #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21ce - end # High Definition Audio Controller + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB Enhanced Host Controller #2 + device pci 1b.0 on end # High Definition Audio Controller device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21ce - end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 on - subsystemid 0x17aa 0x21ce smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard device pci 1c.4 on - subsystemid 0x17aa 0x21ce chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" - device pci 00.0 on - subsystemid 0x17aa 0x21ce - end + device pci 00.0 on end end end # PCIe Port #5 (Ricoh SD & FW) device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21ce - end # USB Enhanced Host Controller #1 + device pci 1d.0 on end # USB Enhanced Host Controller #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on - subsystemid 0x17aa 0x21ce chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -176,11 +159,8 @@ register "has_thinker1" = "1" end end # LPC Controller - device pci 1f.2 on - subsystemid 0x17aa 0x21ce - end # 6 port SATA AHCI Controller + device pci 1f.2 on end # 6 port SATA AHCI Controller device pci 1f.3 on - subsystemid 0x17aa 0x21ce # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -194,9 +174,7 @@ end end # SMBus Controller device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21ce - end # Thermal + device pci 1f.6 on end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia321f2b974539ac1684173d767dd9eb64060364a Gerrit-Change-Number: 37284 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: [WIP] mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant
by Bill XIE (Code Review) 09 Dec '19

09 Dec '19

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36992 ) Change subject: [WIP] mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ...................................................................... [WIP] mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant It is an ATX board similar to existing ga-b75* boards. The major difference is the configuration of pci-e ports on PCH, and on-board pci-e NIC. (see below) Tested: - CPU i5 3570T - Slotted DIMM 8GiB*4 from Kingston - usb2 and usb3 - libgfxinit-based graphic init - NVRAM options for North and South bridges - tpm 1.2 on lpc (similar to ga-b75m-d3h) - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Seabios. Should work: - sata - Sound - S3 Unstable: - some pci-e devices connected to pch (including the AR8161 below attached to 1c.2) breaks RTC init and causes hang in mc146818rtc.c:__cmos_init(), possibly related to power consumption. TODO: Add AR8161 support. (it is supported by driver "alx" in Linux kernel, and the logic to set mac address is essentially identical to the one for atl1e, but the logic to detect address burned in efuse and external rom are different) Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/overridetree.cb A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/overridetree.cb 9 files changed, 348 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36992/1 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index ceb2dbc..7fd030a 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -1,4 +1,4 @@ -if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V +if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V || BOARD_GIGABYTE_GA_B75_D3V config BOARD_SPECIFIC_OPTIONS def_bool y @@ -34,11 +34,17 @@ string default "ga-b75m-d3h" if BOARD_GIGABYTE_GA_B75M_D3H default "ga-b75m-d3v" if BOARD_GIGABYTE_GA_B75M_D3V + default "ga-b75-d3v" if BOARD_GIGABYTE_GA_B75_D3V config MAINBOARD_PART_NUMBER string default "GA-B75M-D3H" if BOARD_GIGABYTE_GA_B75M_D3H default "GA-B75M-D3V" if BOARD_GIGABYTE_GA_B75M_D3V + default "GA-B75-D3V" if BOARD_GIGABYTE_GA_B75_D3V + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAX_CPUS int @@ -49,4 +55,4 @@ string default "src/mainboard/$(MAINBOARDDIR)/data.vbt" -endif # BOARD_GIGABYTE_GA_B75M* +endif # BOARD_GIGABYTE_GA_B75* diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name index f8fbe54..93f73a5 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name @@ -3,3 +3,6 @@ config BOARD_GIGABYTE_GA_B75M_D3V bool "GA-B75M-D3V" + +config BOARD_GIGABYTE_GA_B75_D3V + bool "GA-B75-D3V" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt new file mode 100644 index 0000000..f90483f --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.gigabyte.com/Motherboard/GA-B75-D3V-rev-11 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads new file mode 100644 index 0000000..416732d --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads @@ -0,0 +1,28 @@ +-- +-- Copyright (C) 2017 Bill XIE persmule(a)gmail.com +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c new file mode 100644 index 0000000..763dfad --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h new file mode 100644 index 0000000..c92c625 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef GA_B75_D3V_HDA_VERB_H +#define GA_B75_D3V_HDA_VERB_H + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0887, // Realtek 887 + 0x1458a002, // Subsystem ID + 0x0000000e, // Number of entries + + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x1458a002), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x2, 0x11, 0x99430130), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), +}; + +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb new file mode 100644 index 0000000..e5b7285 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb @@ -0,0 +1,26 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + device pci 16.0 off end # Management Engine Interface 1 + register "xhci_overcurrent_mapping" = "0x00000c03" + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on + device pci 00.0 on # PCI 1969:1091 + subsystemid 0x1458 0xe000 + end + end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1f.0 on # ISA/LPC bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8728f + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # LPT + device pnp 2e.4 on # EC + io 0x62 = 0x230 + end + end + end + end + end +end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/overridetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/overridetree.cb new file mode 100644 index 0000000..dbe35ba --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/overridetree.cb @@ -0,0 +1,3 @@ +chip northbridge/intel/sandybridge + device domain 0 on end +end \ No newline at end of file diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/overridetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/overridetree.cb new file mode 100644 index 0000000..dbe35ba --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/overridetree.cb @@ -0,0 +1,3 @@ +chip northbridge/intel/sandybridge + device domain 0 on end +end \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/36992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Gerrit-Change-Number: 36992 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

5 26

Change in coreboot[master]: Documentation: Move ACPI documentation in a subindex
by Arthur Heymans (Code Review) 09 Dec '19

09 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37242 ) Change subject: Documentation: Move ACPI documentation in a subindex ...................................................................... Documentation: Move ACPI documentation in a subindex Change-Id: I17c5263674b805a73d98aaa3e7090083905e37ef Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A Documentation/acpi/index.md M Documentation/index.md 2 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/37242/1 diff --git a/Documentation/acpi/index.md b/Documentation/acpi/index.md new file mode 100644 index 0000000..8add8db --- /dev/null +++ b/Documentation/acpi/index.md @@ -0,0 +1,11 @@ +# ACPI-specific documentation + +This section contains documentation about coreboot on ACPI. + +## GPIO + +- [GPIO toggling in ACPI AML](gpio.md) + +## devicetree + +- [Adding devices to a device tree](devicetree.md) diff --git a/Documentation/index.md b/Documentation/index.md index 3ed6bd3..bfc9cea 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -171,8 +171,7 @@ * [Payloads](payloads.md) * [Distributions](distributions.md) * [Technotes](technotes/index.md) -* [GPIO toggling in ACPI AML](acpi/gpio.md) -* [Adding devices to a device tree](acpi/devicetree.md) +* [ACPI](acpi/index.md) * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) * [Display panel](gfx/display-panel.md) * [CPU Architecture](arch/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/37242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17c5263674b805a73d98aaa3e7090083905e37ef Gerrit-Change-Number: 37242 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: Documentation: Remove redundant 'documentation'
by Arthur Heymans (Code Review) 09 Dec '19

09 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37241 ) Change subject: Documentation: Remove redundant 'documentation' ...................................................................... Documentation: Remove redundant 'documentation' We are already in documentation so it should be obvious that other links point to other documentation. Change-Id: I7a021a09bdb88418ec85dbf433465f26445057d0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/index.md 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37241/1 diff --git a/Documentation/index.md b/Documentation/index.md index 8a996b9..3ed6bd3 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -174,17 +174,17 @@ * [GPIO toggling in ACPI AML](acpi/gpio.md) * [Adding devices to a device tree](acpi/devicetree.md) * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) -* [Display panel-specific documentation](gfx/display-panel.md) -* [Architecture-specific documentation](arch/index.md) -* [Platform independend drivers documentation](drivers/index.md) -* [Northbridge-specific documentation](northbridge/index.md) -* [System on Chip-specific documentation](soc/index.md) -* [Mainboard-specific documentation](mainboard/index.md) -* [Payload-specific documentation](lib/payloads/index.md) -* [Library-specific documentation](lib/index.md) +* [Display panel](gfx/display-panel.md) +* [CPU Architecture](arch/index.md) +* [Platform independend drivers](drivers/index.md) +* [Northbridge](northbridge/index.md) +* [System on Chip](soc/index.md) +* [Mainboard](mainboard/index.md) +* [Payloads](lib/payloads/index.md) +* [Libraries](lib/index.md) * [Security](security/index.md) -* [SuperIO-specific documentation](superio/index.md) -* [Vendorcode-specific documentation](vendorcode/index.md) +* [SuperIO](superio/index.md) +* [Vendorcode](vendorcode/index.md) * [Utilities](util.md) * [Release notes for past releases](releases/index.md) * [Flashing firmware tutorial](flash_tutorial/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/37241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a021a09bdb88418ec85dbf433465f26445057d0 Gerrit-Change-Number: 37241 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 5

Change in em100[master]: WIP: Add more commands to trace mode
by Stefan Reinauer (Code Review) 06 Dec '19

06 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/36804 ) Change subject: WIP: Add more commands to trace mode ...................................................................... WIP: Add more commands to trace mode This is untested, unfinished work. DO NOT COMMIT Change-Id: I9c478475fe7553ab7e116890461ebd3f72cd9872 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M trace.c 1 file changed, 17 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/04/36804/1 diff --git a/trace.c b/trace.c index 50c2fc6..2fc3d44 100644 --- a/trace.c +++ b/trace.c @@ -115,14 +115,23 @@ struct spi_cmd_values spi_command_list[] = { /* name cmd, addr, pad */ - {"write status register", 0x01, 0, 0}, - {"page program", 0x02, 1, 0}, - {"read", 0x03, 1, 0}, - {"write disable", 0x04, 0, 0}, - {"read status register", 0x05, 0, 0}, - {"write enable", 0x06, 0, 0}, - {"fast read", 0x0b, 1, 1}, - {"EM100 specific", 0x11, 0, 0}, + {"No Operation", 0x00, 0, 0}, + {"Write Status Register", 0x01, 0, 0}, + {"Page Program", 0x02, 1, 0}, + {"Normal Read", 0x03, 1, 0}, + {"Write Disable", 0x04, 0, 0}, + {"Read Status Register", 0x05, 0, 0}, + {"Write Enable", 0x06, 0, 0}, + {"Fast Read", 0x0b, 1, 1}, + {"4-Byte Fast Read", 0x0c, 1, 1}, + {"DTR/DDR Fast Read", 0x0d, 1, 1}, + {"4-Byte DTR/DDR Fast Read", 0x0e, 1, 1}, + {"Write Status Register 3", 0x11, 0, 0}, + {"4-Byte Page Program", 0x12, 1, 0}, + {"4-Byte Read", 0x13, 1, 0}, + {"Autoboot Register Read", 0x14, 0, 0}, + {"Autoboot Register Write", 0x15, 0, 0}, + {"fast dual read", 0x3b, 1, 2}, {"chip erase", 0x60, 0, 0}, {"read JEDEC ID", 0x9f, 0, 0}, -- To view, visit https://review.coreboot.org/c/em100/+/36804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I9c478475fe7553ab7e116890461ebd3f72cd9872 Gerrit-Change-Number: 36804 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/lenovo/w520/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 06 Dec '19

06 Dec '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37294 ) Change subject: mb/lenovo/w520/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/w520/devicetree: Use subsystemid inheritance Change-Id: If7816992e717b4da585b16e5bbe67610c9af867d Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t520/variants/w520/devicetree.cb 1 file changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/37294/1 diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index 8716046..8b2cbe7 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -37,9 +37,13 @@ register "pci_mmio_size" = "2048" device domain 0 on + subsystemid 0x17aa 0x21cf inherit + device pci 00.0 on end # host bridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on end # vga controller + device pci 02.0 on + subsystemid 0x17aa 0x21d1 + end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -73,7 +77,9 @@ device pci 16.1 off end device pci 16.2 off end device pci 16.3 off end - device pci 19.0 on end # Intel Gigabit Ethernet + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x17aa 0x21ce + end device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 @@ -87,10 +93,10 @@ device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on #LPC bridge chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end -- To view, visit https://review.coreboot.org/c/coreboot/+/37294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7816992e717b4da585b16e5bbe67610c9af867d Gerrit-Change-Number: 37294 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/lenovo/t520/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 06 Dec '19

06 Dec '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37293 ) Change subject: mb/lenovo/t520/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/t520/devicetree: Use subsystemid inheritance Change-Id: Iffeb634c73f58aa1cddac5210d75fda75a3d5e92 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t520/variants/t520/devicetree.cb 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/37293/1 diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index 7893daf..0bfa18f 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -37,9 +37,13 @@ register "pci_mmio_size" = "2048" device domain 0 on + subsystemid 0x17aa 0x21cf inherit + device pci 00.0 on end # host bridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on end # vga controller + device pci 02.0 on + subsystemid 0x17aa 0x21d1 + end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -73,7 +77,9 @@ device pci 16.1 off end device pci 16.2 off end device pci 16.3 off end - device pci 19.0 on end # Intel Gigabit Ethernet + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x17aa 0x21ce + end device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 @@ -91,8 +97,7 @@ device pci 1f.0 on #LPC bridge chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end -- To view, visit https://review.coreboot.org/c/coreboot/+/37293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffeb634c73f58aa1cddac5210d75fda75a3d5e92 Gerrit-Change-Number: 37293 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: riscv: Implement ipi using clint for emulation to enable smp in qemu.
by Philipp Hug (Code Review) 06 Dec '19

06 Dec '19

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35246 ) Change subject: riscv: Implement ipi using clint for emulation to enable smp in qemu. ...................................................................... riscv: Implement ipi using clint for emulation to enable smp in qemu. testing=Set MAX_CPUS=2 and run qemu with -smp 2 Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae --- M src/mainboard/emulation/qemu-riscv/Makefile.inc M src/mainboard/emulation/qemu-riscv/clint.c M src/mainboard/emulation/spike-riscv/Makefile.inc M src/mainboard/emulation/spike-riscv/clint.c M src/soc/ucb/riscv/Makefile.inc D src/soc/ucb/riscv/ipi.c 6 files changed, 14 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35246/1 diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index eb99544..2ca75fd 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -19,6 +19,7 @@ romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c +romstage-y += clint.c ramstage-y += uart.c ramstage-y += rom_media.c diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c index 367d48d..4a00bc2 100644 --- a/src/mainboard/emulation/qemu-riscv/clint.c +++ b/src/mainboard/emulation/qemu-riscv/clint.c @@ -14,6 +14,7 @@ */ #include <mcall.h> +#include <device/mmio.h> #include <mainboard/addressmap.h> /* This function is used to initialize HLS()->time/HLS()->timecmp */ @@ -23,3 +24,8 @@ HLS()->time = (uint64_t *)(QEMU_VIRT_CLINT + 0xbff8); HLS()->timecmp = (uint64_t *)(QEMU_VIRT_CLINT + 0x4000 + 8 * hart_id); } + +void set_msip(int hartid, int val) +{ + write32((void *)(QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index 38977b6..bfeaf58 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -18,6 +18,7 @@ romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c +romstage-y += clint.c ramstage-y += uart.c ramstage-y += rom_media.c ramstage-y += clint.c diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c index 7ad3f5a..c39e058 100644 --- a/src/mainboard/emulation/spike-riscv/clint.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -14,6 +14,7 @@ */ #include <mcall.h> +#include <device/mmio.h> #define SPIKE_CLINT_BASE 0x02000000 @@ -24,3 +25,8 @@ HLS()->time = (uint64_t *)(SPIKE_CLINT_BASE + 0xbff8); HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id); } + +void set_msip(int hartid, int val) +{ + write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index ef03642..80899d57 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -1,11 +1,7 @@ ifeq ($(CONFIG_SOC_UCB_RISCV),y) -bootblock-y += ipi.c - romstage-y += cbmem.c -romstage-y += ipi.c ramstage-y += cbmem.c -ramstage-y += ipi.c endif diff --git a/src/soc/ucb/riscv/ipi.c b/src/soc/ucb/riscv/ipi.c deleted file mode 100644 index 80307a8..0000000 --- a/src/soc/ucb/riscv/ipi.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mcall.h> - -/* TODO: Please implement this function */ -void set_msip(int hartid, int val) -{ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/35246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae Gerrit-Change-Number: 35246 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019