coreboot-gerrit November 2019

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Change in coreboot[master]: mb/pcengines/apu2: move to C bootblock
by Michał Żygowski (Code Review) 11 Dec '19

11 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36915 ) Change subject: mb/pcengines/apu2: move to C bootblock ...................................................................... mb/pcengines/apu2: move to C bootblock Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 --- M src/mainboard/pcengines/apu2/Makefile.inc A src/mainboard/pcengines/apu2/bootblock.c M src/mainboard/pcengines/apu2/romstage.c 3 files changed, 37 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36915/1 diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 4ebfa9d..fe2036f1f 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -14,6 +14,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c romstage-y += gpio_ftns.c diff --git a/src/mainboard/pcengines/apu2/bootblock.c b/src/mainboard/pcengines/apu2/bootblock.c new file mode 100644 index 0000000..5dcf386 --- /dev/null +++ b/src/mainboard/pcengines/apu2/bootblock.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> + +#define SIO_PORT 0x2e +#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) +#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) + +void bootblock_mainboard_early_init(void) +{ + hudson_lpc_port80(); + hudson_clk_output_48Mhz(); + + /* COM2 on apu5 is reserved so only COM1 should be supported */ + if ((CONFIG_UART_FOR_CONSOLE == 1) && + !CONFIG(BOARD_PCENGINES_APU5)) + nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); + else if (CONFIG_UART_FOR_CONSOLE == 0) + nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 47a7d39..7e35239 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -15,73 +15,20 @@ #include <stdint.h> #include <device/pci_def.h> -#include <arch/io.h> #include <device/pci_ops.h> -#include <device/pnp.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> -#include <northbridge/amd/pi/agesawrapper.h> -#include <northbridge/amd/pi/agesawrapper_call.h> -#include <cpu/x86/bist.h> -#include <southbridge/amd/pi/hudson/hudson.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct5104d/nct5104d.h> -#include <Fch/Fch.h> #include "gpio_ftns.h" -#define SIO_PORT 0x2e -#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) -#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) - static void early_lpc_init(void); void board_BeforeAgesa(struct sysinfo *cb) { u32 val; - pci_devfn_t dev; - u32 data; - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - hudson_lpc_port80(); - - post_code(0x30); early_lpc_init(); - hudson_clk_output_48Mhz(); - post_code(0x31); - - dev = PCI_DEV(0, 0x14, 3); - data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ - pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); - - /* COM2 on apu5 is reserved so only COM1 should be supported */ - if ((CONFIG_UART_FOR_CONSOLE == 1) && - !CONFIG(BOARD_PCENGINES_APU5)) - nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); - else if (CONFIG_UART_FOR_CONSOLE == 0) - nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - /* Disable SVI2 controller to wait for command completion */ val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); if (val & (1 << 30)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 Gerrit-Change-Number: 36915 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: AMD AGESA, binaryPI: implement C bootblock
by Michał Żygowski (Code Review) 11 Dec '19

11 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36914 ) Change subject: AMD AGESA, binaryPI: implement C bootblock ...................................................................... AMD AGESA, binaryPI: implement C bootblock Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I29916a96f490ff717c69dc7cd565d74a83dbfb0d --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/00730F01/Makefile.inc M src/cpu/amd/pi/Kconfig M src/cpu/amd/pi/romstage.c M src/cpu/x86/lapic/Makefile.inc M src/drivers/amd/agesa/Makefile.inc A src/drivers/amd/agesa/bootblock.c M src/drivers/amd/agesa/cache_as_ram.S A src/drivers/amd/agesa/exit_car.S M src/drivers/amd/agesa/romstage.c M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/hudson.h 13 files changed, 157 insertions(+), 138 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/36914/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index d14eb40..65f2b44 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -30,6 +30,8 @@ select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select C_ENVIRONMENT_BOOTBLOCK + if CPU_AMD_AGESA @@ -49,6 +51,11 @@ hex default 0x10000 +config DCACHE_BSP_STACK_SIZE + hex + depends on C_ENVIRONMENT_BOOTBLOCK + default 0x4000 + config ENABLE_MRC_CACHE bool "Use cached memory configuration" default n diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index c4a92cf..aa0c05c 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -11,6 +11,8 @@ # GNU General Public License for more details. # +bootblock-y += fixme.c + romstage-y += fixme.c ramstage-y += fixme.c diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index b33302e..82dc9e8 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -29,6 +29,7 @@ select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select C_ENVIRONMENT_BOOTBLOCK if CPU_AMD_PI @@ -51,6 +52,11 @@ hex default 0x10000 +config DCACHE_BSP_STACK_SIZE + hex + depends on C_ENVIRONMENT_BOOTBLOCK + default 0x4000 + config S3_DATA_POS hex default 0xFFFF0000 diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c index cac5664..f060dc2 100644 --- a/src/cpu/amd/pi/romstage.c +++ b/src/cpu/amd/pi/romstage.c @@ -21,11 +21,6 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h> -void asmlinkage early_all_cores(void) -{ - amd_initmmio(); -} - void *asmlinkage romstage_main(unsigned long bist) { int s3resume = 0; diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..0d11478 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S +bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index 4d5bd3e..be048c4 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -21,8 +21,8 @@ ramstage-y += state_machine.c -cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S -postcar-y += cache_as_ram.S +bootblock-y += cache_as_ram.S +postcar-y += exit_car.S else @@ -30,6 +30,8 @@ endif +bootblock-y += bootblock.c + romstage-y += def_callouts.c romstage-y += eventlog.c diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c new file mode 100644 index 0000000..1a6bfdb --- /dev/null +++ b/src/drivers/amd/agesa/bootblock.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + amd_initmmio(); + enable_lapic(); + /* TSC cannot be relied upon. Override the TSC value passed in. */ + bootblock_main_with_basetime(timestamp_get()); +} \ No newline at end of file diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index dcb0c43..707615d 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -25,14 +25,14 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -.code32 -.globl _cache_as_ram_setup, _cache_as_ram_setup_end -.globl chipset_teardown_car +/* + * on entry: + * mm0: BIST (ignored) + * mm2_mm1: timestamp at bootblock_protected_mode_entry + */ -_cache_as_ram_setup: - - /* Preserve BIST. */ - movd %eax, %mm0 +.global bootblock_pre_c_entry +bootblock_pre_c_entry: post_code(0xa0) @@ -43,128 +43,35 @@ orl $(3 << 9), %eax movl %eax, %cr4 - post_code(0xa1) AMD_ENABLE_STACK - /* Align the stack. */ - and $0xFFFFFFF0, %esp - -#ifdef __x86_64__ - /* switch to 64 bit long mode */ - mov %esi, %ecx - add $0, %ecx # core number - xor %eax, %eax - lea (0x1000+0x23)(%ecx), %edi - mov %edi, (%ecx) - mov %eax, 4(%ecx) - - lea 0x1000(%ecx), %edi - movl $0x000000e3, 0x00(%edi) - movl %eax, 0x04(%edi) - movl $0x400000e3, 0x08(%edi) - movl %eax, 0x0c(%edi) - movl $0x800000e3, 0x10(%edi) - movl %eax, 0x14(%edi) - movl $0xc00000e3, 0x18(%edi) - movl %eax, 0x1c(%edi) - - # load ROM based identity mapped page tables - mov %ecx, %eax - mov %eax, %cr3 - - # enable PAE - mov %cr4, %eax - bts $5, %eax - mov %eax, %cr4 - - # enable long mode - mov $0xC0000080, %ecx + /* Setup bootblock stack on BSP */ + mov $0x1b, %ecx rdmsr - bts $8, %eax - wrmsr + test $256, %eax + jz stack_align - # enable paging - mov %cr0, %eax - bts $31, %eax - mov %eax, %cr0 + mov $_ecar_stack, %esp - # use call far to switch to 64-bit code segment - ljmp $0x18, $1f -1: +stack_align: -#endif + /* Align the stack and keep aligned for call to bootblock_c_entry() */ + and $0xfffffff0, %esp + sub $8, %esp - call early_all_cores + movd %mm2, %eax + pushl %eax /* tsc[63:32] */ + movd %mm1, %eax + pushl %eax /* tsc[31:0] */ - /* Must maintain 16-byte stack alignment here. */ - pushl $0x0 - pushl $0x0 - pushl $0x0 - movd %mm0, %eax /* bist */ - pushl %eax - call romstage_main +before_carstage: + post_code(0xa2) -#if CONFIG(POSTCAR_STAGE) + call bootblock_c_entry + /* Never reached */ -/* We do not return. Execution continues with run_postcar_phase() - * calling to chipset_teardown_car below. - */ - jmp postcar_entry_failure - -chipset_teardown_car: - -/* - * Retrieve return address from stack as it will get trashed below if - * execution is utilizing the cache-as-ram stack. - */ - pop %esp - -#else - - movl %eax, %esp - -/* Register %esp is new stacktop for remaining of romstage. */ - -#endif - - /* Disable cache */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - -/* Register %esp is preserved in AMD_DISABLE_STACK. */ - AMD_DISABLE_STACK - -#if CONFIG(POSTCAR_STAGE) - - jmp *%esp - -#else - - /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff, %eax - movl %eax, %cr0 - - call romstage_after_car - -#endif - - /* Should never see this postcode */ - post_code(0xaf) - -stop: +.halt_forever: + post_code(POST_DEAD_CODE) hlt - jmp stop - -/* These are here for linking purposes. */ -.weak early_all_cores, romstage_main -early_all_cores: -romstage_main: -postcar_entry_failure: - /* Should never see this postcode */ - post_code(0xae) - jmp stop - -_cache_as_ram_setup_end: + jmp .halt_forever diff --git a/src/drivers/amd/agesa/exit_car.S b/src/drivers/amd/agesa/exit_car.S new file mode 100644 index 0000000..f9d056e --- /dev/null +++ b/src/drivers/amd/agesa/exit_car.S @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <gcccar.inc> +#include <cpu/x86/cache.h> + +.code32 +.globl chipset_teardown_car + +chipset_teardown_car: + pop %esp + + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + AMD_DISABLE_STACK + + /* enable cache */ + movl %cr0, %eax + andl $(~(CR0_CD | CR0_NW)), %eax + movl %eax, %cr0 + + jmp *%esp diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 76a6ea4..bfdbda3 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -34,11 +34,6 @@ #error "LEGACY_WRAPPER code not supported" #endif -void asmlinkage early_all_cores(void) -{ - amd_initmmio(); -} - void __weak platform_once(struct sysinfo *cb) { board_BeforeAgesa(cb); @@ -52,7 +47,7 @@ agesa_set_interface(cb); } -void *asmlinkage romstage_main(unsigned long bist) +void asmlinkage car_stage_entry(void) { struct postcar_frame pcf; struct sysinfo romstage_state; @@ -75,9 +70,6 @@ printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1)); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - agesa_execute_state(cb, AMD_INIT_RESET); agesa_execute_state(cb, AMD_INIT_EARLY); @@ -109,6 +101,5 @@ recover_postcar_frame(&pcf, cb->s3resume); run_postcar_phase(&pcf); - /* We do not return. */ - return NULL; + /* We do not return. */ } diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 4b4b138..6199b24 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,6 +28,8 @@ # #***************************************************************************** +bootblock-y += bootblock.c +bootblock-y += early_setup.c bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index f12cec8..3899783 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -13,8 +13,12 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <stdint.h> +#include <arch/io.h> #include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <southbridge/amd/pi/hudson/hudson.h> /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -60,3 +64,40 @@ { hudson_enable_rom(); } + +void bootblock_soc_early_init(void) +{ + pci_devfn_t dev; + u32 data; + + bootblock_southbridge_init(); + hudson_lpc_decode(); + + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding for SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + + /* + * Enable FCH to decode TPM associated Memory and IO regions for vboot + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + */ + + data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); + data |= TPM_12_EN | TPM_LEGACY_EN; + pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); +} diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 9511a6a..08adb84 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -117,6 +117,10 @@ #define LPC_ALT_WIDEIO1_ENABLE BIT(2) #define LPC_ALT_WIDEIO0_ENABLE BIT(0) +#define LPC_TRUSTED_PLATFORM_MODULE 0x7c +#define TPM_12_EN BIT(0) +#define TPM_LEGACY_EN BIT(2) + #define LPC_WIDEIO2_GENERIC_PORT 0x90 #define SPI_CNTRL0 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/36914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29916a96f490ff717c69dc7cd565d74a83dbfb0d Gerrit-Change-Number: 36914 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

7 102

Change in coreboot[master]: device/software_i2c: Add function to recover bus
by Patrick Rudolph (Code Review) 11 Dec '19

11 Dec '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35725 ) Change subject: device/software_i2c: Add function to recover bus ...................................................................... device/software_i2c: Add function to recover bus As the software bus might be in unknown state, add a function to reset it to known (idle) state. Copied from linux kernel. Tested on Supermicro X11SSH-TF. Change-Id: I264471e872cb353b28a6b71cc64a11aec59e63f2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/software_i2c.c M src/include/device/i2c_simple.h 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35725/1 diff --git a/src/device/software_i2c.c b/src/device/software_i2c.c index 5dc9990..eecb670 100644 --- a/src/device/software_i2c.c +++ b/src/device/software_i2c.c @@ -343,3 +343,49 @@ "SDA %d, SCL %d\n", bus, bits, software_i2c[bus]->get_sda(bus), software_i2c[bus]->get_scl(bus)); } + +/* + * Try to recover the bus from unknown state. + * Useful if the power rail or reset line isn't under firmware control. + */ +#define RECOVERY_CLK_CNT 9 + +int i2c_recover_bus(unsigned bus) +{ + int i = 0, scl = 1; + + printk(BIOS_INFO, "software_i2c(%d): Trying i2c bus recovery\n", bus); + + /* + * If we can set SDA, we will always create a STOP to ensure additional + * pulses will do no harm. This is achieved by letting SDA follow SCL + * half a cycle later. Check the 'incomplete_write_byte' fault injector + * for details. + */ + software_i2c[bus]->set_scl(bus, 1); + wait(bus); + software_i2c[bus]->set_sda(bus, 1); + wait(bus); + + /* + * By this time SCL is high, as we need to give 9 falling-rising edges + */ + while (i++ < RECOVERY_CLK_CNT * 2) { + if (scl) { + /* SCL shouldn't be low here */ + if (!software_i2c[bus]->get_scl(bus)) { + printk(BIOS_ERR, "software_i2c(%d): SCL stuck low\n", bus); + return 1; + break; + } + } + + scl = !scl; + software_i2c[bus]->set_scl(bus, scl); + /* Creating STOP again, see above */ + wait(bus); + software_i2c[bus]->set_sda(bus, scl); + wait(bus); + } + return 0; +} diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h index e3cc892..7f508b2 100644 --- a/src/include/device/i2c_simple.h +++ b/src/include/device/i2c_simple.h @@ -45,6 +45,8 @@ int i2c_write_field(unsigned int bus, uint8_t slave, uint8_t reg, uint8_t data, uint8_t mask, uint8_t shift); +int i2c_recover_bus(unsigned int bus); + /* * software_i2c is supposed to be a debug feature. It's usually not compiled in, * but when it is it can be dynamically enabled at runtime for certain busses. -- To view, visit https://review.coreboot.org/c/coreboot/+/35725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I264471e872cb353b28a6b71cc64a11aec59e63f2 Gerrit-Change-Number: 35725 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 14

Change in coreboot[master]: mb/amd/padmelon: Use Prairie Falcon configuration
by Richard Spiegel (Code Review) 11 Dec '19

11 Dec '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36824 ) Change subject: mb/amd/padmelon: Use Prairie Falcon configuration ...................................................................... mb/amd/padmelon: Use Prairie Falcon configuration While Merlin Falcon binaries are not available, make it explicit that it's compiling for Prairie Falcon (it was being surreptitious about it). Board Padmelon accepts 3 different SOC, just changing some resistors (soldered or not): Brown Falcon, Prairie Falcon and Merlin Falcon. Code for Brown Falcon is not currently available. BUG=None TEST=Build with prairie falcon. Change-Id: I1663e4403a32a7d626dd2fa06763f18f4230457e Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/amd/padmelon/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/36824/1 diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index 3d8efb1..5179ca7 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -17,7 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select SOC_AMD_MERLINFALCON + select SOC_AMD_PRAIRIEFALCON select BOARD_ROMSIZE_KB_8192 select DRIVERS_I2C_GENERIC select DRIVERS_PS2_KEYBOARD -- To view, visit https://review.coreboot.org/c/coreboot/+/36824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1663e4403a32a7d626dd2fa06763f18f4230457e Gerrit-Change-Number: 36824 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: soc/amd/stoneyridge|mbs: Deprecate SOC_AMD_NAME_PKG and others
by Marshall Dawson (Code Review) 11 Dec '19

11 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37225 ) Change subject: soc/amd/stoneyridge|mbs: Deprecate SOC_AMD_NAME_PKG and others ...................................................................... soc/amd/stoneyridge|mbs: Deprecate SOC_AMD_NAME_PKG and others Add package and APU selections to mainboards and remove symbols no longer used in soc//stoneyridge. Change-Id: I60214b6557bef50358f9ec8f9fcdb7265e04663b Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/gardenia/Kconfig M src/mainboard/amd/padmelon/Kconfig M src/mainboard/google/kahlee/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/amd/pi/Kconfig 7 files changed, 14 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/37225/1 diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index 2d3f264..e97a3ba 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -18,7 +18,8 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_AMD_STONEYRIDGE - select SOC_AMD_STONEYRIDGE_FP4 + select AMD_APU_STONEYRIDGE + select AMD_APU_PKG_FP4 select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index f5d4b6d..1be3a62 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -18,7 +18,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SOC_AMD_STONEYRIDGE - select SOC_AMD_MERLINFALCON + select AMD_APU_MERLINFALCON + select AMD_APU_PKG_FP4 select BOARD_ROMSIZE_KB_8192 select DRIVERS_I2C_GENERIC select DRIVERS_PS2_KEYBOARD diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 20b5273..7d98d89 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -16,7 +16,8 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE bool select SOC_AMD_STONEYRIDGE - select SOC_AMD_STONEYRIDGE_FT4 + select AMD_APU_STONEYRIDGE + select AMD_APU_PKG_FT4 select ALWAYS_LOAD_OPROM select ALWAYS_RUN_OPROM select BOARD_ROMSIZE_KB_16384 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 09ff596..bb21516 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -20,34 +20,6 @@ if SOC_AMD_STONEYRIDGE -config SOC_AMD_STONEYRIDGE_FP4 - bool - select AMD_APU_STONEYRIDGE - select AMD_APU_PKG_FP4 - help - AMD Stoney Ridge FP4 support - -config SOC_AMD_STONEYRIDGE_FT4 - bool - select AMD_APU_STONEYRIDGE - select AMD_APU_PKG_FT4 - help - AMD Stoney Ridge FT4 support - -config SOC_AMD_MERLINFALCON - bool - select AMD_APU_MERLINFALCON - select AMD_APU_PKG_FP4 - help - AMD Merlin Falcon FP4 support - -config SOC_AMD_PRAIRIEFALCON - bool - select AMD_APU_PRAIRIEFALCON - select AMD_APU_PKG_FP4 - help - AMD Prairie Falcon FP4 support - config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index b7498fc..6489944 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -27,7 +27,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc @@ -344,4 +344,4 @@ endif # ifneq ($(FIRMWARE_LOCATE),) -endif # ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +endif # ($(CONFIG_SOC_AMD_STONEYRIDGE),y) diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index fef7dff..a1f1da0 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -28,7 +28,7 @@ # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) # AGESA V5 Files AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH)) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 5e7d1f7..baf95ad 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -26,14 +26,14 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE || SOC_AMD_MERLINFALCON +if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE config AGESA_BINARY_PI_VENDORCODE_PATH string "AGESA PI directory path" default "src/vendorcode/amd/pi/00630F01" if CPU_AMD_PI_00630F01 default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01 - default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_MERLINFALCON - default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE + default "src/vendorcode/amd/pi/00670F00" if AMD_APU_MERLINFALCON + default "src/vendorcode/amd/pi/00670F00" if AMD_APU_STONEYRIDGE || AMD_APU_PRAIRIEFALCON default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01 help Specify where to find the AGESA header files @@ -43,8 +43,8 @@ string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_PRAIRIEFALCON + default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_MERLINFALCON + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_PRAIRIEFALCON default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_STONEYRIDGE default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help -- To view, visit https://review.coreboot.org/c/coreboot/+/37225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60214b6557bef50358f9ec8f9fcdb7265e04663b Gerrit-Change-Number: 37225 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: soc/amd/stoneyridge|mbs: Define SOC_AMD_STONEYRIDGE symbol
by Marshall Dawson (Code Review) 11 Dec '19

11 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37224 ) Change subject: soc/amd/stoneyridge|mbs: Define SOC_AMD_STONEYRIDGE symbol ...................................................................... soc/amd/stoneyridge|mbs: Define SOC_AMD_STONEYRIDGE symbol Make a new Kconfig symbol for using soc//stoneyridge. This code also supports Prairie Falcon is backward-compatible with Carrizo and Merlin Falcon. Although Bettong uses Carrizo, it does not currently rely on stoneyridge source, so it is unaffected by this change. Change-Id: I786ca54b0444cbcf36dc428a193006797b01fc09 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/gardenia/Kconfig M src/mainboard/amd/padmelon/Kconfig M src/mainboard/google/kahlee/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/vendorcode/amd/pi/Kconfig 5 files changed, 17 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/37224/1 diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index 02e3e95..2d3f264 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select SOC_AMD_STONEYRIDGE select SOC_AMD_STONEYRIDGE_FP4 select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index e4dd90c..f5d4b6d 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select SOC_AMD_STONEYRIDGE select SOC_AMD_MERLINFALCON select BOARD_ROMSIZE_KB_8192 select DRIVERS_I2C_GENERIC diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 86325532..20b5273 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE bool + select SOC_AMD_STONEYRIDGE select SOC_AMD_STONEYRIDGE_FT4 select ALWAYS_LOAD_OPROM select ALWAYS_RUN_OPROM diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index e2a6896..09ff596 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -13,6 +13,13 @@ ## GNU General Public License for more details. ## +config SOC_AMD_STONEYRIDGE + bool + help + AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh. + +if SOC_AMD_STONEYRIDGE + config SOC_AMD_STONEYRIDGE_FP4 bool select AMD_APU_STONEYRIDGE @@ -41,8 +48,6 @@ help AMD Prairie Falcon FP4 support -if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON - config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 @@ -441,4 +446,4 @@ return to S0. Otherwise the system will remain in S5 once power is restored. -endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON +endif # SOC_AMD_STONEYRIDGE diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index e6f9fee..5e7d1f7 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -26,15 +26,14 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON +if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE || SOC_AMD_MERLINFALCON config AGESA_BINARY_PI_VENDORCODE_PATH string "AGESA PI directory path" default "src/vendorcode/amd/pi/00630F01" if CPU_AMD_PI_00630F01 default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01 default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_MERLINFALCON - default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FP4 - default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FT4 + default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01 help Specify where to find the AGESA header files @@ -46,15 +45,14 @@ default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_PRAIRIEFALCON - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_STONEYRIDGE default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help Specify the binary file to use for AMD platform initialization. config AGESA_BINARY_PI_AS_STAGE bool "AGESA Binary PI is added as stage to CBFS." - depends on SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_STONEYRIDGE_FP4 + depends on SOC_AMD_STONEYRIDGE help AGESA will be added as a stage utilizing --xip cbfstool options as needed relocating the image to the proper location in memory-mapped @@ -72,7 +70,7 @@ config AGESA_PRE_MEMORY_BINARY_PI_FILE string depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE help Specify the binary file to use for pre-memory AMD platform initialization. @@ -80,7 +78,7 @@ config AGESA_POST_MEMORY_BINARY_PI_FILE string depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE help Specify the binary file to use for post-memory AMD platform initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/37224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I786ca54b0444cbcf36dc428a193006797b01fc09 Gerrit-Change-Number: 37224 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/amd/stoneyridge|mb: Add Kconfig symbol for Prairie Falcon
by Marshall Dawson (Code Review) 11 Dec '19

11 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37223 ) Change subject: soc/amd/stoneyridge|mb: Add Kconfig symbol for Prairie Falcon ...................................................................... soc/amd/stoneyridge|mb: Add Kconfig symbol for Prairie Falcon The stoneyridge code inferred that if Merlin Falcon was built but no Merlin Falcon binaries were present, the intent must be Prairie Falcon. The two falcons are Embedded variants, and Prairie Falcon falls within Family 15h Models 70h-7Fh. Add a Prairie Falcon symbol that can be used explicitely. Drop HAVE_MERLINFALCON_BINARIES. Change-Id: I0d3a1bc302760c18c8fe3d57c955e2bb3bd8153a Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/padmelon/devicetree.cb M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/chip.h M src/vendorcode/amd/pi/Kconfig 5 files changed, 25 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/37223/1 diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb index 9baee2f..fa83d10 100644 --- a/src/mainboard/amd/padmelon/devicetree.cb +++ b/src/mainboard/amd/padmelon/devicetree.cb @@ -16,7 +16,7 @@ register "spd_addr_lookup" = " { -#if CONFIG(HAVE_MERLINFALCON_BINARIES) +#if CONFIG(AMD_APU_MERLINFALCON) { {0xA0, 0x00}, {0xA4, 0x00} }, // socket 0 - Channel 0 & 1, slot 0 #else { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 2fe3ef7..e2a6896 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -34,15 +34,14 @@ help AMD Merlin Falcon FP4 support -config HAVE_MERLINFALCON_BINARIES - depends on AMD_APU_MERLINFALCON - bool "Merlinfalcon binaries are present" - default n +config SOC_AMD_PRAIRIEFALCON + bool + select AMD_APU_PRAIRIEFALCON + select AMD_APU_PKG_FP4 help - This config option will be removed once the binaries are merged - to the blobs repo. See 33615. + AMD Prairie Falcon FP4 support -if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON +if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON config CPU_SPECIFIC_OPTIONS def_bool y @@ -89,10 +88,15 @@ help AMD Stoney Ridge APU +config AMD_APU_PRAIRIEFALCON + bool + help + AMD Embedded Prairie Falcon APU + config AMD_APU_MERLINFALCON bool help - AMD Merlin Falcon APU + AMD Embedded Merlin Falcon APU config AMD_APU_PKG_FP4 bool @@ -178,7 +182,8 @@ string default "" if !USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/CarrizoGenericVbios.bin" if AMD_APU_MERLINFALCON - default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" + default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_PRAIRIEFALCON + default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_STONEYRIDGE config S3_VGA_ROM_RUN bool @@ -229,7 +234,8 @@ string "AMD public Key" default "" if !USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/PSP/CZ/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON - default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" + default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_PRAIRIEFALCON + default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_STONEYRIDGE config STONEYRIDGE_SATA_MODE int "SATA Mode" @@ -435,4 +441,4 @@ return to S0. Otherwise the system will remain in S5 once power is restored. -endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON +endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index d2d64c8..b7498fc 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -145,8 +145,12 @@ ifeq ($(CONFIG_AMD_APU_MERLINFALCON),y) FIRMWARE_TYPE=CZ else +ifeq ($(CONFIG_AMD_APU_PRAIRIEFALCON),y) +FIRMWARE_TYPE=ST +else $(error soc/amd/stoneyridge: Unusable FIRMWARE_TYPE) +endif # CONFIG_AMD_APU_PRAIRIEFALCON endif # CONFIG_AMD_APU_MERLINFALCON endif # CONFIG_AMD_APU_STONEYRIDGE diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 00b675c..fedb3e9 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -23,12 +23,11 @@ #include <soc/i2c.h> #include <arch/acpi_device.h> -/* Merlin Falcon supports 2 channels, Prairie Falcon only 1 (channel B) */ #define MAX_NODES 1 -#if CONFIG(SOC_AMD_MERLINFALCON) && CONFIG(HAVE_MERLINFALCON_BINARIES) +#if CONFIG(AMD_APU_MERLINFALCON) #define MAX_DRAM_CH 2 #define MAX_DIMMS_PER_CH 2 -#else +#else /* AMD_APU_STONEYRIDGE || AMD_APU_PRAIRIEFALCON */ #define MAX_DRAM_CH 1 #define MAX_DIMMS_PER_CH 2 #endif diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 9f5d94d..e6f9fee 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -44,8 +44,8 @@ string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_PRAIRIEFALCON default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 -- To view, visit https://review.coreboot.org/c/coreboot/+/37223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d3a1bc302760c18c8fe3d57c955e2bb3bd8153a Gerrit-Change-Number: 37223 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: vc/amd/pi: Allow 00670F00 to build with no binaryPI
by Marshall Dawson (Code Review) 11 Dec '19

11 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37228 ) Change subject: vc/amd/pi: Allow 00670F00 to build with no binaryPI ...................................................................... vc/amd/pi: Allow 00670F00 to build with no binaryPI Make the default binaryPI image strings for all stoneyridge-based APUs depend on USE_AMD_BLOBS. Ensure the build completes without names, and without images. Change-Id: I74a38efa2a4ad2f9f12a1f8e7fb8694d0ab9dd1e Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/amd/pi/Kconfig 2 files changed, 28 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37228/1 diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index fef7dff..796d130 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -116,10 +116,22 @@ ####################################################################### +warn_no_agesa: + printf "\n\t** WARNING **\n" + printf "coreboot has been built with no AGESA support. Successfully " + printf "booting is unlikely.\n\n" + +PHONY+=warn_no_amdfw + ifeq ($(CONFIG_AGESA_SPLIT_MEMORY_FILES), y) # convert input elf to rmodule AGESA_POST_MEM_INPUT_ELF = $(call strip_quotes,$(CONFIG_AGESA_POST_MEMORY_BINARY_PI_FILE)) + +# If no post-mem file then also skip pre-mem file +ifeq ($(AGESA_POST_MEM_INPUT_ELF,)) +files_added:: warn_no_agesa +else AGESA_POST_MEM_ELF = $(objcbfs)/$(patsubst %.elf,%.debug,$(notdir $(AGESA_POST_MEM_INPUT_ELF))) AGESA_POST_MEM_ELF_RMOD = $(AGESA_POST_MEM_ELF).rmod @@ -140,10 +152,18 @@ $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-file := $(AGESA_POST_MEM_ELF_RMOD) $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-type := stage $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-compression := $(CBFS_COMPRESS_FLAG) + +endif # AGESA_POST_MEM_INPUT_ELF == "" + +else # CONFIG_AGESA_SPLIT_MEMORY_FILES + +AGESA_BINARYPI_INPUT_FILE = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_FILE)) +ifeq ($(AGESA_BINARYPI_INPUT_FILE),) +files_added:: warn_no_agesa else cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME) -$(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE) +$(CONFIG_AGESA_CBFS_NAME)-file := $(AGESA_BINARYPI_INPUT_FILE) ifeq ($(CONFIG_AGESA_BINARY_PI_AS_STAGE),y) $(CONFIG_AGESA_CBFS_NAME)-type := stage @@ -156,6 +176,7 @@ $(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) endif # CONFIG_AGESA_BINARY_PI_AS_STAGE +endif # AGESA_BINARYPI_INPUT_FILE == "" endif # CONFIG_AGESA_SPLIT_MEMORY_FILES endif diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 0605563..73fe4f2 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -44,10 +44,10 @@ string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/blobs/pi/amd/merlinfalcon/$(CONFIG_AMD_SOC_PACKAGE)/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/merlinfalcon/$(CONFIG_AMD_SOC_PACKAGE)/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES && USE_AMD_BLOBS + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES && USE_AMD_BLOBS + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 && USE_AMD_BLOBS + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help Specify the binary file to use for AMD platform initialization. @@ -72,7 +72,7 @@ config AGESA_PRE_MEMORY_BINARY_PI_FILE string depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS help Specify the binary file to use for pre-memory AMD platform initialization. @@ -80,7 +80,7 @@ config AGESA_POST_MEMORY_BINARY_PI_FILE string depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS help Specify the binary file to use for post-memory AMD platform initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/37228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74a38efa2a4ad2f9f12a1f8e7fb8694d0ab9dd1e Gerrit-Change-Number: 37228 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: mb/google/drallion/variants/drallion: Update thermal configuration fo...
by John Su (Code Review) 11 Dec '19

11 Dec '19

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36860 ) Change subject: mb/google/drallion/variants/drallion: Update thermal configuration for DPTF ...................................................................... mb/google/drallion/variants/drallion: Update thermal configuration for DPTF Follow thermal table(b/144464314#1) for first tunning. BUG=b:144464314 TEST=Built and tested on drallion Change-Id: I4546622cdc6efb2bf2eb973cfc5c6f22c40cc6ef Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl 1 file changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/36860/1 diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl index 73e1dec..3ff23b7 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl @@ -13,42 +13,42 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 98 -#define DPTF_CPU_CRITICAL 108 +#define DPTF_CPU_PASSIVE 99 +#define DPTF_CPU_CRITICAL 127 /* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "Skin" -#define DPTF_TSR0_PASSIVE 55 -#define DPTF_TSR0_CRITICAL 100 +#define DPTF_TSR0_PASSIVE 90 +#define DPTF_TSR0_CRITICAL 127 /* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "DDR" -#define DPTF_TSR1_PASSIVE 53 -#define DPTF_TSR1_CRITICAL 100 +#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_CRITICAL 127 /* M.2 Sensor for Ambient temperature monitor */ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 38 -#define DPTF_TSR2_CRITICAL 93 +#define DPTF_TSR2_PASSIVE 50 +#define DPTF_TSR2_CRITICAL 127 #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 250, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 400, 40, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 250, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 300, 50, 2, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 250, 10, 2, 0, 0, 0 }, /* CPU Throttle Effect on Ambient (TSR2) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 250, 10, 1, 0, 0, 0 }, }) Name (MPPC, Package () @@ -56,15 +56,15 @@ 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 3000, /* PowerLimitMinimum */ - 21000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 28000, /* TimeWindowMaximum */ + 4000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 10000, /* TimeWindowMinimum */ + 10000, /* TimeWindowMaximum */ 100 /* StepSize */ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 15000, /* PowerLimitMinimum */ + 4000, /* PowerLimitMinimum */ 51000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 28000, /* TimeWindowMaximum */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4546622cdc6efb2bf2eb973cfc5c6f22c40cc6ef Gerrit-Change-Number: 36860 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: src/arch/x86/car.ld: add AP entry address in CAR space
by Michał Żygowski (Code Review) 10 Dec '19

10 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37167 ) Change subject: src/arch/x86/car.ld: add AP entry address in CAR space ...................................................................... src/arch/x86/car.ld: add AP entry address in CAR space This is a placeholder for AP entry address for AMD platforms that support C environment bootblock. This shortcut address allows APs to jump to the AGESA entries directly after CAR setup and avoid looking for a scratch register for each family to store the AP entry address. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I177cd6f84c3f36776ec7bc8eeacb5b2a1d9142d2 --- M src/arch/x86/car.ld M src/arch/x86/include/arch/symbols.h 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37167/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 3680250..de760f8 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -68,6 +68,11 @@ . += 80; _ecar_ehci_dbg_info = .; + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); + _car_amd_ap_entry = .; + . += 4; + _ecar_amd_ap_entry = .; + /* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram * cbmem console. This is useful for clearing this area on a per-stage diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h index efe10fe..9ab0dba 100644 --- a/src/arch/x86/include/arch/symbols.h +++ b/src/arch/x86/include/arch/symbols.h @@ -38,4 +38,6 @@ #define _car_ehci_dbg_info_size \ (_ecar_ehci_dbg_info - _car_ehci_dbg_info) +extern unsigned long _car_amd_ap_entry; + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I177cd6f84c3f36776ec7bc8eeacb5b2a1d9142d2 Gerrit-Change-Number: 37167 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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