coreboot-gerrit November 2019

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Change in coreboot[master]: endian: Replace explicit byte swapping with compiler builtin
by Julius Werner (Code Review) 06 Dec '19

06 Dec '19

Hello Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37343 to review the following change. Change subject: endian: Replace explicit byte swapping with compiler builtin ...................................................................... endian: Replace explicit byte swapping with compiler builtin gcc seems to have some stupid problem with deciding when to inline byte swapping functions (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92716). Using the compiler builtin instead seems to solve the problem. (This doesn't yet solve the issue for the read_be32()-family of functions, which we should maybe just get rid of at some point?) Change-Id: Ia2a6d8ea98987266ccc32ffaa0a7f78965fca1cd Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/include/endian.h D payloads/libpayload/include/swab.h M src/include/endian.h D src/include/swab.h M src/vendorcode/eltan/security/mboot/mboot.c M src/vendorcode/eltan/security/mboot/mboot.h 6 files changed, 20 insertions(+), 130 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/37343/1 diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index b387e66..7f8b93a 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -34,23 +34,6 @@ #include <arch/types.h> #include <libpayload-config.h> -static inline uint16_t swap_bytes16(uint16_t in) -{ - return ((in & 0xFF) << 8) | ((in & 0xFF00) >> 8); -} - -static inline uint32_t swap_bytes32(uint32_t in) -{ - return ((in & 0xFF) << 24) | ((in & 0xFF00) << 8) | - ((in & 0xFF0000) >> 8) | ((in & 0xFF000000) >> 24); -} - -static inline uint64_t swap_bytes64(uint64_t in) -{ - return ((uint64_t)swap_bytes32((uint32_t)in) << 32) | - ((uint64_t)swap_bytes32((uint32_t)(in >> 32))); -} - /* Endian functions from glibc 2.9 / BSD "endian.h" */ #if CONFIG(LP_BIG_ENDIAN) @@ -59,15 +42,15 @@ #define htobe32(in) (in) #define htobe64(in) (in) -#define htole16(in) swap_bytes16(in) -#define htole32(in) swap_bytes32(in) -#define htole64(in) swap_bytes64(in) +#define htole16(in) __builtin_bswap16(in) +#define htole32(in) __builtin_bswap32(in) +#define htole64(in) __builtin_bswap64(in) #elif CONFIG(LP_LITTLE_ENDIAN) -#define htobe16(in) swap_bytes16(in) -#define htobe32(in) swap_bytes32(in) -#define htobe64(in) swap_bytes64(in) +#define htobe16(in) __builtin_bswap16(in) +#define htobe32(in) __builtin_bswap32(in) +#define htobe64(in) __builtin_bswap64(in) #define htole16(in) (in) #define htole32(in) (in) diff --git a/payloads/libpayload/include/swab.h b/payloads/libpayload/include/swab.h deleted file mode 100644 index 2198077..0000000 --- a/payloads/libpayload/include/swab.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef _SWAB_H -#define _SWAB_H - -/* - * linux/byteorder/swab.h - * Byte-swapping, independently from CPU endianness - * swabXX[ps]?(foo) - * - * Francois-Rene Rideau <fare(a)tunes.org> 19971205 - * separated swab functions from cpu_to_XX, - * to clean up support for bizarre-endian architectures. - * - * See asm-i386/byteorder.h and suches for examples of how to provide - * architecture-dependent optimized versions - * - */ - -/* casts are necessary for constants, because we never know for sure - * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. - */ -#define swab16(x) \ - ((unsigned short)( \ - (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \ - (((unsigned short)(x) & (unsigned short)0xff00U) >> 8))) - -#define swab32(x) \ - ((unsigned int)( \ - (((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \ - (((unsigned int)(x) & (unsigned int)0x0000ff00UL) << 8) | \ - (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \ - (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24))) - -#define swab64(x) \ - ((uint64_t)( \ - (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ - (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ - (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ - (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ - (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ - (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ - (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ - (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) - -#endif /* _SWAB_H */ diff --git a/src/include/endian.h b/src/include/endian.h index 8dc1854..d4b1707 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -17,7 +17,6 @@ #include <arch/byteorder.h> #include <stdint.h> -#include <swab.h> #if defined(__LITTLE_ENDIAN) #define cpu_to_le64(x) ((uint64_t)(x)) @@ -26,19 +25,19 @@ #define le32_to_cpu(x) ((uint32_t)(x)) #define cpu_to_le16(x) ((uint16_t)(x)) #define le16_to_cpu(x) ((uint16_t)(x)) - #define cpu_to_be64(x) swab64(x) - #define be64_to_cpu(x) swab64(x) - #define cpu_to_be32(x) swab32(x) - #define be32_to_cpu(x) swab32(x) - #define cpu_to_be16(x) swab16(x) - #define be16_to_cpu(x) swab16(x) + #define cpu_to_be64(x) __builtin_bswap64(x) + #define be64_to_cpu(x) __builtin_bswap64(x) + #define cpu_to_be32(x) __builtin_bswap32(x) + #define be32_to_cpu(x) __builtin_bswap32(x) + #define cpu_to_be16(x) __builtin_bswap16(x) + #define be16_to_cpu(x) __builtin_bswap16(x) #elif defined(__BIG_ENDIAN) - #define cpu_to_le64(x) swab64(x) - #define le64_to_cpu(x) swab64(x) - #define cpu_to_le32(x) swab32(x) - #define le32_to_cpu(x) swab32(x) - #define cpu_to_le16(x) swab16(x) - #define le16_to_cpu(x) swab16(x) + #define cpu_to_le64(x) __builtin_bswap64(x) + #define le64_to_cpu(x) __builtin_bswap64(x) + #define cpu_to_le32(x) __builtin_bswap32(x) + #define le32_to_cpu(x) __builtin_bswap32(x) + #define cpu_to_le16(x) __builtin_bswap16(x) + #define le16_to_cpu(x) __builtin_bswap16(x) #define cpu_to_be64(x) ((uint64_t)(x)) #define be64_to_cpu(x) ((uint64_t)(x)) #define cpu_to_be32(x) ((uint32_t)(x)) diff --git a/src/include/swab.h b/src/include/swab.h deleted file mode 100644 index 956cfa5..0000000 --- a/src/include/swab.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * linux/byteorder/swab.h - * Byte-swapping, independently from CPU endianness - * swabXX[ps]?(foo) - * - * Francois-Rene Rideau <fare(a)tunes.org> 19971205 - * separated swab functions from cpu_to_XX, - * to clean up support for bizarre-endian architectures. - * - * See asm-i386/byteorder.h and such for examples of how to provide - * architecture-dependent optimized versions - * - */ - -/* casts are necessary for constants, because we never know how for sure - * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. - */ - -#ifndef _SWAB_H -#define _SWAB_H - -#include <stdint.h> - -#define swab16(x) \ - ((unsigned short)( \ - (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \ - (((unsigned short)(x) & (unsigned short)0xff00U) >> 8))) - -#define swab32(x) \ - ((unsigned int)( \ - (((unsigned int)(x) & 0x000000ffUL) << 24) | \ - (((unsigned int)(x) & 0x0000ff00UL) << 8) | \ - (((unsigned int)(x) & 0x00ff0000UL) >> 8) | \ - (((unsigned int)(x) & 0xff000000UL) >> 24))) - -#define swab64(x) \ - ((uint64_t)( \ - (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ - (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ - (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ - (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ - (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ - (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ - (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ - (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) - -#endif /* _SWAB_H */ diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index c5523a5..f47d74b 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -100,8 +100,8 @@ Pcrs->count = TpmCap.data.assignedPCR.count; printk(BIOS_DEBUG, "Pcrs->count = %d\n", Pcrs->count); for (index = 0; index < Pcrs->count; index++) { - Pcrs->pcrSelections[index].hash = - swab16(TpmCap.data.assignedPCR.pcrSelections[index].hash); + Pcrs->pcrSelections[index].hash = __builtin_bswap16( + TpmCap.data.assignedPCR.pcrSelections[index].hash); printk(BIOS_DEBUG, "Pcrs->pcrSelections[%d].hash = 0x%x\n", index, Pcrs->pcrSelections[index].hash); Pcrs->pcrSelections[index].sizeofSelect = diff --git a/src/vendorcode/eltan/security/mboot/mboot.h b/src/vendorcode/eltan/security/mboot/mboot.h index 79f2308..3b08924 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.h +++ b/src/vendorcode/eltan/security/mboot/mboot.h @@ -27,7 +27,6 @@ #include <boot/coreboot_tables.h> #include <security/tpm/tss/tcg-2.0/tss_structures.h> #include <security/tpm/tss.h> -#include <swab.h> /* TPM2 interface */ #define EFI_TPM2_ACPI_TABLE_START_METHOD_TIS 6 -- To view, visit https://review.coreboot.org/c/coreboot/+/37343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2a6d8ea98987266ccc32ffaa0a7f78965fca1cd Gerrit-Change-Number: 37343 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: vboot: update VbExNvStorageWrite function
by Joel Kitching (Code Review) 06 Dec '19

06 Dec '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37315 ) Change subject: vboot: update VbExNvStorageWrite function ...................................................................... vboot: update VbExNvStorageWrite function Going forwards, vb2ex_commit_data will be used to flush both nvdata and secdata. BUG=b:124141368, chromium:1006689 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ia2612da0df101cd3c46151dbce728633a39fada1 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/ec_sync.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/37315/1 diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index c2a6b25..8a3ba71 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -399,9 +399,9 @@ /* * Write opaque data into NV storage region. */ -vb2_error_t VbExNvStorageWrite(const uint8_t *buf) +vb2_error_t vb2ex_commit_data(struct vb2_context *ctx) { - save_vbnv(buf); + save_vbnv(ctx->nvdata); return VB2_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2612da0df101cd3c46151dbce728633a39fada1 Gerrit-Change-Number: 37315 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: src/mb/intel/coffeelake_rvp: Move the base of DT to baseboard
by Gaggery Tsai (Code Review) 05 Dec '19

05 Dec '19

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36794 ) Change subject: src/mb/intel/coffeelake_rvp: Move the base of DT to baseboard ...................................................................... src/mb/intel/coffeelake_rvp: Move the base of DT to baseboard This patch moves the base of devicetree settings into baseboard and creates overridetree.cb for each variant. TEST=build an image for each variant Change-Id: I067bdb3fcf1218b93e52801f6db093e24d7d2b62 Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig R src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb R src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb R src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb D src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb D src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb A src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb 9 files changed, 268 insertions(+), 488 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/36794/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index e7c5d36..299d072 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -63,7 +63,11 @@ config DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config FMDFILE string diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb similarity index 68% rename from src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb rename to src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 429d5da..aa245cf 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -7,20 +7,9 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" - register "HeciEnabled" = "1" - # Enable eDP device - register "DdiPortEdp" = "1" - # Enable HPD for DDI ports B/C/D/F - register "DdiPortBHpd" = "1" - register "DdiPortCHpd" = "1" - register "DdiPortDHpd" = "1" - register "DdiPortFHpd" = "1" - # Enable DDC for DDI ports B/C/D/F - register "DdiPortBDdc" = "1" - register "DdiPortCDdc" = "1" - register "DdiPortDDdc" = "1" - register "DdiPortFDdc" = "1" + # HECI + register "HeciEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" @@ -40,16 +29,6 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsEnable[3]" = "1" - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "1" - register "SataPortsEnable[7]" = "1" - register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" @@ -87,8 +66,8 @@ # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" + # Disable S0ix + register "s0ix_enable" = "0" device domain 0 on device pci 00.0 on end # Host Bridge @@ -99,41 +78,37 @@ device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 + device pci 17.0 off end # SATA + device pci 19.0 off end # I2C #4 (Not available on PCH-H) + device pci 19.1 off end # I2C #5 (Not available on PCH-H) device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC + device pci 1a.0 off end # eMMC device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 on end # PCI Express Port 8 device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.3 on end # PCI Express Port 12 + device pci 1d.4 on end # PCI Express Port 13 + device pci 1d.5 on end # PCI Express Port 14 + device pci 1d.6 on end # PCI Express Port 15 + device pci 1d.7 on end # PCI Express Port 16 device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 + device pci 1e.1 on end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 on @@ -146,6 +121,6 @@ device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + device pci 1f.6 off end # GbE end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb similarity index 62% rename from src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb rename to src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb index 9648ac3..e21a782 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb @@ -5,9 +5,7 @@ end # FSP configuration - register "SaGv" = "SaGv_Enabled" register "RMT" = "1" - register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)" register "usb2_ports[1]" = "USB2_PORT_MID(OC6)" @@ -48,22 +46,6 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" register "PcieRpEnable[16]" = "1" register "PcieRpEnable[17]" = "1" register "PcieRpEnable[18]" = "1" @@ -91,42 +73,14 @@ register "PcieClkSrcClkReq[8]" = "8" register "PcieClkSrcClkReq[9]" = "9" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # HECI - register "HeciEnabled" = "1" - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 - device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 @@ -134,20 +88,9 @@ device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb similarity index 63% rename from src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb rename to src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index 126cab0..618ac3b 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -5,9 +5,7 @@ end # FSP configuration - register "SaGv" = "SaGv_Enabled" register "RMT" = "1" - register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" @@ -48,22 +46,6 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" register "PcieRpEnable[16]" = "1" register "PcieRpEnable[17]" = "1" register "PcieRpEnable[18]" = "1" @@ -95,46 +77,15 @@ register "PcieClkSrcClkReq[9]" = "9" register "PcieClkSrcClkReq[10]" = "10" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # HECI - register "HeciEnabled" = "1" - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C 0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.4 on end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 X4 SLOT 1 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 @@ -144,20 +95,9 @@ device pci 1d.7 off end # PCI Express Port 16 device pci 1b.0 on end # PCI Express Port 17 device pci 1b.4 on end # PCI Express Port 21 X4 SLOT 2 - device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb deleted file mode 100644 index e5f867c..0000000 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb +++ /dev/null @@ -1,156 +0,0 @@ -chip soc/intel/cannonlake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "ScsEmmcHs400Enabled" = "1" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" - - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" - - register "PcieClkSrcUsage[0]" = "1" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "13" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "14" - - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "1" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| I2C3 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[3] = { - .speed = I2C_SPEED_STANDARD, - .rise_time_ns = 104, - .fall_time_ns = 52, - }, - }" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 on - chip drivers/i2c/max98373 - register "interleave_mode" = "1" - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" - register "uid" = "0" - register "desc" = ""Right Speaker Amp"" - register "name" = ""MAXR"" - device i2c 32 on end - end - end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb new file mode 100644 index 0000000..11d93f8 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -0,0 +1,81 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + + register "PcieClkSrcUsage[0]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "14" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + # Enable S0ix + register "s0ix_enable" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| I2C3 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[3] = { + .speed = I2C_SPEED_STANDARD, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + }" + + device domain 0 on + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 15.2 off end # I2C #2 + device pci 15.3 on + chip drivers/i2c/max98373 + register "interleave_mode" = "1" + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 32 on end + end + end # I2C #3 + device pci 19.0 on end # I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb deleted file mode 100644 index 241ac33..0000000 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb +++ /dev/null @@ -1,167 +0,0 @@ -chip soc/intel/cannonlake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "ScsEmmcHs400Enabled" = "1" - register "HeciEnabled" = "1" - register "s0ix_enable" = "1" - - # Enable eDP device - register "DdiPortEdp" = "1" - # Enable HPD for DDI ports B/C - register "DdiPortBHpd" = "1" - register "DdiPortCHpd" = "1" - register "DdiPortDHpd" = "1" - register "DdiPortFHpd" = "1" - # Enable DDC for DDI ports B/C - register "DdiPortBDdc" = "1" - register "DdiPortCDdc" = "1" - register "DdiPortDDdc" = "1" - register "DdiPortFDdc" = "1" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, - }" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsEnable[3]" = "1" - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "1" - register "SataPortsEnable[7]" = "1" - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" - - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" - - register "PcieClkSrcUsage[0]" = "1" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "13" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "14" - - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE - end -end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb new file mode 100644 index 0000000..76a8a1b --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -0,0 +1,86 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + + register "PcieClkSrcUsage[0]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "14" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + device domain 0 on + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 17.0 on end # SATA + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.1 off end # UART #1 + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb new file mode 100644 index 0000000..3e8baf7 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -0,0 +1,74 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C/D/F + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C/D/F + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + + register "PcieClkSrcUsage[0]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "14" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + device domain 0 on + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.1 off end # UART #1 + device pci 1f.6 on end # GbE + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/36794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I067bdb3fcf1218b93e52801f6db093e24d7d2b62 Gerrit-Change-Number: 36794 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: [NOT FOR MERGE] - For Richard - hack the Makefile for testing
by Marshall Dawson (Code Review) 05 Dec '19

05 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37221 ) Change subject: [NOT FOR MERGE] - For Richard - hack the Makefile for testing ...................................................................... [NOT FOR MERGE] - For Richard - hack the Makefile for testing This will let you test WIP amd_blobs (and blobs) that you might want, without worrying the submodule will be updated when you use USE_AMD_BLOBS. Change-Id: Iaa6b1a3ed1fbeababb38aa5cdafd90e14fcac50f Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M Makefile.inc 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/37221/1 diff --git a/Makefile.inc b/Makefile.inc index dc5272e..b7170e2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -199,14 +199,14 @@ ifeq ($(CONFIG_USE_BLOBS),y) # These items are necessary because each has update=none in .gitmodules. They are ignored # until expressly requested and enabled with --checkout -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs)) +# forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs)) forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode)) ifeq ($(CONFIG_PLATFORM_USES_FSP1_0)$(CONFIG_PLATFORM_USES_FSP1_1)$(CONFIG_PLATFORM_USES_FSP2_0),y) forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp)) endif -ifeq ($(CONFIG_USE_AMD_BLOBS),y) -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs)) -endif +# ifeq ($(CONFIG_USE_AMD_BLOBS),y) +# forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs)) +# endif endif UPDATED_SUBMODULES:=1 COREBOOT_EXPORTS += UPDATED_SUBMODULES -- To view, visit https://review.coreboot.org/c/coreboot/+/37221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa6b1a3ed1fbeababb38aa5cdafd90e14fcac50f Gerrit-Change-Number: 37221 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/braswell: Use common sb code for SPI lockdown configuration
by Arthur Heymans (Code Review) 05 Dec '19

05 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36007 ) Change subject: soc/intel/braswell: Use common sb code for SPI lockdown configuration ...................................................................... soc/intel/braswell: Use common sb code for SPI lockdown configuration This removes the weakly linked function to configure the SPI lockdown. Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/facebook/fbg1701/w25q64.c M src/mainboard/google/cyan/w25q64.c M src/mainboard/intel/strago/w25q64.c M src/mainboard/portwell/m107/w25q64.c M src/soc/intel/braswell/include/soc/spi.h M src/soc/intel/braswell/southcluster.c 6 files changed, 22 insertions(+), 186 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/36007/1 diff --git a/src/mainboard/facebook/fbg1701/w25q64.c b/src/mainboard/facebook/fbg1701/w25q64.c index bc908f0..2f131f4 100644 --- a/src/mainboard/facebook/fbg1701/w25q64.c +++ b/src/mainboard/facebook/fbg1701/w25q64.c @@ -20,57 +20,16 @@ #include <drivers/spi/spi_winbond.h> /* - * SPI lockdown configuration + * SPI VSCC configuration */ -#define SPI_OPMENU_0 CMD_W25_WRSR /* Write Status Register */ -#define SPI_OPTYPE_0 SPI_OPTYPE_WR_NOADDR /* Write, no address */ - -#define SPI_OPMENU_1 CMD_W25_PP /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_2 CMD_W25_READ /* Read Data */ -#define SPI_OPTYPE_2 SPI_OPTYPE_RD_ADDR /* Read, address required */ - -#define SPI_OPMENU_3 CMD_W25_RDSR /* Read Status Register */ -#define SPI_OPTYPE_3 SPI_OPTYPE_RD_NOADDR /* Read, no address */ - -#define SPI_OPMENU_4 CMD_W25_SE /* Sector Erase */ -#define SPI_OPTYPE_4 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_5 CMD_W25_RDID /* Read ID */ -#define SPI_OPTYPE_5 SPI_OPTYPE_RD_NOADDR /* Read, no address */ - -#define SPI_OPMENU_6 CMD_W25_BE /* BE: Block Erase */ -#define SPI_OPTYPE_6 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_7 CMD_W25_FAST_READ /* FAST: Fast Read */ -#define SPI_OPTYPE_7 SPI_OPTYPE_RD_ADDR /* Read, address required */ - -#define SPI_OPPREFIX CMD_W25_WREN /* WREN only to be inline */ - /* with flashrom */ - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) - -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) - #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = CMD_W25_WREN, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/mainboard/google/cyan/w25q64.c b/src/mainboard/google/cyan/w25q64.c index 861a464..5eea802 100644 --- a/src/mainboard/google/cyan/w25q64.c +++ b/src/mainboard/google/cyan/w25q64.c @@ -18,52 +18,16 @@ #include <string.h> /* - * SPI lockdown configuration W25Q64FW. + * SPI VSCC configuration W25Q64FW. */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = SPI_OPPREFIX, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/mainboard/intel/strago/w25q64.c b/src/mainboard/intel/strago/w25q64.c index 861a464..5598de4 100644 --- a/src/mainboard/intel/strago/w25q64.c +++ b/src/mainboard/intel/strago/w25q64.c @@ -18,52 +18,17 @@ #include <string.h> /* - * SPI lockdown configuration W25Q64FW. + * SPI VSCC configuration W25Q64FW. */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = SPI_OPPREFIX, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/mainboard/portwell/m107/w25q64.c b/src/mainboard/portwell/m107/w25q64.c index bc908f0..2f131f4 100644 --- a/src/mainboard/portwell/m107/w25q64.c +++ b/src/mainboard/portwell/m107/w25q64.c @@ -20,57 +20,16 @@ #include <drivers/spi/spi_winbond.h> /* - * SPI lockdown configuration + * SPI VSCC configuration */ -#define SPI_OPMENU_0 CMD_W25_WRSR /* Write Status Register */ -#define SPI_OPTYPE_0 SPI_OPTYPE_WR_NOADDR /* Write, no address */ - -#define SPI_OPMENU_1 CMD_W25_PP /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_2 CMD_W25_READ /* Read Data */ -#define SPI_OPTYPE_2 SPI_OPTYPE_RD_ADDR /* Read, address required */ - -#define SPI_OPMENU_3 CMD_W25_RDSR /* Read Status Register */ -#define SPI_OPTYPE_3 SPI_OPTYPE_RD_NOADDR /* Read, no address */ - -#define SPI_OPMENU_4 CMD_W25_SE /* Sector Erase */ -#define SPI_OPTYPE_4 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_5 CMD_W25_RDID /* Read ID */ -#define SPI_OPTYPE_5 SPI_OPTYPE_RD_NOADDR /* Read, no address */ - -#define SPI_OPMENU_6 CMD_W25_BE /* BE: Block Erase */ -#define SPI_OPTYPE_6 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_7 CMD_W25_FAST_READ /* FAST: Fast Read */ -#define SPI_OPTYPE_7 SPI_OPTYPE_RD_ADDR /* Read, address required */ - -#define SPI_OPPREFIX CMD_W25_WREN /* WREN only to be inline */ - /* with flashrom */ - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) - -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) - #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = CMD_W25_WREN, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h index 2d27545..ddbe7b9 100644 --- a/src/soc/intel/braswell/include/soc/spi.h +++ b/src/soc/intel/braswell/include/soc/spi.h @@ -60,17 +60,14 @@ # define BCR_WPD (0x1 << 0) /* - * SPI lockdown configuration. + * SPI VSCC configuration. */ -struct spi_config { - uint16_t preop; - uint16_t optype; - uint32_t opmenu[2]; +struct vscc_config { uint32_t lvscc; uint32_t uvscc; }; /* Return 0 on success < 0 on failure. */ -int mainboard_get_spi_config(struct spi_config *cfg); +int mainboard_get_spi_vscc_config(struct vscc_config *cfg); #endif /* _SOC_SPI_H_ */ diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index c233dc8..8b13fd0 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -42,6 +42,7 @@ #include <soc/spi.h> #include <spi-generic.h> #include <stdint.h> +#include <southbridge/intel/common/spi.h> static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode) { @@ -608,13 +609,6 @@ .device = LPC_DEVID, }; -int __weak mainboard_get_spi_config(struct spi_config *cfg) -{ - printk(BIOS_SPEW, "%s/%s (0x%p)\n", - __FILE__, __func__, (void *)cfg); - return -1; -} - static void finalize_chipset(void *unused) { void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); @@ -622,7 +616,7 @@ void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2); void *etr = (void *)(PMC_BASE_ADDRESS + ETR); uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; - struct spi_config cfg; + struct vscc_config cfg; printk(BIOS_SPEW, "%s/%s (0x%p)\n", __FILE__, __func__, unused); @@ -639,14 +633,12 @@ /* Set the CF9 lock. */ write32(etr, read32(etr) | CF9LOCK); - if (mainboard_get_spi_config(&cfg) < 0) { - printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); + spi_finalize_ops(); + write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); + + if (mainboard_get_spi_vscc_config(&cfg) < 0) { + printk(BIOS_DEBUG, "No SPI VSCC configuration.\n"); } else { - write16(spi + PREOP, cfg.preop); - write16(spi + OPTYPE, cfg.optype); - write32(spi + OPMENU0, cfg.opmenu[0]); - write32(spi + OPMENU1, cfg.opmenu[1]); - write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); write32(spi + UVSCC, cfg.uvscc); write32(spi + LVSCC, cfg.lvscc | VCL); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113 Gerrit-Change-Number: 36007 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: mb/intel/icelake_rvp: Remove nested variant header references
by Aamir Bohra (Code Review) 05 Dec '19

05 Dec '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37356 ) Change subject: mb/intel/icelake_rvp: Remove nested variant header references ...................................................................... mb/intel/icelake_rvp: Remove nested variant header references Change-Id: I11b2d75dc0d4ff180b03324e5ce3d5590c8169a5 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/bootblock.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/hda_verb.c M src/mainboard/intel/icelake_rvp/mainboard.c M src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h R src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h M src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h D src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h D src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h D src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h D src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h D src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h 13 files changed, 7 insertions(+), 798 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/37356/1 diff --git a/src/mainboard/intel/icelake_rvp/bootblock.c b/src/mainboard/intel/icelake_rvp/bootblock.c index 8655947..f982bf4 100644 --- a/src/mainboard/intel/icelake_rvp/bootblock.c +++ b/src/mainboard/intel/icelake_rvp/bootblock.c @@ -12,11 +12,10 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <bootblock_common.h> #include <soc/gpio.h> -#include <variant/gpio.h> void bootblock_mainboard_init(void) { diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index 785fe4a..da3f1d4 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -14,11 +14,10 @@ */ #include <arch/acpi.h> +#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boot/coreboot_tables.h> #include <gpio.h> -#include <soc/gpio.h> -#include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 152f038..f8fcd4d 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -14,8 +14,8 @@ */ #include <arch/acpi.h> -#include "variant/ec.h" -#include "variant/gpio.h" +#include <baseboard/ec.h> +#include <baseboard/gpio.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/intel/icelake_rvp/hda_verb.c b/src/mainboard/intel/icelake_rvp/hda_verb.c index c87392d..c01530b 100644 --- a/src/mainboard/intel/icelake_rvp/hda_verb.c +++ b/src/mainboard/intel/icelake_rvp/hda_verb.c @@ -12,5 +12,4 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - -#include "variant/hda_verb.h" +#include <baseboard/hda_verb.h> \ No newline at end of file diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c index 8e51e45..edc27a9 100644 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ b/src/mainboard/intel/icelake_rvp/mainboard.c @@ -14,11 +14,10 @@ */ #include <arch/acpi.h> +#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <device/device.h> -#include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <variant/gpio.h> static void mainboard_init(void *chip_info) { diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h index 03096ac..ed33547 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h @@ -18,9 +18,7 @@ #include <ec/ec.h> #include <ec/google/chromeec/ec_commands.h> - -#include <variant/gpio.h> - +#include <baseboard/gpio.h> #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/hda_verb.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h similarity index 100% rename from src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/hda_verb.h rename to src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h index 12d16bc..a00b344 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -25,7 +25,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); - const struct cros_gpio *variant_cros_gpios(size_t *num); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h deleted file mode 100644 index af41bf4..0000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_EC_H__ -#define __MAINBOARD_EC_H__ - -#include <baseboard/ec.h> - -#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h deleted file mode 100644 index c34a9b3..0000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GPIO_H__ -#define __MAINBOARD_GPIO_H__ - -#include <baseboard/gpio.h> - -#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h deleted file mode 100644 index af41bf4..0000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_EC_H__ -#define __MAINBOARD_EC_H__ - -#include <baseboard/ec.h> - -#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h deleted file mode 100644 index c34a9b3..0000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GPIO_H__ -#define __MAINBOARD_GPIO_H__ - -#include <baseboard/gpio.h> - -#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h deleted file mode 100644 index d821a26..0000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h +++ /dev/null @@ -1,700 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef HDA_VERB_H -#define HDA_VERB_H - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* ALC 700 */ - 0x10EC0700, - 0xFFFFFFFF, - 0x00000023, - - AZALIA_SUBVENDOR(0, 0x10EC10F2), - AZALIA_PIN_CFG(0, 0x01, 0x00000000), - AZALIA_PIN_CFG(0, 0x12, 0x40000000), - AZALIA_PIN_CFG(0, 0x13, 0x40000000), - AZALIA_PIN_CFG(0, 0x14, 0x411111F0), - AZALIA_PIN_CFG(0, 0x15, 0x411111F0), - AZALIA_PIN_CFG(0, 0x16, 0x411111F0), - AZALIA_PIN_CFG(0, 0x17, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111F0), - AZALIA_PIN_CFG(0, 0x19, 0x04A11030), - AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1D, 0x40622005), - AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1F, 0x411111F0), - AZALIA_PIN_CFG(0, 0x21, 0x04211020), - AZALIA_PIN_CFG(0, 0x29, 0x411111F0), - - /* Widget node 0x20 */ - 0x02050045, - 0x02045289, - 0x0205004A, - 0x0204201B, - /* Widget node 0x20 - 1 */ - 0x05850000, - 0x05843888, - 0x0205006F, - 0x02042C0B, - - //Widget node 0X20 for ALC1305 20160603 update - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040000, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040004, - 0x02050028, - 0x02040600, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FFD0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040080, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003A, - 0x02050028, - 0x02040DFE, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x0204005D, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x02040442, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040005, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040006, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040008, - 0x02050028, - 0x0204B000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204002E, - 0x02050028, - 0x02040800, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400C3, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204D4A0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400CC, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204400A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400C1, - 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- 0x02050024, - 0x02040010, - 0x02050026, - 0x02040004, - 0x02050028, - 0x02040500, - 0x02050029, - 0x0204B024 -}; - -const u32 pc_beep_verbs[] = { -}; -AZALIA_ARRAY_SIZES; -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11b2d75dc0d4ff180b03324e5ce3d5590c8169a5 Gerrit-Change-Number: 37356 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

8 15

Change in coreboot[master]: trogdor: libpayload USB support
by mturney mturney (Code Review) 05 Dec '19

05 Dec '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36233 ) Change subject: trogdor: libpayload USB support ...................................................................... trogdor: libpayload USB support Change-Id: I26c28f9af8d819f4644e383e8d0293a3d5de9eef Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> --- M payloads/libpayload/configs/config.trogdor 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/36233/1 diff --git a/payloads/libpayload/configs/config.trogdor b/payloads/libpayload/configs/config.trogdor index 0625ff5..7ca654b 100644 --- a/payloads/libpayload/configs/config.trogdor +++ b/payloads/libpayload/configs/config.trogdor @@ -3,3 +3,6 @@ CONFIG_LP_TIMER_ARM64_ARCH=y CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_SC7180_SERIAL_CONSOLE=y +CONFIG_LP_USB=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y -- To view, visit https://review.coreboot.org/c/coreboot/+/36233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26c28f9af8d819f4644e383e8d0293a3d5de9eef Gerrit-Change-Number: 36233 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: trogdor: Add mainboard USB support
by mturney mturney (Code Review) 05 Dec '19

05 Dec '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36232 ) Change subject: trogdor: Add mainboard USB support ...................................................................... trogdor: Add mainboard USB support Change-Id: I126d1d6b582ea95c97ac55784d44d3081aabdae7 Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> --- M src/mainboard/google/trogdor/mainboard.c M src/mainboard/google/trogdor/romstage.c 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/36232/1 diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index dbdb4ed..170955a 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -19,10 +19,23 @@ #include <gpio.h> #include <timestamp.h> #include <soc/qupv3_fw_config.h> +#include <soc/usb.h> + +static struct usb_board_data usb0_board_data = { + .pll_bias_control_2 = 0x22, + .imp_ctrl1 = 0x08, + .port_tune1 = 0xc5, +}; + +static void setup_usb(void) +{ + setup_usb_host0(&usb0_board_data); +} static void mainboard_init(struct device *dev) { qupv3_fw_init(); + setup_usb(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c index 7185387..872798a 100644 --- a/src/mainboard/google/trogdor/romstage.c +++ b/src/mainboard/google/trogdor/romstage.c @@ -14,10 +14,22 @@ */ #include <arch/stages.h> +#include <soc/usb.h> #include <soc/qclib_common.h> +static void prepare_usb(void) +{ + /* + * Do DWC3 core and phy reset. Kick these resets + * off early so they get at least 1ms to settle. + */ + reset_usb0(); +} + void platform_romstage_main(void) { + prepare_usb(); + /* QCLib: DDR init & train */ qclib_load_and_run(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I126d1d6b582ea95c97ac55784d44d3081aabdae7 Gerrit-Change-Number: 36232 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: sc7180: Add USB support
by mturney mturney (Code Review) 05 Dec '19

05 Dec '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35503 ) Change subject: sc7180: Add USB support ...................................................................... sc7180: Add USB support This includes USB QUSB2,QMP Phy and Controller support And libpayload support for USB Change-Id: I0651fc28dc227efbeb23eeefe9b96a3b940ae995 Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> --- M payloads/libpayload/configs/config.trogdor M src/mainboard/google/trogdor/mainboard.c M src/mainboard/google/trogdor/romstage.c M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/include/soc/addressmap.h M src/soc/qualcomm/sc7180/include/soc/clock.h A src/soc/qualcomm/sc7180/include/soc/efuse.h A src/soc/qualcomm/sc7180/include/soc/usb.h A src/soc/qualcomm/sc7180/usb.c 9 files changed, 931 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35503/1 diff --git a/payloads/libpayload/configs/config.trogdor b/payloads/libpayload/configs/config.trogdor index 0625ff5..7ca654b 100644 --- a/payloads/libpayload/configs/config.trogdor +++ b/payloads/libpayload/configs/config.trogdor @@ -3,3 +3,6 @@ CONFIG_LP_TIMER_ARM64_ARCH=y CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_SC7180_SERIAL_CONSOLE=y +CONFIG_LP_USB=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index dbdb4ed..170955a 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -19,10 +19,23 @@ #include <gpio.h> #include <timestamp.h> #include <soc/qupv3_fw_config.h> +#include <soc/usb.h> + +static struct usb_board_data usb0_board_data = { + .pll_bias_control_2 = 0x22, + .imp_ctrl1 = 0x08, + .port_tune1 = 0xc5, +}; + +static void setup_usb(void) +{ + setup_usb_host0(&usb0_board_data); +} static void mainboard_init(struct device *dev) { qupv3_fw_init(); + setup_usb(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c index 7185387..872798a 100644 --- a/src/mainboard/google/trogdor/romstage.c +++ b/src/mainboard/google/trogdor/romstage.c @@ -14,10 +14,22 @@ */ #include <arch/stages.h> +#include <soc/usb.h> #include <soc/qclib_common.h> +static void prepare_usb(void) +{ + /* + * Do DWC3 core and phy reset. Kick these resets + * off early so they get at least 1ms to settle. + */ + reset_usb0(); +} + void platform_romstage_main(void) { + prepare_usb(); + /* QCLib: DDR init & train */ qclib_load_and_run(); } diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index d8fc33a..8db260d 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -28,6 +28,8 @@ romstage-y += timer.c romstage-y += gpio.c romstage-y += ../common/qclib.c +romstage-y += qclib.c +romstage-y += usb.c romstage-y += ../common/mmu.c romstage-y += mmu.c romstage-y += spi.c @@ -49,6 +51,7 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c ramstage-y += aop_load_reset.c +ramstage-y += usb.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index 1a24d94..ae6bb6b 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -46,4 +46,16 @@ #define QUP_SERIAL10_BASE 0xA90000 #define QUP_SERIAL11_BASE 0xA94000 +/* + * USB BASE ADDRESSES + */ +#define QFPROM_BASE 0x00780000 +#define QUSB_PRIM_PHY_BASE 0x088e3000 +#define QUSB_PRIM_PHY_DIG_BASE 0x088e3200 +#define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 +#define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 +#define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 +#define QMP_PHY_PCS_REG_BASE 0x088e9c00 +#define USB_HOST_DWC3_BASE 0x0a60c100 + #endif /* __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index d90779b..ae9abd2 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -76,7 +76,7 @@ struct sc7180_gpll gpll0; u8 _res0[0xf000 - 0x1000]; u32 usb30_prim_bcr; - u8 _res3[0x17000 - 0xf004]; + u8 _res1[0x17000 - 0xf004]; u32 qup_wrap0_bcr; u32 qup_wrap0_m_ahb_cbcr; u32 qup_wrap0_s_ahb_cbcr; @@ -84,33 +84,39 @@ u32 qup_wrap0_core_cdivr; u32 qup_wrap0_core_2x_cbcr; struct sc7180_rcg qup_wrap0_core_2x; - u8 _res4[0x17030 - 0x17020]; + u8 _res2[0x17030 - 0x17020]; struct sc7180_qupv3_clock qup_wrap0_s[6]; - u8 _res5[0x18000 - 0x17750]; + u8 _res3[0x18000 - 0x17750]; u32 qup_wrap1_bcr; u32 qup_wrap1_core_2x_cbcr; u32 qup_wrap1_core_cbcr; u32 qup_wrap1_m_ahb_cbcr; u32 qup_wrap1_s_ahb_cbcr; struct sc7180_qupv3_clock qup_wrap1_s[6]; - u8 _res6[0x18994 - 0x18734]; + u8 _res4[0x18994-0x18734]; u32 qup_wrap1_core_cdivr; - u8 _res7[0x4b000 - 0x18998]; + u8 _res5[0x26000-0x18998]; + u32 qusb2phy_prim_bcr; + u8 _res6[0x4B000 - 0x26004]; u32 qspi_bcr; u32 qspi_cnoc_ahb_cbcr; u32 qspi_core_cbcr; struct sc7180_rcg qspi_core; - u8 _res8[0x50000 - 0x4b014]; + u8 _res7[0x50000-0x4b014]; u32 usb3_phy_prim_bcr; u32 usb3phy_phy_prim_bcr; u32 usb3_dp_phy_prim_bcr; u32 usb3_phy_sec_bcr; u32 usb3phy_phy_sec_bcr; u32 usb3_dp_phy_sec_bcr; - u8 _res9[0x52008 - 0x50018]; + u8 _res8[0x52008-0x50018]; u32 apcs_clk_br_en1; - u8 _res10[0x1000000 - 0x5200c]; + u8 _res9[0x1000000-0x5200c]; }; +check_member(sc7180_gcc, usb30_prim_bcr, 0xf000); +check_member(sc7180_gcc, qusb2phy_prim_bcr, 0x26000); +check_member(sc7180_gcc, usb3phy_phy_prim_bcr, 0x50004); +check_member(sc7180_gcc, usb3_phy_prim_bcr, 0x50000); struct sc7180_aoss { u8 _res[0x5002c]; diff --git a/src/soc/qualcomm/sc7180/include/soc/efuse.h b/src/soc/qualcomm/sc7180/include/soc/efuse.h new file mode 100644 index 0000000..baaa971 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/efuse.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__ +#define __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__ + +/** + * USB EFUSE registers + */ +struct qfprom_corr { + u8 rsvd[0x4258 - 0x0]; + u32 qusb_hstx_trim_lsb; +}; +check_member(qfprom_corr, qusb_hstx_trim_lsb, 0x4258); + +#endif /* __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/usb.h b/src/soc/qualcomm/sc7180/include/soc/usb.h new file mode 100644 index 0000000..3a8816a --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/usb.h @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <types.h> + +#ifndef _SC7180_USB_H_ +#define _SC7180_USB_H_ + +/* QSCRATCH_GENERAL_CFG register bit offset */ +#define PIPE_UTMI_CLK_SEL BIT(0) +#define PIPE3_PHYSTATUS_SW BIT(3) +#define PIPE_UTMI_CLK_DIS BIT(8) + +/* Global USB3 Control Registers */ +#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) +#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_PRTCAP_HOST 1 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define USBTRDTIM_UTMI_8_BIT 9 +#define UTMI_PHYIF_8_BIT 0 + +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE (1 << 3) +#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) + +#define PORT_TUNE1_MASK 0xf0 + +/* QUSB2PHY_PWR_CTRL1 register related bits */ +#define POWER_DOWN BIT(0) + +/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */ +#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 + +/* STAT5 register bits */ +#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) + +/* QUSB PHY register values */ +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c +#define QUSB2PHY_PLL_CMODE 0x80 +#define QUSB2PHY_PLL_LOCK_DELAY 0x0a +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x22 +#define QUSB2PHY_PWR_CTRL2 0x21 +#define QUSB2PHY_IMP_CTRL1 0x08 +#define QUSB2PHY_IMP_CTRL2 0x58 +#define QUSB2PHY_PORT_TUNE1 0xc5 +#define QUSB2PHY_PORT_TUNE2 0x29 +#define QUSB2PHY_PORT_TUNE3 0xca +#define QUSB2PHY_PORT_TUNE4 0x04 +#define QUSB2PHY_PORT_TUNE5 0x03 +#define QUSB2PHY_CHG_CTRL2 0x30 + +/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ +#define USB3_PCS_PHYSTATUS BIT(6) + +struct usb_board_data { + /* Register values going to override from the boardfile */ + u32 pll_bias_control_2; + u32 imp_ctrl1; + u32 port_tune1; +}; + +struct qmp_phy_init_tbl { + u32 *address; + u32 val; +}; + +void setup_usb_host0(struct usb_board_data *data); + +/* Call reset_ before setup_ */ +void reset_usb0(void); + + +#endif /* _SC7180_USB_H_ */ diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/sc7180/usb.c new file mode 100644 index 0000000..7c65830 --- /dev/null +++ b/src/soc/qualcomm/sc7180/usb.c @@ -0,0 +1,750 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <stdlib.h> +#include <console/console.h> +#include <delay.h> +#include <soc/usb.h> +#include <soc/clock.h> +#include <soc/addressmap.h> +#include <soc/efuse.h> +#include <timer.h> + +struct usb_qusb_phy_dig { + u8 rsvd1[16]; + u32 pwr_ctrl1; + u32 pwr_ctrl2; + u8 rsvd2[8]; + u32 imp_ctrl1; + u32 imp_ctrl2; + u8 rsvd3[20]; + u32 chg_ctrl2; + u32 tune1; + u32 tune2; + u32 tune3; + u32 tune4; + u32 tune5; + u8 rsvd4[44]; + u32 debug_ctrl2; + u8 rsvd5[28]; + u32 debug_stat5; +}; +check_member(usb_qusb_phy_dig, tune5, 0x50); +check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80); +check_member(usb_qusb_phy_dig, debug_stat5, 0xA0); + +struct usb_qusb_phy_pll { + u8 rsvd0[4]; + u32 analog_controls_two; + u8 rsvd1[36]; + u32 cmode; + u8 rsvd2[132]; + u32 dig_tim; + u8 rsvd3[204]; + u32 lock_delay; + u8 rsvd4[4]; + u32 clock_inverters; + u8 rsvd5[4]; + u32 bias_ctrl_1; + u32 bias_ctrl_2; +}; +check_member(usb_qusb_phy_pll, cmode, 0x2C); +check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198); +check_member(usb_qusb_phy_pll, dig_tim, 0xB4); + +/* Only for QMP V3 PHY - QSERDES COM registers */ +struct usb3_phy_qserdes_com_reg_layout { + u8 _reserved1[16]; + u32 com_ssc_en_center; + u32 com_ssc_adj_per1; + u32 com_ssc_adj_per2; + u32 com_ssc_per1; + u32 com_ssc_per2; + u32 com_ssc_step_size1; + u32 com_ssc_step_size2; + u8 _reserved2[8]; + u32 com_bias_en_clkbuflr_en; + u32 com_sys_clk_enable1; + u32 com_sys_clk_ctrl; + u32 com_sysclk_buf_enable; + u32 com_pll_en; + u32 com_pll_ivco; + u8 _reserved3[20]; + u32 com_cp_ctrl_mode0; + u8 _reserved4[4]; + u32 com_pll_rctrl_mode0; + u8 _reserved5[4]; + u32 com_pll_cctrl_mode0; + u8 _reserved6[12]; + u32 com_sysclk_en_sel; + u8 _reserved7[8]; + u32 com_resetsm_ctrl2; + u32 com_lock_cmp_en; + u32 com_lock_cmp_cfg; + u32 com_lock_cmp1_mode0; + u32 com_lock_cmp2_mode0; + u32 com_lock_cmp3_mode0; + u8 _reserved8[12]; + u32 com_dec_start_mode0; + u8 _reserved9[4]; + u32 com_div_frac_start1_mode0; + u32 com_div_frac_start2_mode0; + u32 com_div_frac_start3_mode0; + u8 _reserved10[20]; + u32 com_integloop_gain0_mode0; + u32 com_integloop_gain1_mode0; + u8 _reserved11[16]; + u32 com_vco_tune_map; + u32 com_vco_tune1_mode0; + u32 com_vco_tune2_mode0; + u8 _reserved12[60]; + u32 com_clk_select; + u32 com_hsclk_sel; + u8 _reserved13[8]; + u32 com_coreclk_div_mode0; + u8 _reserved14[8]; + u32 com_core_clk_en; + u32 com_c_ready_status; + u32 com_cmn_config; + u32 com_cmn_rate_override; + u32 com_svs_mode_clk_sel; +}; +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020); +check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x034); +check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x048); +check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x060); +check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x080); +check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x08c); +check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0b0); +check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0b8); +check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0d8); +check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x0f0); +check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x138); +check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x148); +check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x154); +check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x164); + +/* Only for QMP V3 PHY - TX registers */ +struct usb3_phy_qserdes_tx_reg_layout { + u8 _reserved1[68]; + u32 tx_res_code_lane_offset_tx; + u32 tx_res_code_lane_offset_rx; + u8 _reserved2[20]; + u32 tx_highz_drvr_en; + u8 _reserved3[40]; + u32 tx_lane_mode_1; + u8 _reserved4[20]; + u32 tx_rcv_detect_lvl_2; +}; +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x044); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x048); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_highz_drvr_en, 0x060); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x08c); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x0a4); + +/* Only for QMP V3 PHY - RX registers */ +struct usb3_phy_qserdes_rx_reg_layout { + u8 _reserved1[8]; + u32 rx_ucdr_fo_gain; + u32 rx_ucdr_so_gain_half; + u8 _reserved2[32]; + u32 rx_ucdr_fastlock_fo_gain; + u32 rx_ucdr_so_saturtn_and_en; + u8 _reserved3[12]; + u32 rx_ucdr_pi_cntrls; + u8 _reserved4[120]; + u32 rx_vga_cal_ctrl2; + u8 _reserved5[16]; + u32 rx_rx_equ_adap_ctrl2; + u32 rx_rx_equ_adap_ctrl3; + u32 rx_rx_equ_adap_ctrl4; + u8 _reserved6[24]; + u32 rx_rx_eq_offset_adap_ctrl1; + u32 rx_rx_offset_adap_ctrl2; + u32 rx_sigdet_enables; + u32 rx_sigdet_ctrl; + u8 _reserved7[4]; + u32 rx_sigdet_deglitch_ctrl; + u32 rx_rx_band; + u8 _reserved8[80]; + u32 rx_rx_mode_00; +}; +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fo_gain, 0x008); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain_half, 0x00c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_saturtn_and_en, 0x034); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_cntrls, 0x044); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_ctrl2, 0x0c0); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl2, 0x0d4); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl3, 0x0d8); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl4, 0x0dc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_eq_offset_adap_ctrl1, 0x0f8); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_offset_adap_ctrl2, 0x0fc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_enables, 0x100); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_ctrl, 0x104); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_deglitch_ctrl, 0x10c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_band, 0x110); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00, 0x164); + +/* Only for QMP V3 PHY - PCS registers */ +struct usb3_phy_pcs_reg_layout { + u32 pcs_sw_reset; + u32 pcs_power_down_control; + u32 pcs_start_control; + u32 pcs_txmgn_v0; + u32 pcs_txmgn_v1; + u32 pcs_txmgn_v2; + u32 pcs_txmgn_v3; + u32 pcs_txmgn_v4; + u32 pcs_txmgn_ls; + u32 pcs_txdeemph_m6db_v0; + u32 pcs_txdeemph_m3p5db_v0; + u32 pcs_txdeemph_m6db_v1; + u32 pcs_txdeemph_m3p5db_v1; + u32 pcs_txdeemph_m6db_v2; + u32 pcs_txdeemph_m3p5db_v2; + u32 pcs_txdeemph_m6db_v3; + u32 pcs_txdeemph_m3p5db_v3; + u32 pcs_txdeemph_m6db_v4; + u32 pcs_txdeemph_m3p5db_v4; + u32 pcs_txdeemph_m6db_ls; + u32 pcs_txdeemph_m3p5db_ls; + u8 _reserved1[8]; + u32 pcs_rate_slew_cntrl; + u8 _reserved2[4]; + u32 pcs_power_state_config2; + u8 _reserved3[8]; + u32 pcs_rcvr_dtct_dly_p1u2_l; + u32 pcs_rcvr_dtct_dly_p1u2_h; + u32 pcs_rcvr_dtct_dly_u3_l; + u32 pcs_rcvr_dtct_dly_u3_h; + u32 pcs_lock_detect_config1; + u32 pcs_lock_detect_config2; + u32 pcs_lock_detect_config3; + u32 pcs_tsync_rsync_time; + u8 _reserved4[16]; + u32 pcs_pwrup_reset_dly_time_auxclk; + u8 _reserved5[12]; + u32 pcs_lfps_ecstart_eqtlock; + u8 _reserved6[4]; + u32 pcs_rxeqtraining_wait_time; + u32 pcs_rxeqtraining_run_time; + u8 _reserved7[4]; + u32 pcs_fll_ctrl1; + u32 pcs_fll_ctrl2; + u32 pcs_fll_cnt_val_l; + u32 pcs_fll_cnt_val_h_tol; + u32 pcs_fll_man_code; + u32 pcs_autonomous_mode_ctrl; + u8 _reserved8[152]; + u32 pcs_ready_status; + u8 _reserved9[96]; + u32 pcs_rx_sigdet_lvl; + u8 _reserved10[48]; + u32 pcs_refgen_req_config1; + u32 pcs_refgen_req_config2; +}; +check_member(usb3_phy_pcs_reg_layout, pcs_sw_reset, 0x000); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v0, 0x00c); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v1, 0x010); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v2, 0x014); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v3, 0x018); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v4, 0x01c); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_ls, 0x020); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v0, 0x024); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v0, 0x028); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v1, 0x02c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v1, 0x030); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v2, 0x034); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v2, 0x038); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v3, 0x03c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v3, 0x040); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v4, 0x044); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v4, 0x048); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_ls, 0x04c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_ls, 0x050); +check_member(usb3_phy_pcs_reg_layout, pcs_rate_slew_cntrl, 0x05c); +check_member(usb3_phy_pcs_reg_layout, pcs_power_state_config2, 0x064); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_l, 0x070); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_h, 0x074); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_l, 0x078); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_h, 0x07c); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x080); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x084); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config3, 0x088); +check_member(usb3_phy_pcs_reg_layout, pcs_pwrup_reset_dly_time_auxclk, 0x0a0); +check_member(usb3_phy_pcs_reg_layout, pcs_rxeqtraining_wait_time, 0x0b8); +check_member(usb3_phy_pcs_reg_layout, pcs_fll_cnt_val_h_tol, 0x0d0); +check_member(usb3_phy_pcs_reg_layout, pcs_autonomous_mode_ctrl, 0x0d8); +check_member(usb3_phy_pcs_reg_layout, pcs_ready_status, 0x174); +check_member(usb3_phy_pcs_reg_layout, pcs_refgen_req_config2, 0x210); + +static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout = + (void *)QMP_PHY_QSERDES_COM_REG_BASE; +static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout = + (void *)QMP_PHY_QSERDES_TX_REG_BASE; +static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = + (void *)QMP_PHY_QSERDES_RX_REG_BASE; +static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = + (void *)QMP_PHY_PCS_REG_BASE; + + + +struct usb_dwc3 { + u32 sbuscfg0; + u32 sbuscfg1; + u32 txthrcfg; + u32 rxthrcfg; + u32 ctl; + u32 pmsts; + u32 sts; + u32 uctl1; + u32 snpsid; + u32 gpio; + u32 uid; + u32 uctl; + u64 buserraddr; + u64 prtbimap; + u8 reserved1[32]; + u32 dbgfifospace; + u32 dbgltssm; + u32 dbglnmcc; + u32 dbgbmu; + u32 dbglspmux; + u32 dbglsp; + u32 dbgepinfo0; + u32 dbgepinfo1; + u64 prtbimap_hs; + u64 prtbimap_fs; + u8 reserved2[112]; + u32 usb2phycfg; + u8 reserved3[124]; + u32 usb2phyacc; + u8 reserved4[60]; + u32 usb3pipectl; + u8 reserved5[60]; +}; +check_member(usb_dwc3, usb3pipectl, 0x1c0); + +static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { + {&qserdes_com_reg_layout->com_pll_ivco, 0x07}, + {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x14}, + {&qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x08}, + {&qserdes_com_reg_layout->com_clk_select, 0x30}, + {&qserdes_com_reg_layout->com_sys_clk_ctrl, 0x02}, + {&qserdes_com_reg_layout->com_resetsm_ctrl2, 0x08}, + {&qserdes_com_reg_layout->com_cmn_config, 0x16}, + {&qserdes_com_reg_layout->com_svs_mode_clk_sel, 0x01}, + {&qserdes_com_reg_layout->com_hsclk_sel, 0x80}, + {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, + {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, + {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, + {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, + {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, + {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, + {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, + {&qserdes_com_reg_layout->com_integloop_gain1_mode0, 0x00}, + {&qserdes_com_reg_layout->com_integloop_gain0_mode0, 0x3f}, + {&qserdes_com_reg_layout->com_vco_tune2_mode0, 0x01}, + {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0xc9}, + {&qserdes_com_reg_layout->com_coreclk_div_mode0, 0x0a}, + {&qserdes_com_reg_layout->com_lock_cmp3_mode0, 0x00}, + {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, + {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x15}, + {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, + {&qserdes_com_reg_layout->com_core_clk_en, 0x00}, + {&qserdes_com_reg_layout->com_lock_cmp_cfg, 0x00}, + {&qserdes_com_reg_layout->com_vco_tune_map, 0x00}, + {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, + {&qserdes_com_reg_layout->com_ssc_en_center, 0x01}, + {&qserdes_com_reg_layout->com_ssc_per1, 0x31}, + {&qserdes_com_reg_layout->com_ssc_per2, 0x01}, + {&qserdes_com_reg_layout->com_ssc_adj_per1, 0x00}, + {&qserdes_com_reg_layout->com_ssc_adj_per2, 0x00}, + {&qserdes_com_reg_layout->com_ssc_step_size1, 0x85}, + {&qserdes_com_reg_layout->com_ssc_step_size2, 0x07}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { + {&qserdes_tx_reg_layout->tx_highz_drvr_en, 0x10}, + {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, + {&qserdes_tx_reg_layout->tx_lane_mode_1, 0x16}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x09}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x06}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x0b}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0f}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl3, 0x4e}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl4, 0x18}, + {&qserdes_rx_reg_layout->rx_rx_eq_offset_adap_ctrl1, 0x77}, + {&qserdes_rx_reg_layout->rx_rx_offset_adap_ctrl2, 0x80}, + {&qserdes_rx_reg_layout->rx_sigdet_ctrl, 0x03}, + {&qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x16}, + {&qserdes_rx_reg_layout->rx_ucdr_so_saturtn_and_en, 0x75}, + {&qserdes_rx_reg_layout->rx_ucdr_pi_cntrls, 0x80}, + {&qserdes_rx_reg_layout->rx_ucdr_fo_gain, 0x0a}, + {&qserdes_rx_reg_layout->rx_ucdr_so_gain_half, 0x06}, + {&qserdes_rx_reg_layout->rx_sigdet_enables, 0x00}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { + /* FLL settings */ + {&pcs_reg_layout->pcs_fll_ctrl2, 0x83}, + {&pcs_reg_layout->pcs_fll_cnt_val_l, 0x09}, + {&pcs_reg_layout->pcs_fll_cnt_val_h_tol, 0xa2}, + {&pcs_reg_layout->pcs_fll_man_code, 0x40}, + {&pcs_reg_layout->pcs_fll_ctrl1, 0x02}, + + /* Lock Det settings */ + {&pcs_reg_layout->pcs_lock_detect_config1, 0xd1}, + {&pcs_reg_layout->pcs_lock_detect_config2, 0x1f}, + {&pcs_reg_layout->pcs_lock_detect_config3, 0x47}, + {&pcs_reg_layout->pcs_power_state_config2, 0x1b}, + + {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xba}, + {&pcs_reg_layout->pcs_txmgn_v0, 0x9f}, + {&pcs_reg_layout->pcs_txmgn_v1, 0x9f}, + {&pcs_reg_layout->pcs_txmgn_v2, 0xb7}, + {&pcs_reg_layout->pcs_txmgn_v3, 0x4e}, + {&pcs_reg_layout->pcs_txmgn_v4, 0x65}, + {&pcs_reg_layout->pcs_txmgn_ls, 0x6b}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v0, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v0, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v1, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v1, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v2, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v2, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v3, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v3, 0x1d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v4, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v4, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_ls, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_ls, 0x0d}, + {&pcs_reg_layout->pcs_rate_slew_cntrl, 0x02}, + {&pcs_reg_layout->pcs_pwrup_reset_dly_time_auxclk, 0x04}, + {&pcs_reg_layout->pcs_tsync_rsync_time, 0x44}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_l, 0xe7}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_h, 0x03}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_l, 0x40}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_h, 0x00}, + {&pcs_reg_layout->pcs_rxeqtraining_wait_time, 0x75}, + {&pcs_reg_layout->pcs_lfps_ecstart_eqtlock, 0x86}, + {&pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, +}; + + + +struct usb_dwc3_cfg { + struct usb_dwc3 *usb_host_dwc3; + struct usb_qusb_phy_pll *qusb_phy_pll; + struct usb_qusb_phy_dig *qusb_phy_dig; + /* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + struct usb3_phy_pcs_reg_layout *qmp_pcs_reg; + + u32 *usb3_bcr; + u32 *qusb2phy_bcr; + u32 *gcc_usb3phy_bcr_reg; + u32 *gcc_qmpphy_bcr_reg; + struct usb_board_data *board_data; + u32 efuse_offset; +}; + +static struct usb_dwc3_cfg usb_port0 = { + .usb_host_dwc3 = (void *)USB_HOST_DWC3_BASE, + .qusb_phy_pll = (void *)QUSB_PRIM_PHY_BASE, + .qusb_phy_dig = (void *)QUSB_PRIM_PHY_DIG_BASE, + .serdes_tbl = qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), + .tx_tbl = qmp_v3_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), + .rx_tbl = qmp_v3_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), + .pcs_tbl = qmp_v3_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), + .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, + .usb3_bcr = &gcc->usb30_prim_bcr, + .qusb2phy_bcr = &gcc->qusb2phy_prim_bcr, + .gcc_usb3phy_bcr_reg = &gcc->usb3_dp_phy_prim_bcr, + .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_prim_bcr, + .efuse_offset = 25, +}; + + +static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE; + +static void reset_usb(struct usb_dwc3_cfg *dwc3) +{ + /* Assert Core reset */ + clock_reset_bcr(dwc3->usb3_bcr, 1); + + /* Assert QUSB PHY reset */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 1); + + /* Assert QMP PHY reset */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1); +} + +void reset_usb0(void) +{ + /* Before Resetting PHY, put Core in Reset */ + printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(0)\n"); + + reset_usb(&usb_port0); +} + + +/* + * Update board specific PHY tuning override values that specified from + * board file. + */ +static void qusb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3) +{ + /* Override preemphasis value */ + write32(&dwc3->qusb_phy_dig->tune1, + dwc3->board_data->port_tune1); + + /* Override BIAS_CTRL_2 to reduce the TX swing overshooting. */ + write32(&dwc3->qusb_phy_pll->bias_ctrl_2, + dwc3->board_data->pll_bias_control_2); + + /* Override IMP_RES_OFFSET value */ + write32(&dwc3->qusb_phy_dig->imp_ctrl1, + dwc3->board_data->imp_ctrl1); +} + +/* + * Fetches HS Tx tuning value from efuse register and sets the + * QUSB2PHY_PORT_TUNE1/2 register. + * For error case, skip setting the value and use the default value. + */ +static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3) +{ + /* + * Efuse registers 3 bit value specifies tuning for HSTX + * output current in TUNE1 Register. Hence Extract 3 bits from + * EFUSE at correct position. + */ + + const int efuse_bits = 3; + int bit_pos = dwc3->efuse_offset; + + u32 bit_mask = (1 << efuse_bits) - 1; + u32 tune_val = + (read32(&qfprom_corr_efuse->qusb_hstx_trim_lsb) >> bit_pos) + & bit_mask; + /* + * if efuse reg is updated (i.e non-zero) then use it to program + * tune parameters. + */ + if (tune_val) + clrsetbits_le32(&dwc3->qusb_phy_dig->tune1, + PORT_TUNE1_MASK, tune_val << 4); +} + +static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy) +{ + write32(&phy->pwr_ctrl2, QUSB2PHY_PWR_CTRL2); + /* IMP_CTRL1: Control the impedance reduction */ + write32(&phy->imp_ctrl1, QUSB2PHY_IMP_CTRL1); + /* IMP_CTRL2: Impedance offset/mapping slope */ + write32(&phy->imp_ctrl2, QUSB2PHY_IMP_CTRL1); + write32(&phy->chg_ctrl2, QUSB2PHY_IMP_CTRL2); + /* + * TUNE1: Sets HS Impedance to approx 45 ohms + * then override with efuse value. + */ + write32(&phy->tune1, QUSB2PHY_PORT_TUNE1); + /* TUNE2: Tuning for HS Disconnect Level */ + write32(&phy->tune2, QUSB2PHY_PORT_TUNE2); + /* TUNE3: Tune squelch range */ + write32(&phy->tune3, QUSB2PHY_PORT_TUNE3); + /* TUNE4: Sets EOP_DLY(Squelch rising edge to linestate falling edge) */ + write32(&phy->tune4, QUSB2PHY_PORT_TUNE4); + write32(&phy->tune5, QUSB2PHY_PORT_TUNE5); + + if (dwc3->board_data) { + /* Override board specific PHY tuning values */ + qusb2_phy_override_phy_params(dwc3); + + /* Set efuse value for tuning the PHY */ + qusb2_phy_set_tune_param(dwc3); + } +} + +static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) +{ + /* PWR_CTRL: set the power down bit to disable the PHY */ + setbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&dwc3->qusb_phy_pll->analog_controls_two, + QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); + write32(&dwc3->qusb_phy_pll->clock_inverters, + QUSB2PHY_PLL_CLOCK_INVERTERS); + write32(&dwc3->qusb_phy_pll->cmode, + QUSB2PHY_PLL_CMODE); + write32(&dwc3->qusb_phy_pll->lock_delay, + QUSB2PHY_PLL_LOCK_DELAY); + write32(&dwc3->qusb_phy_pll->dig_tim, + QUSB2PHY_PLL_DIGITAL_TIMERS_TWO); + write32(&dwc3->qusb_phy_pll->bias_ctrl_1, + QUSB2PHY_PLL_BIAS_CONTROL_1); + write32(&dwc3->qusb_phy_pll->bias_ctrl_2, + QUSB2PHY_PLL_BIAS_CONTROL_2); + + tune_phy(dwc3, dwc3->qusb_phy_dig); + + /* PWR_CTRL1: Clear the power down bit to enable the PHY */ + clrbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&dwc3->qusb_phy_dig->debug_ctrl2, + DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); + + /* + * DEBUG_STAT5: wait for 160uS for PLL lock; + * vstatus[0] changes from 0 to 1. + */ + long lock_us = wait_us(160, read32(&dwc3->qusb_phy_dig->debug_stat5) & + VSTATUS_PLL_LOCK_STATUS_MASK); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QUSB PHY PLL LOCK fails\n"); + else + printk(BIOS_DEBUG, "QUSB PHY initialized and locked in %ldus\n", + lock_us); +} + +static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], + int num) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) + write32(t->address, t->val); +} + +static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3) +{ + /* power up USB3 PHY */ + write32(&dwc3->qmp_pcs_reg->pcs_power_down_control, 0x01); + + /* Serdes configuration */ + qcom_qmp_phy_configure(dwc3->serdes_tbl, dwc3->serdes_tbl_num); + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_configure(dwc3->tx_tbl, dwc3->tx_tbl_num); + qcom_qmp_phy_configure(dwc3->rx_tbl, dwc3->rx_tbl_num); + qcom_qmp_phy_configure(dwc3->pcs_tbl, dwc3->pcs_tbl_num); + + /* perform software reset of PCS/Serdes */ + write32(&dwc3->qmp_pcs_reg->pcs_sw_reset, 0x00); + /* start PCS/Serdes to operation mode */ + write32(&dwc3->qmp_pcs_reg->pcs_start_control, 0x03); + + /* + * Wait for PHY initialization to be done + * PCS_STATUS: wait for 1ms for PHY STATUS; + * SW can continuously check for PHYSTATUS = 1.b0. + */ + long lock_us = wait_us(1000, + !(read32(&dwc3->qmp_pcs_reg->pcs_ready_status) & + USB3_PCS_PHYSTATUS)); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QMP PHY PLL LOCK fails:\n"); + else + printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", + lock_us); +} + +static void setup_dwc3(struct usb_dwc3 *dwc3) +{ + /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ + clrsetbits_le32(&dwc3->usb3pipectl, + DWC3_GUSB3PIPECTL_DELAYP1TRANS, + DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); + + /* + * Configure USB phy interface of DWC3 core. + * 1. Select UTMI+ PHY with 16-bit interface. + * 2. Set USBTRDTIM to the corresponding value + * according to the UTMI+ PHY interface. + */ + clrsetbits_le32(&dwc3->usb2phycfg, + (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | + DWC3_GUSB2PHYCFG_PHYIF_MASK), + (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); + + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + DWC3_GCTL_DISSCRAMBLE), + DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); + + /* configure controller in Host mode */ + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); + printk(BIOS_SPEW, "Configure USB in Host mode\n"); +} + +/* Initialization of DWC3 Core and PHY */ +static void setup_usb_host(struct usb_dwc3_cfg *dwc3, + struct usb_board_data *board_data) +{ + dwc3->board_data = board_data; + + /* Clear core reset. */ + clock_reset_bcr(dwc3->usb3_bcr, 0); + + /* Clear QUSB PHY reset. */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 0); + + /* Initialize QUSB PHY */ + hs_qusb_phy_init(dwc3); + + /* Clear QMP PHY resets. */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 0); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 0); + + /* Initialize QMP PHY */ + ss_qmp_phy_init(dwc3); + + setup_dwc3(dwc3->usb_host_dwc3); + + printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); +} + +void setup_usb_host0(struct usb_board_data *board_data) +{ + printk(BIOS_INFO, "Setting up USB HOST0 controller.\n"); + setup_usb_host(&usb_port0, board_data); +} + + -- To view, visit https://review.coreboot.org/c/coreboot/+/35503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0651fc28dc227efbeb23eeefe9b96a3b940ae995 Gerrit-Change-Number: 35503 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: sc7180: Add AOP firmware support
by mturney mturney (Code Review) 05 Dec '19

05 Dec '19

Hello ashk(a)codeaurora.org, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35502 to review the following change. Change subject: sc7180: Add AOP firmware support ...................................................................... sc7180: Add AOP firmware support Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25210/85 Change-Id: I1cd552fbf03b5135e5911f1143f8778cad81e360 Signed-off-by: ashk <ashk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/aop_load_reset.c A src/soc/qualcomm/sc7180/include/soc/aop.h M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/mmu.c M src/soc/qualcomm/sc7180/soc.c 7 files changed, 89 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35502/1 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 7ad0328..d8fc33a 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -48,6 +48,7 @@ ramstage-y += qcom_qup_se.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c +ramstage-y += aop_load_reset.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c new file mode 100644 index 0000000..8d22d62 --- /dev/null +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/cache.h> +#include <cbfs.h> +#include <halt.h> +#include <console/console.h> +#include <timestamp.h> +#include <soc/mmu.h> +#include <soc/aop.h> +#include <soc/clock.h> + +void aop_fw_load_reset(void) +{ + bool aop_fw_entry; + + struct prog aop_fw_prog = + PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); + + if (prog_locate(&aop_fw_prog)) + die("SOC image: AOP_FW not found"); + + aop_fw_entry = selfload(&aop_fw_prog); + if (!aop_fw_entry) + die("SOC image: AOP load failed"); + + clock_reset_aop(); + + printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); +} diff --git a/src/soc/qualcomm/sc7180/include/soc/aop.h b/src/soc/qualcomm/sc7180/include/soc/aop.h new file mode 100644 index 0000000..5573163 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/aop.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_AOP_H__ +#define _SOC_QUALCOMM_SC7180_AOP_H__ + +void aop_fw_load_reset(void); + +#endif // _SOC_QUALCOMM_SC7180_AOP_H__ diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index ae00816..f4e6f05 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -24,8 +24,24 @@ #define BSRAM_START(addr) SYMBOL(bsram, addr) #define BSRAM_END(addr) SYMBOL(ebsram, addr) +/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) +#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) + +/* AOPMSG : 0x0C300000 - 0x0C400000 */ +#define AOPMSG_START(addr) SYMBOL(aopmsg, addr) +#define AOPMSG_END(addr) SYMBOL(eaopmsg, addr) + SECTIONS { + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + + AOPMSG_START(0x0C300000) + REGION(aop_ss_msg_ram_drv15, 0x0C3F0000, 0x400, 0x100) + AOPMSG_END(0x0C400000) + SSRAM_START(0x14680000) OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) REGION(qcsdi, 0x14699000, 52K, 4K) diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index 14b779f..893ecc3 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -26,5 +26,7 @@ DECLARE_REGION(dcb); DECLARE_REGION(pmic); DECLARE_REGION(limits_cfg); +DECLARE_REGION(aop); +DECLARE_REGION(aop_ss_msg_ram_drv15); #endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index fd59a5a..2eb8c86 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -33,3 +33,7 @@ mmu_enable(); } +void soc_mmu_dram_config_post_dram_init(void) +{ + mmu_config_range((void *)_aop, REGION_SIZE(aop), CACHED_RAM); +} diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 4fc5b30..7039935 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -18,6 +18,7 @@ #include <soc/mmu.h> #include <soc/mmu_common.h> #include <soc/symbols.h> +#include <soc/aop.h> static void soc_read_resources(struct device *dev) { @@ -34,7 +35,7 @@ static void soc_init(struct device *dev) { - + aop_fw_load_reset(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/35502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cd552fbf03b5135e5911f1143f8778cad81e360 Gerrit-Change-Number: 35502 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

4 9

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