coreboot-gerrit November 2019

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Change in coreboot[master]: lib/imd_cbmem: Rename imd_cbmem into imd, use directly
by Patrick Georgi (Code Review) 03 Dec '19

03 Dec '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37363 ) Change subject: lib/imd_cbmem: Rename imd_cbmem into imd, use directly ...................................................................... lib/imd_cbmem: Rename imd_cbmem into imd, use directly Change-Id: I70e9d9f769831087becbf42dcfb774d8f2638770 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/lib/imd_cbmem.c 1 file changed, 12 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/37363/1 diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index c3204e2..3dc9058 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -27,6 +27,8 @@ has to fill in the _cbmem_top_ptr symbol based on the calling arguments. */ uintptr_t _cbmem_top_ptr; +static struct imd imd; + void *cbmem_top(void) { if (ENV_ROMSTAGE) { @@ -42,9 +44,6 @@ dead_code(); } - -static struct imd imd_cbmem; - static inline const struct cbmem_entry *imd_to_cbmem(const struct imd_entry *e) { return (const struct cbmem_entry *)e; @@ -74,12 +73,11 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size) { - struct imd *imd = &imd_cbmem; const int no_recovery = 0; cbmem_top_init_once(); - imd_handle_init(imd, cbmem_top()); + imd_handle_init(&imd, cbmem_top()); printk(BIOS_DEBUG, "CBMEM:\n"); @@ -104,12 +102,11 @@ int cbmem_initialize_id_size(u32 id, u64 size) { - struct imd *imd = &imd_cbmem; const int recovery = 1; cbmem_top_init_once(); - imd_handle_init(imd, cbmem_top()); + imd_handle_init(&imd, cbmem_top()); if (imd_recover(imd)) return 1; @@ -145,20 +142,18 @@ const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64) { - struct imd *imd = &imd_cbmem; const struct imd_entry *e; - e = imd_entry_find_or_add(imd, id, size64); + e = imd_entry_find_or_add(&imd, id, size64); return imd_to_cbmem(e); } void *cbmem_add(u32 id, u64 size) { - struct imd *imd = &imd_cbmem; const struct imd_entry *e; - e = imd_entry_find_or_add(imd, id, size); + e = imd_entry_find_or_add(&imd, id, size); if (e == NULL) return NULL; @@ -169,20 +164,18 @@ /* Retrieve a region provided a given id. */ const struct cbmem_entry *cbmem_entry_find(u32 id) { - struct imd *imd = &imd_cbmem; const struct imd_entry *e; - e = imd_entry_find(imd, id); + e = imd_entry_find(&imd, id); return imd_to_cbmem(e); } void *cbmem_find(u32 id) { - struct imd *imd = &imd_cbmem; const struct imd_entry *e; - e = imd_entry_find(imd, id); + e = imd_entry_find(&imd, id); if (e == NULL) return NULL; @@ -194,23 +187,17 @@ * cannot be removed unless it was the last one added. */ int cbmem_entry_remove(const struct cbmem_entry *entry) { - struct imd *imd = &imd_cbmem; - - return imd_entry_remove(imd, cbmem_to_imd(entry)); + return imd_entry_remove(&imd, cbmem_to_imd(entry)); } u64 cbmem_entry_size(const struct cbmem_entry *entry) { - struct imd *imd = &imd_cbmem; - - return imd_entry_size(imd, cbmem_to_imd(entry)); + return imd_entry_size(&imd, cbmem_to_imd(entry)); } void *cbmem_entry_start(const struct cbmem_entry *entry) { - struct imd *imd = &imd_cbmem; - - return imd_entry_at(imd, cbmem_to_imd(entry)); + return imd_entry_at(&imd, cbmem_to_imd(entry)); } void cbmem_add_bootmem(void) @@ -237,9 +224,8 @@ void cbmem_list(void) { static const struct imd_lookup lookup[] = { CBMEM_ID_TO_NAME_TABLE }; - struct imd *imd = &imd_cbmem; - imd_print_entries(imd, lookup, ARRAY_SIZE(lookup)); + imd_print_entries(&imd, lookup, ARRAY_SIZE(lookup)); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70e9d9f769831087becbf42dcfb774d8f2638770 Gerrit-Change-Number: 37363 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/imd_cbmem: Remove the indirections that hide imd_cbmem
by Patrick Georgi (Code Review) 03 Dec '19

03 Dec '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37362 ) Change subject: lib/imd_cbmem: Remove the indirections that hide imd_cbmem ...................................................................... lib/imd_cbmem: Remove the indirections that hide imd_cbmem Change-Id: Ie68c6e2ebe56a5902a7665bf62119302146f5928 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/lib/imd_cbmem.c 1 file changed, 10 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/37362/1 diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 4172fa4..c3204e2 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -55,32 +55,6 @@ return (const struct imd_entry *)e; } -/* These are the different situations to handle: - * - * In ramstage cbmem_initialize() attempts a recovery of the - * cbmem region set up by romstage. It uses cbmem_top() as the - * starting point of recovery. - * - * In romstage, similar to ramstage, cbmem_initialize() needs to - * attempt recovery of the cbmem area using cbmem_top() as the limit. - * cbmem_initialize_empty() initializes an empty cbmem area from - * cbmem_top(); - * - */ -static struct imd *imd_init_backing(struct imd *backing) -{ - return &imd_cbmem; -} - -static struct imd *imd_init_backing_with_recover(struct imd *backing) -{ - struct imd *imd; - - imd = imd_init_backing(backing); - - return imd; -} - void cbmem_initialize_empty(void) { cbmem_initialize_empty_id_size(0, 0); @@ -100,13 +74,11 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const int no_recovery = 0; cbmem_top_init_once(); - imd = imd_init_backing(&imd_backing); imd_handle_init(imd, cbmem_top()); printk(BIOS_DEBUG, "CBMEM:\n"); @@ -132,13 +104,11 @@ int cbmem_initialize_id_size(u32 id, u64 size) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const int recovery = 1; cbmem_top_init_once(); - imd = imd_init_backing(&imd_backing); imd_handle_init(imd, cbmem_top()); if (imd_recover(imd)) @@ -175,12 +145,9 @@ const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const struct imd_entry *e; - imd = imd_init_backing_with_recover(&imd_backing); - e = imd_entry_find_or_add(imd, id, size64); return imd_to_cbmem(e); @@ -188,12 +155,9 @@ void *cbmem_add(u32 id, u64 size) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const struct imd_entry *e; - imd = imd_init_backing_with_recover(&imd_backing); - e = imd_entry_find_or_add(imd, id, size); if (e == NULL) @@ -205,12 +169,9 @@ /* Retrieve a region provided a given id. */ const struct cbmem_entry *cbmem_entry_find(u32 id) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const struct imd_entry *e; - imd = imd_init_backing_with_recover(&imd_backing); - e = imd_entry_find(imd, id); return imd_to_cbmem(e); @@ -218,12 +179,9 @@ void *cbmem_find(u32 id) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const struct imd_entry *e; - imd = imd_init_backing_with_recover(&imd_backing); - e = imd_entry_find(imd, id); if (e == NULL) @@ -236,30 +194,21 @@ * cannot be removed unless it was the last one added. */ int cbmem_entry_remove(const struct cbmem_entry *entry) { - struct imd *imd; - struct imd imd_backing; - - imd = imd_init_backing_with_recover(&imd_backing); + struct imd *imd = &imd_cbmem; return imd_entry_remove(imd, cbmem_to_imd(entry)); } u64 cbmem_entry_size(const struct cbmem_entry *entry) { - struct imd *imd; - struct imd imd_backing; - - imd = imd_init_backing_with_recover(&imd_backing); + struct imd *imd = &imd_cbmem; return imd_entry_size(imd, cbmem_to_imd(entry)); } void *cbmem_entry_start(const struct cbmem_entry *entry) { - struct imd *imd; - struct imd imd_backing; - - imd = imd_init_backing_with_recover(&imd_backing); + struct imd *imd = &imd_cbmem; return imd_entry_at(imd, cbmem_to_imd(entry)); } @@ -288,10 +237,8 @@ void cbmem_list(void) { static const struct imd_lookup lookup[] = { CBMEM_ID_TO_NAME_TABLE }; - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; - imd = imd_init_backing_with_recover(&imd_backing); imd_print_entries(imd, lookup, ARRAY_SIZE(lookup)); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie68c6e2ebe56a5902a7665bf62119302146f5928 Gerrit-Change-Number: 37362 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: lib/imd_cbmem: &imd_cbmem is never NULL, so remove that path
by Patrick Georgi (Code Review) 03 Dec '19

03 Dec '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37361 ) Change subject: lib/imd_cbmem: &imd_cbmem is never NULL, so remove that path ...................................................................... lib/imd_cbmem: &imd_cbmem is never NULL, so remove that path Change-Id: Ib9a9c88d6cd4842df447f046bc0abaa7ef5032c7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/lib/imd_cbmem.c 1 file changed, 1 insertion(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/37361/1 diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index d7f7d20..4172fa4 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -69,16 +69,7 @@ */ static struct imd *imd_init_backing(struct imd *backing) { - struct imd *imd; - - imd = &imd_cbmem; - - if (imd != NULL) - return imd; - - imd = backing; - - return imd; + return &imd_cbmem; } static struct imd *imd_init_backing_with_recover(struct imd *backing) -- To view, visit https://review.coreboot.org/c/coreboot/+/37361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a9c88d6cd4842df447f046bc0abaa7ef5032c7 Gerrit-Change-Number: 37361 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: hatch: Create stryke variant
by Dtrain Hsu (Code Review) 03 Dec '19

03 Dec '19

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37229 ) Change subject: hatch: Create stryke variant ...................................................................... hatch: Create stryke variant (Auto-Generated by create_coreboot_variant.sh version 1.0.0). BUG=b:145101696 TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_STRYKE Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Iea6f8a1c6c24a1e3545c364551cb623debdc4a1a --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/stryke/Makefile.inc A src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/stryke/include/variant/ec.h A src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h A src/mainboard/google/hatch/variants/stryke/overridetree.cb 7 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/37229/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index d6e6e46..8be340e 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -96,6 +96,7 @@ default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Puff" if BOARD_GOOGLE_PUFF + default "Stryke" if BOARD_GOOGLE_STRYKE config MAINBOARD_VENDOR string @@ -125,6 +126,7 @@ default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "puff" if BOARD_GOOGLE_PUFF + default "stryke" if BOARD_GOOGLE_STRYKE config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 82da883..ed90de6 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -50,3 +50,8 @@ select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 + +config BOARD_GOOGLE_STRYKE + bool "-> Stryke" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 diff --git a/src/mainboard/google/hatch/variants/stryke/Makefile.inc b/src/mainboard/google/hatch/variants/stryke/Makefile.inc new file mode 100644 index 0000000..38cf728 --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/Makefile.inc @@ -0,0 +1,13 @@ +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..496334d --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h b/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h new file mode 100644 index 0000000..2526962 --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h b/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h new file mode 100644 index 0000000..3b07c1b --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + +#endif diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb new file mode 100644 index 0000000..abbcaaa --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/cannonlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/37229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea6f8a1c6c24a1e3545c364551cb623debdc4a1a Gerrit-Change-Number: 37229 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: src: Add missing include <stdlib.h>
by HAOUAS Elyes (Code Review) 03 Dec '19

03 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37366 ) Change subject: src: Add missing include <stdlib.h> ...................................................................... src: Add missing include <stdlib.h> Also use <types.h> when <stdint.h> and <stddef.h> are needed. Also add some missing includes spotted by Jenkins. Change-Id: I17dc2fed6c6518daf5af286788c98c049088911e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/storage/bouncebuf.c M src/commonlib/storage/sdhci.c M src/commonlib/storage/sdhci_adma.c M src/device/oprom/yabel/vbe.c M src/lib/fit_payload.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/soc/amd/common/block/spi/fch_spi_flash.c M src/soc/intel/broadwell/me.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/smbios.c M src/soc/intel/quark/i2c.c M src/soc/intel/skylake/elog.c M src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c M src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c M src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c M src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c 18 files changed, 42 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/37366/1 diff --git a/src/commonlib/storage/bouncebuf.c b/src/commonlib/storage/bouncebuf.c index 99287b6..6244896 100644 --- a/src/commonlib/storage/bouncebuf.c +++ b/src/commonlib/storage/bouncebuf.c @@ -15,10 +15,13 @@ */ #include <arch/cache.h> +#include <commonlib/stdlib.h> +#include <stdlib.h> +#include <string.h> +#include <types.h> + #include "bouncebuf.h" #include "storage.h" -#include <string.h> -#include <commonlib/stdlib.h> static int addr_aligned(struct bounce_buffer *state) { diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 25c0d6f1e..25d0f2f 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -14,17 +14,20 @@ * Secure Digital (SD) Host Controller interface specific code */ -#include "bouncebuf.h" #include <commonlib/sd_mmc_ctrlr.h> #include <commonlib/sdhci.h> #include <commonlib/storage.h> #include <delay.h> #include <endian.h> +#include <timer.h> +#include <commonlib/stdlib.h> +#include <stdlib.h> +#include <types.h> + +#include "bouncebuf.h" #include "sdhci.h" #include "sd_mmc.h" #include "storage.h" -#include <timer.h> -#include <commonlib/stdlib.h> #define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \ || (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_VERSTAGE) \ diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index 2806bde..7738afb 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -19,6 +19,8 @@ #include <console/console.h> #include <delay.h> #include <endian.h> +#include <stdlib.h> +#include <stdint.h> #include <string.h> #include "sdhci.h" diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index a3d736f..7d1ea59 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -34,6 +34,7 @@ #include <boot/coreboot_tables.h> #include <string.h> +#include <stdlib.h> #include <types.h> #include <endian.h> diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 1b6c986..ccb84f4 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -19,12 +19,13 @@ #include <bootmem.h> #include <cbmem.h> #include <device/resource.h> -#include <stdlib.h> #include <commonlib/region.h> #include <fit.h> #include <program_loading.h> #include <timestamp.h> +#include <stdlib.h> #include <string.h> +#include <types.h> #include <commonlib/cbfs_serialized.h> #include <commonlib/compression.h> #include <lib.h> diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 580e09a..50123f9 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -12,6 +12,7 @@ */ #include <endian.h> +#include <stdlib.h> #include <string.h> #include <smbios.h> #include <console/console.h> diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 7f59d91..0deaff6 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -21,10 +21,12 @@ #include <cpu/x86/cache.h> #include <delay.h> #include <lib.h> +#include <spd.h> +#include <stdlib.h> +#include <string.h> + #include "pineview.h" #include "raminit.h" -#include <spd.h> -#include <string.h> /* Debugging macros. */ #if CONFIG(DEBUG_RAM_SETUP) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4974173..26338d6 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -23,6 +23,7 @@ #include <northbridge/intel/sandybridge/chip.h> #include <device/pci_def.h> #include <delay.h> +#include <stdlib.h> #include "raminit_native.h" #include "raminit_common.h" diff --git a/src/soc/amd/common/block/spi/fch_spi_flash.c b/src/soc/amd/common/block/spi/fch_spi_flash.c index 40dd0e2..5942e77 100644 --- a/src/soc/amd/common/block/spi/fch_spi_flash.c +++ b/src/soc/amd/common/block/spi/fch_spi_flash.c @@ -19,6 +19,7 @@ #include <amdblocks/fch_spi.h> #include <drivers/spi/spi_flash_internal.h> #include <timer.h> +#include <stdlib.h> #include <string.h> static void spi_flash_addr(u32 addr, u8 *cmd) diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 0021d2c..774f2bc 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -39,7 +39,7 @@ #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/intel/broadwell/chip.h> - +#include <stdlib.h> #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 0a43442..2f86940 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -19,8 +19,10 @@ #include <intelblocks/fast_spi.h> #include <soc/pci_devs.h> #include <spi_flash.h> +#include <stdlib.h> #include <string.h> #include <timer.h> +#include <types.h> /* Helper to create a FAST_SPI context on API entry. */ #define BOILERPLATE_CREATE_CTX(ctx) \ diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index d315e15..a468abb 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -13,11 +13,14 @@ * GNU General Public License for more details. */ -#include <smbios.h> -#include "smbios.h" -#include <string.h> #include <console/console.h> #include <device/dram/ddr3.h> +#include <smbios.h> +#include <stdlib.h> +#include <string.h> +#include <types.h> + +#include "smbios.h" /* Fill the SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.*/ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index b09852b..ad6418f 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -22,6 +22,8 @@ #include <soc/i2c.h> #include <soc/ramstage.h> #include <soc/reg_access.h> +#include <stdint.h> +#include <stdlib.h> #include <timer.h> static void i2c_disable(I2C_REGS *regs) diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 7951394..7871d7d 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -20,6 +20,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <stdint.h> +#include <stdlib.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <intelblocks/xhci.h> diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c index e078e74..cc6a5dd 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c @@ -12,6 +12,7 @@ #include <bdk.h> #include <libbdk-hal/bdk-config.h> +#include <stdlib.h> #include <string.h> #include <assert.h> #include <lame_string.h> diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c index b9552d4..810a0ed 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c @@ -37,7 +37,9 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include <bdk.h> +#include <stdlib.h> #include <string.h> + #include "libbdk-arch/bdk-csrs-gser.h" #include "libbdk-arch/bdk-csrs-gsern.h" #include "libbdk-hal/if/bdk-if.h" diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c index 0df70eb..ed003dc 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c @@ -36,8 +36,11 @@ * QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ + #include <bdk.h> #include <string.h> +#include <stdlib.h> + #include "libbdk-arch/bdk-csrs-ap.h" #include "libbdk-arch/bdk-csrs-pccpf.h" #include "libbdk-hal/bdk-ecam.h" diff --git a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c index 291fe85..445ada8 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c @@ -40,6 +40,7 @@ #include "dram-internal.h" #include <string.h> +#include <stdlib.h> #include <lame_string.h> /* for strtoul */ #include <libbdk-hal/bdk-atomic.h> #include <libbdk-hal/bdk-clock.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17dc2fed6c6518daf5af286788c98c049088911e Gerrit-Change-Number: 37366 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: soc/amd/stoneyidge: Use USE_AMD_BLOBS to remove default paths
by Marshall Dawson (Code Review) 03 Dec '19

03 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37220 ) Change subject: soc/amd/stoneyidge: Use USE_AMD_BLOBS to remove default paths ...................................................................... soc/amd/stoneyidge: Use USE_AMD_BLOBS to remove default paths Remove default path/to/file strings when USE_AMD_BLOBS is not enabled. This will result in a buildable, but not runable image, in the default configuration. Drop the check for HAVE_MERLINFALCON_BINARIES in the path default. A later patch will address the poor use of this symbol All PSP blobs are still assumed to be in the same directory as the AMD public key. Qualify building the amdfw.rom intermediate image and including it into coreboot.rom on whether the public key remains "". This change infers it's OK to skip xHCI and GEC firmware too, although the images normally reside in a separate directory. This change only determines whether default paths and names exist. Paths will be updated in a follow-on patch. Change-Id: Ic21fbd7a58b340a9bcaaea456e1f38b567215b81 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 20 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/37220/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b55833d..c477e03 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -176,7 +176,8 @@ config VGA_BIOS_FILE string - default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if AMD_APU_MERLINFALCON && HAVE_MERLINFALCON_BINARIES + default "" if !USE_AMD_BLOBS + default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if AMD_APU_MERLINFALCON default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" config S3_VGA_ROM_RUN @@ -216,6 +217,7 @@ config STONEYRIDGE_XHCI_FWM_FILE string "XHCI firmware path and filename" + default "" if !USE_AMD_BLOBS default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin" depends on STONEYRIDGE_XHCI_FWM @@ -225,7 +227,8 @@ config AMD_PUBKEY_FILE string "AMD public Key" - default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON && HAVE_MERLINFALCON_BINARIES + default "" if !USE_AMD_BLOBS + default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" config STONEYRIDGE_SATA_MODE diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index f697fc2..d2d64c8 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -137,20 +137,15 @@ ### 0 FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +ifneq ($(FIRMWARE_LOCATE),) ifeq ($(CONFIG_AMD_APU_STONEYRIDGE),y) FIRMWARE_TYPE=ST else - ifeq ($(CONFIG_AMD_APU_MERLINFALCON),y) -# If Merlin Falcon, but blobs aren't present, use Stoney Ridge instead -ifeq ($(CONFIG_HAVE_MERLINFALCON_BINARIES),y) FIRMWARE_TYPE=CZ else -FIRMWARE_TYPE=ST -endif # CONFIG_HAVE_MERLINFALCON_BINARIES -else -$(error stoneyridge: Unknown FIRMWARE_TYPE) +$(error soc/amd/stoneyridge: Unusable FIRMWARE_TYPE) endif # CONFIG_AMD_APU_MERLINFALCON endif # CONFIG_AMD_APU_STONEYRIDGE @@ -332,4 +327,17 @@ endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) +else # ifneq ($(FIRMWARE_LOCATE),) + +warn_no_amdfw: + printf "\n\t** WARNING **\n" + printf "coreboot has been built with no PSP firmware and " + printf "a non-booting image has been generated.\n\n" + +PHONY+=warn_no_amdfw + +files_added:: warn_no_amdfw + +endif # ifneq ($(FIRMWARE_LOCATE),) + endif # ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/37220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic21fbd7a58b340a9bcaaea456e1f38b567215b81 Gerrit-Change-Number: 37220 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 6

Change in em100[master]: Add compatibility mode
by Stefan Reinauer (Code Review) 03 Dec '19

03 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37258 ) Change subject: Add compatibility mode ...................................................................... Add compatibility mode Add a compatibility mode to the em100 tool. Right now coreboot and the Chrome OS build system carry a bunch of work-arounds to produce two sets of images, one for "real SPI chips" and one for use with the EM100Pro. Instead, we can (and should) just recognize these images and have the em100 tool handle them correctly during upload. em100 --compatibility ... does exactly that. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Ie02264facb028841d18ed84680ffa40f45987510 --- M Makefile M em100.c M em100.h A ifd.h A image.c 5 files changed, 251 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/58/37258/1 diff --git a/Makefile b/Makefile index 0b7c217..3bdb103 100644 --- a/Makefile +++ b/Makefile @@ -40,7 +40,7 @@ XZ = xz/xz_crc32.c xz/xz_crc64.c xz/xz_dec_bcj.c xz/xz_dec_lzma2.c xz/xz_dec_stream.c SOURCES = em100.c firmware.c fpga.c hexdump.c sdram.c spi.c system.c trace.c usb.c -SOURCES += curl.c chips.c tar.c $(XZ) +SOURCES += image.c curl.c chips.c tar.c $(XZ) OBJECTS = $(SOURCES:.c=.o) all: dep em100 diff --git a/em100.c b/em100.c index e52222b..abd8415 100644 --- a/em100.c +++ b/em100.c @@ -758,7 +758,8 @@ {"device", 1, 0, 'x'}, {"list-devices", 0, 0, 'l'}, {"update-files", 0, 0, 'U'}, - {"terminal",0 ,0, 'T'}, + {"terminal", 0, 0, 'T'}, + {"compatible", 0, 0, 'C'}, {NULL, 0, 0, 0} }; @@ -787,6 +788,7 @@ " -x|--device EMxxxxxx use EM100pro with serial no EMxxxxxx\n" " -l|--list-devices list all connected EM100pro devices\n" " -U|--update-files update device (chip) and firmware database\n" + " -C|--compatible enable compatibility mode (patch image for EM100Pro)\n" " -D|--debug: print debug information.\n" " -h|--help: this help text\n\n", name); @@ -802,7 +804,7 @@ const char *holdpin = NULL; int do_start = 0, do_stop = 0; int verify = 0, trace = 0, terminal=0; - int debug = 0; + int debug = 0, compatibility = 0; int bus = 0, device = 0; int firmware_is_dpfw = 0; unsigned int serial_number = 0; @@ -810,7 +812,7 @@ unsigned int spi_start_address = 0; const char *voltage = NULL; - while ((opt = getopt_long(argc, argv, "c:d:a:u:rsvtO:F:f:g:S:V:p:Dx:lUhT", + while ((opt = getopt_long(argc, argv, "c:d:a:u:rsvtO:F:f:g:S:V:p:DCx:lUhT", longopts, &idx)) != -1) { switch (opt) { case 'c': @@ -881,6 +883,9 @@ case 'U': update_all_files(); return 0; + case 'C': + compatibility = 1; + break; default: case 'h': usage(argv[0]); @@ -1074,6 +1079,9 @@ return 1; } + if (compatibility) + autocorrect_image(&em100, data, length); + if (spi_start_address) { readback = malloc(maxlen); if (readback == NULL) { diff --git a/em100.h b/em100.h index f0bacf2..448e6bb 100644 --- a/em100.h +++ b/em100.h @@ -196,9 +196,13 @@ #define MB * 1024 * 1024 #define FILENAME_BUFFER_SIZE 1024 +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) char *get_em100_file(const char *name); /* Chips */ int parse_dcfg(chipdesc *chip, TFILE *dcfg); +/* Images */ +int autocorrect_image(struct em100 *em100, char *image, size_t size); + #endif diff --git a/ifd.h b/ifd.h new file mode 100644 index 0000000..dac4edb --- /dev/null +++ b/ifd.h @@ -0,0 +1,50 @@ +/* + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +enum ifd_version { + IFD_VERSION_1, + IFD_VERSION_2, +}; + +enum platform { + PLATFORM_APL, + PLATFORM_CNL, + PLATFORM_GLK, + PLATFORM_ICL, + PLATFORM_SKLKBL, + PLATFORM_TGL, +}; + +enum spi_frequency { + SPI_FREQUENCY_20MHZ = 0, + SPI_FREQUENCY_33MHZ = 1, + SPI_FREQUENCY_48MHZ = 2, + SPI_FREQUENCY_50MHZ_30MHZ = 4, + SPI_FREQUENCY_17MHZ = 6, +}; + +/* flash descriptor */ +typedef struct { + uint32_t flvalsig; + uint32_t flmap0; + uint32_t flmap1; + uint32_t flmap2; +} __attribute__((packed)) fdbar_t; + +/* component section */ +typedef struct { + uint32_t flcomp; + uint32_t flill; + uint32_t flpb; +} __attribute__((packed)) fcba_t; + diff --git a/image.c b/image.c new file mode 100644 index 0000000..138436b --- /dev/null +++ b/image.c @@ -0,0 +1,185 @@ +/* + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include "em100.h" +#include "ifd.h" + +/** + * PTR_IN_RANGE - examine whether a pointer falls in [base, base + limit) + * @param ptr: the non-void* pointer to a single arbitrary-sized object. + * @param base: base address represented with char* type. + * @param limit: upper limit of the legal address. + * + */ +#define PTR_IN_RANGE(ptr, base, limit) \ + ((const char *)(ptr) >= (base) && \ + (const char *)&(ptr)[1] <= (base) + (limit)) + +static int ifd_version; +static int platform = -1; + +static fdbar_t *find_fd(char *image, int size) +{ + int i, found = 0; + + /* Scan for FD signature */ + for (i = 0; i < (size - 4); i += 4) { + if (*(uint32_t *) (image + i) == 0x0FF0A55A) { + found = 1; + break; // signature found. + } + } + + if (!found) { + printf("No Flash Descriptor found in this image\n"); + return NULL; + } + + fdbar_t *fdb = (fdbar_t *) (image + i); + return PTR_IN_RANGE(fdb, image, size) ? fdb : NULL; +} + +static fcba_t *find_fcba(char *image, int size) +{ + fdbar_t *fdb = find_fd(image, size); + if (!fdb) + return NULL; + fcba_t *fcba = (fcba_t *) (image + ((fdb->flmap0 & 0xff) << 4)); + return PTR_IN_RANGE(fcba, image, size) ? fcba : NULL; + +} + +/* + * Some newer platforms have re-defined the FCBA field that was used to + * distinguish IFD v1 v/s v2. Define a list of platforms that we know do not + * have the required FCBA field, but are IFD v2 and return true if current + * platform is one of them. + */ +static int is_platform_ifd_2(void) +{ + static const int ifd_2_platforms[] = { + PLATFORM_GLK, + PLATFORM_CNL, + PLATFORM_ICL, + PLATFORM_TGL, + }; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(ifd_2_platforms); i++) { + if (platform == ifd_2_platforms[i]) + return 1; + } + + return 0; +} + +/* + * There is no version field in the descriptor so to determine + * if this is a new descriptor format we check the hardcoded SPI + * read frequency to see if it is fixed at 20MHz or 17MHz. + */ +static int get_ifd_version_from_fcba(char *image, int size) +{ + int read_freq; + const fcba_t *fcba = find_fcba(image, size); + const fdbar_t *fdb = find_fd(image, size); + if (!fcba || !fdb) + exit(EXIT_FAILURE); + + read_freq = (fcba->flcomp >> 17) & 7; + + switch (read_freq) { + case SPI_FREQUENCY_20MHZ: + return IFD_VERSION_1; + case SPI_FREQUENCY_17MHZ: + case SPI_FREQUENCY_50MHZ_30MHZ: + return IFD_VERSION_2; + default: + fprintf(stderr, "Unknown descriptor version: %d\n", + read_freq); + exit(EXIT_FAILURE); + } +} + +static void check_ifd_version(char *image, int size) +{ + if (is_platform_ifd_2()) + ifd_version = IFD_VERSION_2; + else + ifd_version = get_ifd_version_from_fcba(image, size); +} + +static void set_spi_frequency(char *image, int size, enum spi_frequency freq) +{ + fcba_t *fcba = find_fcba(image, size); + if (!fcba) + exit(EXIT_FAILURE); + + /* clear bits 21-29 */ + fcba->flcomp &= ~0x3fe00000; + /* Read ID and Read Status Clock Frequency */ + fcba->flcomp |= freq << 27; + /* Write and Erase Clock Frequency */ + fcba->flcomp |= freq << 24; + /* Fast Read Clock Frequency */ + fcba->flcomp |= freq << 21; +} + +static void set_em100_mode(struct em100 *em100, char *image, int size) +{ + fcba_t *fcba = find_fcba(image, size); + if (!fcba) + exit(EXIT_FAILURE); + + int freq; + + if (em100->hwversion == 6) { + printf("EM100Pro-G2 can run at full speed.\n"); + return; + } + + switch (ifd_version) { + case IFD_VERSION_1: + freq = SPI_FREQUENCY_20MHZ; + break; + case IFD_VERSION_2: + freq = SPI_FREQUENCY_17MHZ; + break; + default: + freq = SPI_FREQUENCY_17MHZ; + break; + } + + fcba->flcomp &= ~(1 << 30); + set_spi_frequency(image, size, freq); +} + +int autocorrect_image(struct em100 *em100, char *image, size_t size) +{ + printf("Auto-detecting IFD image ... "); + if (find_fd(image, size)) + printf("OK\n"); + else + return 1; /* No support for other image types (yet). */ + + /* Auto-detect IFD version */ + check_ifd_version(image, size); + + /* Set EM100 mode */ + set_em100_mode(em100, image, size); + + return 0; +} -- To view, visit https://review.coreboot.org/c/em100/+/37258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ie02264facb028841d18ed84680ffa40f45987510 Gerrit-Change-Number: 37258 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: mb/g/drallion: Enable privacy screen on Drallion variant
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36045 ) Change subject: mb/g/drallion: Enable privacy screen on Drallion variant ...................................................................... mb/g/drallion: Enable privacy screen on Drallion variant Enable ACPI methods to control privacy screen on Drallion devices. Drallion devices may not have a privacy screen and it is up to the EC to determine if the privacy screen is present on the system. BUG=b:142656363 TEST=emerge-drallion coreboot chromeos-bootimage Change-Id: I79d02bb1b25f0deb49ae4bb852b7ed8c21fd31c7 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/include/variant/ec.h 4 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/36045/1 diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 256f8cb..1de5ea5 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_GFX if BOARD_GOOGLE_DRALLION select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_ISH diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 2568800..5c2a5c9 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -39,6 +39,7 @@ { #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> + #include <soc/intel/cannonlake/acpi/gfx.asl> } /* Per board variant mainboard hooks. */ #include <variant/acpi/mainboard.asl> diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 1f628d6..184ab63 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -222,7 +222,19 @@ end device domain 0 on device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device + device pci 02.0 on + chip drivers/generic/gfx + register "device_count" = "1" + register "device[0].name" = ""LCD"" + register "device[0].addr" = "0x0400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.detect_function" = ""\\_SB.PCI0.LPCB.EC0.GPVD"" + register "device[0].privacy.status_function" = ""\\_SB.PCI0.LPCB.EC0.GPVX"" + register "device[0].privacy.enable_function" = ""\\_SB.PCI0.LPCB.EC0.EPVX"" + register "device[0].privacy.disable_function" = ""\\_SB.PCI0.LPCB.EC0.DPVX"" + device generic 0 on end + end + end # Integrated Graphics Device device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h index 01a17b5..9cb8ed0 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h @@ -31,4 +31,7 @@ /* Enable DPTF */ #define EC_ENABLE_DPTF +/* Enable Privacy */ +#define EC_ENABLE_PRIVACY + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79d02bb1b25f0deb49ae4bb852b7ed8c21fd31c7 Gerrit-Change-Number: 36045 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

4 17

Change in coreboot[master]: ec/google/wilco: Add placeholder methods for privacy screen
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36044 ) Change subject: ec/google/wilco: Add placeholder methods for privacy screen ...................................................................... ec/google/wilco: Add placeholder methods for privacy screen Add placeholder ACPI methods to the Wilco EC for controlling a privacy screen on the device. These methods will be updteded when the EC has commands to control the screen. BUG=b:142237145, b:142656363 TEST=none Change-Id: Ic3c136f9d2de90eeb3c9e468e4c7430ccf6dcc42 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/ec/google/wilco/acpi/ec.asl A src/ec/google/wilco/acpi/privacy.asl 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/36044/1 diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 532f421..8fcd0dd 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -178,4 +178,7 @@ #ifdef EC_ENABLE_DPTF #include "dptf.asl" #endif +#ifdef EC_ENABLE_PRIVACY + #include "privacy.asl" +#endif } diff --git a/src/ec/google/wilco/acpi/privacy.asl b/src/ec/google/wilco/acpi/privacy.asl new file mode 100644 index 0000000..2121d23 --- /dev/null +++ b/src/ec/google/wilco/acpi/privacy.asl @@ -0,0 +1,25 @@ +/* Read Privacy Screen Present */ +Method (GPVD, 0, Serialized) +{ + Printf ("Read Privacy Screen Present") + Return (One) +} + +/* Read Privacy Screen Status */ +Method (GPVX, 0, Serialized) +{ + Printf ("Read Privacy Screen Status") + Return (0x0) +} + +/* Enable Privacy Screen */ +Method (EPVX, 0, Serialized) +{ + Printf ("Enable Privacy Screen") +} + +/* Disable Privacy Screen */ +Method (DPVX, 0, Serialized) +{ + Printf ("Disable Privacy Screen") +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/36044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3c136f9d2de90eeb3c9e468e4c7430ccf6dcc42 Gerrit-Change-Number: 36044 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: soc/intel/cannonlake: Add gfx.asl file
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36043 ) Change subject: soc/intel/cannonlake: Add gfx.asl file ...................................................................... soc/intel/cannonlake: Add gfx.asl file Add gfx.asl file for cannonlake SOCs to allow for graphics related ACPI devices and methods on cannonlake devices. BUG=b:142237145 TEST=gfx.asl added to drallion dsdt.asl Change-Id: I38a26f3135d571e2f9b63840d38fd4d3476fc142 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- A src/soc/intel/cannonlake/acpi/gfx.asl 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/36043/1 diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/soc/intel/cannonlake/acpi/gfx.asl new file mode 100644 index 0000000..fef28f0 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/gfx.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/36043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38a26f3135d571e2f9b63840d38fd4d3476fc142 Gerrit-Change-Number: 36043 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 14

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coreboot-gerrit November 2019