coreboot-gerrit November 2019

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Change in coreboot[master]: mb/google/poppy: Rework OV5670 power on sequence
by Sakari Ailus (Code Review) 02 Dec '19

02 Dec '19

Sakari Ailus has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36723 ) Change subject: mb/google/poppy: Rework OV5670 power on sequence ...................................................................... mb/google/poppy: Rework OV5670 power on sequence In particular: - Enable regulators *after* configuring the voltage - Allow 1 ms for the voltages to settle - Enable clock after powering on regulators - Remove extra delays between enabling things. The sensor requires 8192 clock cycles after the reset is lifted before I²C access, so 1 ms is enough. - Make the delay after lifting xshutdown 10 ms. This guarantees that streaming will only start once the sensor has had enough time to settle after lifting the reset. Signed-off-by: Sakari Ailus <sakari.ailus(a)linux.intel.com> Tested-by: Jacopo Mondi <jacopo(a)jmondi.org> Change-Id: I4589a7d7ec324f4520572a406cc11ad3feec8b21 --- M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl 1 file changed, 22 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36723/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 12c3c22..355b255 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -526,30 +526,39 @@ daisy chain */ DOVD(1) - VAX2 = 1 /* Enable VAUX2 */ - if (LNotEqual (AX2V, 52)) { /* Set VAUX2 as 1.8006 V */ AX2V = 52 } + VAX2 = 1 /* Enable VAUX2 */ + + \_SB.PCI0.I2C2.PMIC.CGP4(1) + + /* + * Wait for DOVDD and AVDD + * to settle. + */ + Sleep(1) + + if (LNotEqual (AX1V, 19)) { + /* Set VAUX1 as 1.2132V */ + AX1V = 19 + } + VAX1 = 1 /* Enable VAUX1 */ + + /* Wait for VDD to settle. */ Sleep(1) \_SB.PCI0.I2C2.PMIC.CLKE() CLE1 = 1 - VAX1 = 1 /* Enable VAUX1 */ - if (LNotEqual (AX1V, 19)) { - /* Set VAUX1 as 1.2132V */ - AX1V = 19 - } - Sleep(3) - - \_SB.PCI0.I2C2.PMIC.CGP4(1) - Sleep(3) - \_SB.PCI0.I2C2.PMIC.CGP5(1) - Sleep(3) + /* + * Ensure 10 ms between + * power-up and streamon. + */ + Sleep(10) STA = 1 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/36723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4589a7d7ec324f4520572a406cc11ad3feec8b21 Gerrit-Change-Number: 36723 Gerrit-PatchSet: 1 Gerrit-Owner: Sakari Ailus <sakari.ailus+coreboot.org(a)linux.intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/poppy: Power on PMIC before accessing its opregion
by Sakari Ailus (Code Review) 02 Dec '19

02 Dec '19

Sakari Ailus has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36722 ) Change subject: mb/google/poppy: Power on PMIC before accessing its opregion ...................................................................... mb/google/poppy: Power on PMIC before accessing its opregion The PMIC opregion is used to change the direction of two GPIOs for I²C daisy chain operation. Do this after the PMIC is powered on, not before. Reported-by: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> Signed-off-by: Sakari Ailus <sakari.ailus(a)linux.intel.com> Tested-by: Jacopo Mondi <jacopo(a)jmondi.org> Change-Id: I923987ef21a971df9e32ca03f2da4dccdac07843 --- M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/36722/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index d3fafe9..12c3c22 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -458,16 +458,16 @@ /* TODO: Read Voltage and Sleep values from Sensor Obj */ If (LEqual (AVBL, 1)) { If (LEqual (STA, 0)) { + /* Enable VSIO regulator + + daisy chain */ + DOVD(1) + If (LEqual (C0GP, 0)) { \_SB.PCI0.I2C2.PMIC.CGP1() \_SB.PCI0.I2C2.PMIC.CGP2() C0GP = 1 } - /* Enable VSIO regulator + - daisy chain */ - DOVD(1) - VACT = 1 if (LNotEqual (ACVA, 109)) { /* Set ANA at 2.8152V */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923987ef21a971df9e32ca03f2da4dccdac07843 Gerrit-Change-Number: 36722 Gerrit-PatchSet: 1 Gerrit-Owner: Sakari Ailus <sakari.ailus+coreboot.org(a)linux.intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/poppy: Declare output GPIOs as pull-downs
by Sakari Ailus (Code Review) 02 Dec '19

02 Dec '19

Sakari Ailus has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36721 ) Change subject: mb/google/poppy: Declare output GPIOs as pull-downs ...................................................................... mb/google/poppy: Declare output GPIOs as pull-downs The pull direction is used to determine the initial state of the pin. If no pull direction is specified, the pin will remain as input. Fix this. Signed-off-by: Sakari Ailus <sakari.ailus(a)linux.intel.com> Tested-by: Jacopo Mondi <jacopo(a)jmondi.org> Change-Id: I1158bc8aaa447b223e8ce25d808348e758de28c5 --- M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/36721/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 5eaf5b7..d3fafe9 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -142,21 +142,21 @@ 2 } /* GPIO.4 is AVDD pin for user facing camera */ - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + GpioIo (Exclusive, PullDown, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", 0x00, ResourceConsumer,,) { 4 } /* GPIO.5 is XSHUTDOWN pin for user facing camera */ - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + GpioIo (Exclusive, PullDown, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", 0x00, ResourceConsumer,,) { 5 } /* GPIO.9 is XSHUTDOWN pin for world facing camera */ - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + GpioIo (Exclusive, PullDown, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", 0x00, ResourceConsumer,,) { @@ -188,7 +188,7 @@ GPO2, 1, Connection ( - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + GpioIo (Exclusive, PullDown, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", 0x00, ResourceConsumer,,) @@ -199,7 +199,7 @@ GRST, 1, Connection ( - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + GpioIo (Exclusive, PullDown, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", 0x00, ResourceConsumer,,) @@ -210,7 +210,7 @@ GPO4, 1, Connection ( - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + GpioIo (Exclusive, PullDown, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", 0x00, ResourceConsumer,,) -- To view, visit https://review.coreboot.org/c/coreboot/+/36721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1158bc8aaa447b223e8ce25d808348e758de28c5 Gerrit-Change-Number: 36721 Gerrit-PatchSet: 1 Gerrit-Owner: Sakari Ailus <sakari.ailus+coreboot.org(a)linux.intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] soc/amd/common: Inline ACPI MMIO accessors
by Kyösti Mälkki (Code Review) 02 Dec '19

02 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37211 ) Change subject: [WIP] soc/amd/common: Inline ACPI MMIO accessors ...................................................................... [WIP] soc/amd/common: Inline ACPI MMIO accessors TBD: Verify better code density from assembly. Change-Id: If2c37c9886a0151183aa6dd80eb068d6c67b3848 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h 2 files changed, 321 insertions(+), 433 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37211/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index f844ea4..7a4e606 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -14,8 +14,6 @@ */ #include <types.h> -#include <arch/io.h> -#include <device/mmio.h> #include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h> @@ -27,337 +25,3 @@ dw |= ACPIMMIO_DECODE_EN; pm_io_write32(ACPIMMIO_DECODE_REGISTER, dw); } - -/* PM registers are accessed a byte at a time via CD6/CD7 */ -uint8_t pm_io_read8(uint8_t reg) -{ - outb(reg, PM_INDEX); - return inb(PM_DATA); -} - -uint16_t pm_io_read16(uint8_t reg) -{ - return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg); -} - -uint32_t pm_io_read32(uint8_t reg) -{ - return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg); -} - -void pm_io_write8(uint8_t reg, uint8_t value) -{ - outb(reg, PM_INDEX); - outb(value, PM_DATA); -} - -void pm_io_write16(uint8_t reg, uint16_t value) -{ - pm_io_write8(reg, value & 0xff); - value >>= 8; - pm_io_write8(reg + sizeof(uint8_t), value & 0xff); -} - -void pm_io_write32(uint8_t reg, uint32_t value) -{ - pm_io_write16(reg, value & 0xffff); - value >>= 16; - pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); -} - -/* smbus pci read/write - access registers at 0xfed80000 */ - -u8 sm_pci_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); -} - -u16 sm_pci_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg)); -} - -u32 sm_pci_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg)); -} - -void sm_pci_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); -} - -void sm_pci_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); -} - -void sm_pci_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); -} - -uint8_t smi_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_SMI_BASE + reg)); -} - -uint16_t smi_read16(uint8_t reg) -{ - return read16((void *)(ACPIMMIO_SMI_BASE + reg)); -} - -uint32_t smi_read32(uint8_t reg) -{ - return read32((void *)(ACPIMMIO_SMI_BASE + reg)); -} - -void smi_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_SMI_BASE + reg), value); -} - -void smi_write16(uint8_t reg, uint16_t value) -{ - write16((void *)(ACPIMMIO_SMI_BASE + reg), value); -} - -void smi_write32(uint8_t reg, uint32_t value) -{ - write32((void *)(ACPIMMIO_SMI_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -u16 pm_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -u32 pm_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -void pm_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -void pm_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -uint8_t biosram_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); -} - -uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */ -{ - return (biosram_read8(reg + sizeof(uint8_t)) << 8 | biosram_read8(reg)); -} - -uint32_t biosram_read32(uint8_t reg) -{ - uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16; - return value | biosram_read16(reg); -} - -void biosram_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); -} - -void biosram_write16(uint8_t reg, uint16_t value) -{ - biosram_write8(reg, value & 0xff); - value >>= 8; - biosram_write8(reg + sizeof(uint8_t), value & 0xff); -} - -void biosram_write32(uint8_t reg, uint32_t value) -{ - biosram_write16(reg, value & 0xffff); - value >>= 16; - biosram_write16(reg + sizeof(uint16_t), value & 0xffff); -} - -u8 acpi_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -u16 acpi_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -u32 acpi_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -void acpi_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -void acpi_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -void acpi_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -u8 asf_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_ASF_BASE + reg)); -} - -u16 asf_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_ASF_BASE + reg)); -} - -void asf_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_ASF_BASE + reg), value); -} - -void asf_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_ASF_BASE + reg), value); -} - -u8 smbus_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); -} - -u16 smbus_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); -} - -void smbus_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); -} - -void smbus_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); -} - -u8 iomux_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -u16 iomux_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -u32 iomux_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -void iomux_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -void iomux_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -void iomux_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -u8 misc_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -u16 misc_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -u32 misc_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -void misc_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -void misc_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -void misc_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -uint8_t xhci_pm_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -uint16_t xhci_pm_read16(uint8_t reg) -{ - return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -uint32_t xhci_pm_read32(uint8_t reg) -{ - return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -void xhci_pm_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -void xhci_pm_write16(uint8_t reg, uint16_t value) -{ - write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -void xhci_pm_write32(uint8_t reg, uint32_t value) -{ - write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -u8 aoac_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); -} - -void aoac_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); -} diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index b395cdb..53d1f043 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -18,7 +18,11 @@ #ifndef __AMDBLOCKS_ACPIMMIO_H__ #define __AMDBLOCKS_ACPIMMIO_H__ +#include <arch/io.h> +#include <device/mmio.h> #include <stdint.h> +#include <types.h> +#include <amdblocks/acpimmio_map.h> /* * The following AcpiMmio register block mapping represents definitions @@ -100,116 +104,336 @@ /* Enable the AcpiMmio range at 0xfed80000 */ void enable_acpimmio_decode(void); -/* Access SMBus PCI registers at 0xfed80000 */ -uint8_t sm_pci_read8(uint8_t reg); -uint16_t sm_pci_read16(uint8_t reg); -uint32_t sm_pci_read32(uint8_t reg); -void sm_pci_write8(uint8_t reg, uint8_t value); -void sm_pci_write16(uint8_t reg, uint16_t value); -void sm_pci_write32(uint8_t reg, uint32_t value); +/* PM registers are accessed a byte at a time via CD6/CD7 */ +static inline uint8_t pm_io_read8(uint8_t reg) +{ + outb(reg, PM_INDEX); + return inb(PM_DATA); +} -/* Access PM registers using IO cycles */ -uint8_t pm_io_read8(uint8_t reg); -uint16_t pm_io_read16(uint8_t reg); -uint32_t pm_io_read32(uint8_t reg); -void pm_io_write8(uint8_t reg, uint8_t value); -void pm_io_write16(uint8_t reg, uint16_t value); -void pm_io_write32(uint8_t reg, uint32_t value); +static inline uint16_t pm_io_read16(uint8_t reg) +{ + return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg); +} -/* Access SMI registers at 0xfed80100 */ -uint8_t smi_read8(uint8_t reg); -uint16_t smi_read16(uint8_t reg); -uint32_t smi_read32(uint8_t reg); -void smi_write8(uint8_t reg, uint8_t value); -void smi_write16(uint8_t reg, uint16_t value); -void smi_write32(uint8_t reg, uint32_t value); +static inline uint32_t pm_io_read32(uint8_t reg) +{ + return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg); +} -/* Access Power Management registers at 0xfed80300 */ -uint8_t pm_read8(uint8_t reg); -uint16_t pm_read16(uint8_t reg); -uint32_t pm_read32(uint8_t reg); -void pm_write8(uint8_t reg, uint8_t value); -void pm_write16(uint8_t reg, uint16_t value); -void pm_write32(uint8_t reg, uint32_t value); +static inline void pm_io_write8(uint8_t reg, uint8_t value) +{ + outb(reg, PM_INDEX); + outb(value, PM_DATA); +} -/* Access Power Management 2 registers at 0xfed80400 */ -uint8_t pm2_read8(uint8_t reg); -uint16_t pm2_read16(uint8_t reg); -uint32_t pm2_read32(uint8_t reg); -void pm2_write8(uint8_t reg, uint8_t value); -void pm2_write16(uint8_t reg, uint16_t value); -void pm2_write32(uint8_t reg, uint32_t value); +static inline void pm_io_write16(uint8_t reg, uint16_t value) +{ + pm_io_write8(reg, value & 0xff); + value >>= 8; + pm_io_write8(reg + sizeof(uint8_t), value & 0xff); +} -/* Access BIOS RAM storage at 0xfed80500 */ -uint8_t biosram_read8(uint8_t reg); -uint16_t biosram_read16(uint8_t reg); -uint32_t biosram_read32(uint8_t reg); -void biosram_write8(uint8_t reg, uint8_t value); -void biosram_write16(uint8_t reg, uint16_t value); -void biosram_write32(uint8_t reg, uint32_t value); +static inline void pm_io_write32(uint8_t reg, uint32_t value) +{ + pm_io_write16(reg, value & 0xffff); + value >>= 16; + pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); +} -/* Access ACPI registers at 0xfed80800 */ -uint8_t acpi_read8(uint8_t reg); -uint16_t acpi_read16(uint8_t reg); -uint32_t acpi_read32(uint8_t reg); -void acpi_write8(uint8_t reg, uint8_t value); -void acpi_write16(uint8_t reg, uint16_t value); -void acpi_write32(uint8_t reg, uint32_t value); +static inline uint8_t sm_pci_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} -/* Access ASF controller registers at 0xfed80900 */ -uint8_t asf_read8(uint8_t reg); -uint16_t asf_read16(uint8_t reg); -void asf_write8(uint8_t reg, uint8_t value); -void asf_write16(uint8_t reg, uint16_t value); +static inline uint16_t sm_pci_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} -/* Access SMBus controller registers at 0xfed80a00 */ -uint8_t smbus_read8(uint8_t reg); -uint16_t smbus_read16(uint8_t reg); -void smbus_write8(uint8_t reg, uint8_t value); -void smbus_write16(uint8_t reg, uint16_t value); +static inline uint32_t sm_pci_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} -/* Access WDT registers at 0xfed80b00 */ -uint8_t wdt_read8(uint8_t reg); -uint16_t wdt_read16(uint8_t reg); -uint32_t wdt_read32(uint8_t reg); -void wdt_write8(uint8_t reg, uint8_t value); -void wdt_write16(uint8_t reg, uint16_t value); -void wdt_write32(uint8_t reg, uint32_t value); +static inline void sm_pci_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} -/* Access HPET registers at 0xfed80c00 */ -uint8_t hpet_read8(uint8_t reg); -uint16_t hpet_read16(uint8_t reg); -uint32_t hpet_read32(uint8_t reg); -void hpet_write8(uint8_t reg, uint8_t value); -void hpet_write16(uint8_t reg, uint16_t value); -void hpet_write32(uint8_t reg, uint32_t value); +static inline void sm_pci_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} -/* Access GPIO MUX registers at 0xfed80d00 */ -uint8_t iomux_read8(uint8_t reg); -uint16_t iomux_read16(uint8_t reg); -uint32_t iomux_read32(uint8_t reg); -void iomux_write8(uint8_t reg, uint8_t value); -void iomux_write16(uint8_t reg, uint16_t value); -void iomux_write32(uint8_t reg, uint32_t value); +static inline void sm_pci_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} -/* Access Miscellaneous registers at 0xfed80e00 */ -uint8_t misc_read8(uint8_t reg); -uint16_t misc_read16(uint8_t reg); -uint32_t misc_read32(uint8_t reg); -void misc_write8(uint8_t reg, uint8_t value); -void misc_write16(uint8_t reg, uint16_t value); -void misc_write32(uint8_t reg, uint32_t value); +static inline uint8_t smi_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_SMI_BASE + reg)); +} -/* Access xHCI Power Management registers at 0xfed81c00 */ -uint8_t xhci_pm_read8(uint8_t reg); -uint16_t xhci_pm_read16(uint8_t reg); -uint32_t xhci_pm_read32(uint8_t reg); -void xhci_pm_write8(uint8_t reg, uint8_t value); -void xhci_pm_write16(uint8_t reg, uint16_t value); -void xhci_pm_write32(uint8_t reg, uint32_t value); +static inline uint16_t smi_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_SMI_BASE + reg)); +} -/* Access Always On Always Connect registers at 0xfed81e00 */ -uint8_t aoac_read8(uint8_t reg); -void aoac_write8(uint8_t reg, uint8_t value); +static inline uint32_t smi_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_SMI_BASE + reg)); +} + +static inline void smi_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_SMI_BASE + reg), value); +} + +static inline void smi_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_SMI_BASE + reg), value); +} + +static inline void smi_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_SMI_BASE + reg), value); +} + +static inline uint8_t pm_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +static inline uint16_t pm_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +static inline uint32_t pm_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +static inline void pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +static inline void pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +static inline void pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +static inline uint8_t biosram_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); +} + +static inline uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */ +{ + return (biosram_read8(reg + sizeof(uint8_t)) << 8 | biosram_read8(reg)); +} + +static inline uint32_t biosram_read32(uint8_t reg) +{ + uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16; + return value | biosram_read16(reg); +} + +static inline void biosram_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); +} + +static inline void biosram_write16(uint8_t reg, uint16_t value) +{ + biosram_write8(reg, value & 0xff); + value >>= 8; + biosram_write8(reg + sizeof(uint8_t), value & 0xff); +} + +static inline void biosram_write32(uint8_t reg, uint32_t value) +{ + biosram_write16(reg, value & 0xffff); + value >>= 16; + biosram_write16(reg + sizeof(uint16_t), value & 0xffff); +} + +static inline uint8_t acpi_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +static inline uint16_t acpi_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +static inline uint32_t acpi_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +static inline void acpi_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +static inline void acpi_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +static inline void acpi_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +static inline uint8_t asf_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +static inline uint16_t asf_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +static inline void asf_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +static inline void asf_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +static inline uint8_t smbus_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +static inline uint16_t smbus_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +static inline void smbus_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +static inline void smbus_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +static inline uint8_t iomux_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +static inline uint16_t iomux_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +static inline uint32_t iomux_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +static inline void iomux_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +static inline void iomux_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +static inline void iomux_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +static inline uint8_t misc_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +static inline uint16_t misc_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +static inline uint32_t misc_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +static inline void misc_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +static inline void misc_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +static inline void misc_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +static inline uint8_t xhci_pm_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +static inline uint16_t xhci_pm_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +static inline uint32_t xhci_pm_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +static inline void xhci_pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +static inline void xhci_pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +static inline void xhci_pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +static inline uint8_t aoac_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); +} + +static inline void aoac_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); +} #endif /* __AMDBLOCKS_ACPIMMIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2c37c9886a0151183aa6dd80eb068d6c67b3848 Gerrit-Change-Number: 37211 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [TEST ONLY] Jenkins buildtest CONFIG_USE_CANNONLAKE_FSP_CAR
by PraveenX Hodagatta Pranesh (Code Review) 02 Dec '19

02 Dec '19

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37275 ) Change subject: [TEST ONLY] Jenkins buildtest CONFIG_USE_CANNONLAKE_FSP_CAR ...................................................................... [TEST ONLY] Jenkins buildtest CONFIG_USE_CANNONLAKE_FSP_CAR Change-Id: I004fc02bd84b7b8d5c5fb96451e59f143f0fe6d3 Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> --- A configs/config.test 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/37275/1 diff --git a/configs/config.test b/configs/config.test new file mode 100644 index 0000000..23ddc26 --- /dev/null +++ b/configs/config.test @@ -0,0 +1 @@ +CONFIG_USE_CANNONLAKE_FSP_CAR=y -- To view, visit https://review.coreboot.org/c/coreboot/+/37275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I004fc02bd84b7b8d5c5fb96451e59f143f0fe6d3 Gerrit-Change-Number: 37275 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/cannonlake: Fix compilation
by PraveenX Hodagatta Pranesh (Code Review) 02 Dec '19

02 Dec '19

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37265 ) Change subject: soc/intel/cannonlake: Fix compilation ...................................................................... soc/intel/cannonlake: Fix compilation change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h. TEST= Build and boot test on coffeelake RVP. Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/bootblock.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37265/1 diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 9f85397..6a6dd8b 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -39,10 +39,10 @@ * All SoC since Gen-4 has above mechanism in place to load microcode * even before hitting CPU reset vector. Hence skipping FSP-T loading * microcode after CPU reset by passing '0' value to - * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize. */ .MicrocodeRegionBase = 0, - .MicrocodeRegionLength = 0, + .MicrocodeRegionSize = 0, .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, -- To view, visit https://review.coreboot.org/c/coreboot/+/37265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Gerrit-Change-Number: 37265 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: mb/google/hatch/variants/helios: DPTF solution update
by Kane Chen (Code Review) 02 Dec '19

02 Dec '19

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37272 ) Change subject: mb/google/hatch/variants/helios: DPTF solution update ...................................................................... mb/google/hatch/variants/helios: DPTF solution update Modify DPTF parameters. BUG=b:131272830 BRANCH=firmware-hatch-12672.B TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I93930525edf4c5efb6b73bdfc8f16950754f7c9a --- M src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl 1 file changed, 7 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/37272/1 diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index 20a61d7..bcc9715 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -25,9 +25,9 @@ #define DPTF_TSR1_SENSOR_NAME "5V Regulator" #define DPTF_TSR1_PASSIVE 0 #define DPTF_TSR1_CRITICAL 70 -#define DPTF_TSR1_ACTIVE_AC0 43 -#define DPTF_TSR1_ACTIVE_AC1 40 -#define DPTF_TSR1_ACTIVE_AC2 38 +#define DPTF_TSR1_ACTIVE_AC0 42 +#define DPTF_TSR1_ACTIVE_AC1 41 +#define DPTF_TSR1_ACTIVE_AC2 39 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Ambient" @@ -36,14 +36,8 @@ #define DPTF_TSR3_SENSOR_ID 3 #define DPTF_TSR3_SENSOR_NAME "CPU" -#define DPTF_TSR3_PASSIVE 90 -#define DPTF_TSR3_CRITICAL 105 -#define DPTF_TSR3_ACTIVE_AC0 87 -#define DPTF_TSR3_ACTIVE_AC1 85 -#define DPTF_TSR3_ACTIVE_AC2 83 -#define DPTF_TSR3_ACTIVE_AC3 80 -#define DPTF_TSR3_ACTIVE_AC4 78 -#define DPTF_TSR3_ACTIVE_AC5 75 +#define DPTF_TSR3_PASSIVE 85 +#define DPTF_TSR3_CRITICAL 90 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -91,7 +85,7 @@ 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 100, 80, 60, 0, 0, 0, 0, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 70, 50, 0, 0, 0, 0, 0, 0, 0 }, Package () { @@ -99,7 +93,7 @@ 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 90, 69, 56, 46, 36, 30, 0, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }) -- To view, visit https://review.coreboot.org/c/coreboot/+/37272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93930525edf4c5efb6b73bdfc8f16950754f7c9a Gerrit-Change-Number: 37272 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Change compilation based on TIGERLAKE_BASE
by Maulik V Vaghela (Code Review) 02 Dec '19

02 Dec '19

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37376 ) Change subject: soc/intel/tigerlake: Change compilation based on TIGERLAKE_BASE ...................................................................... soc/intel/tigerlake: Change compilation based on TIGERLAKE_BASE since we support JSL and TGL soc under tigerlake folder, we need to make sure all soc related files get compiled based on CONFIG_SOC_INTEL_TIGERLAKE_BASE and not only for Tigerlake. We can control soc specific file compilation through Kconfig of individual soc. Change-Id: I1a663555d0bdf7588c4e12363375e7c90629f7d9 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/tigerlake/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/37376/1 diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index b402fa0..0d5aecb 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y) +ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode -- To view, visit https://review.coreboot.org/c/coreboot/+/37376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a663555d0bdf7588c4e12363375e7c90629f7d9 Gerrit-Change-Number: 37376 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/poppy/rammus: add libgfxinit support
by Matt DeVillier (Code Review) 02 Dec '19

02 Dec '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37312 ) Change subject: mb/google/poppy/rammus: add libgfxinit support ...................................................................... mb/google/poppy/rammus: add libgfxinit support Add libgfxinit support for rammus. Use panel init values from VBT. Test: build/boot rammus with libgfxinit and Tianocore payload Change-Id: I4775a36d83bd67a0064a162effaf96649e9c186d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/Makefile.inc A src/mainboard/google/poppy/gma-mainboard.ads M src/mainboard/google/poppy/variants/rammus/devicetree.cb 4 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/37312/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 9fafef7..e71c020 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -201,6 +201,7 @@ select DRIVERS_USB_ACPI select INCLUDE_NHLT_BLOBS_RAMMUS if USE_BLOBS select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_SPI_TPM_CR50 config VARIANT_SPECIFIC_OPTIONS_SORAKA diff --git a/src/mainboard/google/poppy/Makefile.inc b/src/mainboard/google/poppy/Makefile.inc index 030cf1d..9d26430 100644 --- a/src/mainboard/google/poppy/Makefile.inc +++ b/src/mainboard/google/poppy/Makefile.inc @@ -24,6 +24,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads smm-y += smihandler.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c diff --git a/src/mainboard/google/poppy/gma-mainboard.ads b/src/mainboard/google/poppy/gma-mainboard.ads new file mode 100644 index 0000000..87cdb5e --- /dev/null +++ b/src/mainboard/google/poppy/gma-mainboard.ads @@ -0,0 +1,31 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Internal, + DP1, + DP2, + HDMI1, + HDMI2, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 70a4667..f44f9ce 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -1,5 +1,12 @@ chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" + register "gpu_pp_down_delay_ms" = "500" + register "gpu_pp_cycle_delay_ms" = "600" + register "gpu_pp_backlight_on_delay_ms" = " 1" + register "gpu_pp_backlight_off_delay_ms" = "200" + register "gpu_pch_backlight_pwm_hz" = "1000" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/37312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4775a36d83bd67a0064a162effaf96649e9c186d Gerrit-Change-Number: 37312 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mb/intel/coffeelake_rvp: Rename COMETLAKE_RVP to COMETLAKE_RVPU
by Gaggery Tsai (Code Review) 02 Dec '19

02 Dec '19

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36793 ) Change subject: src/mb/intel/coffeelake_rvp: Rename COMETLAKE_RVP to COMETLAKE_RVPU ...................................................................... src/mb/intel/coffeelake_rvp: Rename COMETLAKE_RVP to COMETLAKE_RVPU This patch renames COMETLAKE_RVP to COMETLAKE_RVPU to avoid confusing. TEST=build an image with COMETLAKE_RVPU Change-Id: I93d7b5cc0be475926bb92503b66797dc67e607f5 Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig.name 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/36793/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 13e55b3..e7c5d36 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVP +if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVPU config BOARD_SPECIFIC_OPTIONS def_bool y @@ -13,7 +13,7 @@ select DRIVERS_I2C_GENERIC select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_COFFEELAKE_RVPU - select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVP + select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVPU select MAINBOARD_USES_IFD_EC_REGION select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 @@ -27,12 +27,12 @@ default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11 default "whl_u" if BOARD_INTEL_WHISKEYLAKE_RVP default "cfl_s" if BOARD_INTEL_COFFEELAKE_RVP8 - default "cml_u" if BOARD_INTEL_COMETLAKE_RVP + default "cml_u" if BOARD_INTEL_COMETLAKE_RVPU config MAINBOARD_PART_NUMBER string default "whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP - default "cmlrvp" if BOARD_INTEL_COMETLAKE_RVP + default "cmlrvp" if BOARD_INTEL_COMETLAKE_RVPU default "cflrvp" config MAINBOARD_VENDOR @@ -42,7 +42,7 @@ config MAINBOARD_FAMILY string default "Intel_whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP - default "Intel_cmlrvp" if BOARD_INTEL_COMETLAKE_RVP + default "Intel_cmlrvp" if BOARD_INTEL_COMETLAKE_RVPU default "Intel_cflrvp" config CHROMEOS diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index 35c0f0f..519cd50 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -12,6 +12,6 @@ config BOARD_INTEL_COFFEELAKE_RVP8 bool "-> Coffeelake S U-DIMM DDR4 RVP8" select SOC_INTEL_COFFEELAKE -config BOARD_INTEL_COMETLAKE_RVP +config BOARD_INTEL_COMETLAKE_RVPU bool "-> Cometlake U DDR4 RVP" select SOC_INTEL_COMETLAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/36793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93d7b5cc0be475926bb92503b66797dc67e607f5 Gerrit-Change-Number: 36793 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019