coreboot-gerrit November 2019

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Change in coreboot[master]: soc/intel: Intel graphics driver scans generic bus
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36042 ) Change subject: soc/intel: Intel graphics driver scans generic bus ...................................................................... soc/intel: Intel graphics driver scans generic bus This change allows for Intel graphics devices to use drivers/generic/gfx driver to populate ACPI SSDT table for common graphics related devices and methods. BUG=b:142237145 TEST=On sarien_cml add generic/gfx to the devicetree and device is enumerated and correct SSDT ASL is observed. Change-Id: Ibc86a88687ac860ebef19a4b68af64fd50d12b8e Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/soc/intel/common/block/graphics/graphics.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/36042/1 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 8e79eab..82133ff 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -118,6 +118,7 @@ .init = graphics_soc_init, .ops_pci = &pci_dev_ops_pci, .write_acpi_tables = graphics_soc_write_acpi_opregion, + .scan_bus = scan_generic_bus, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/36042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc86a88687ac860ebef19a4b68af64fd50d12b8e Gerrit-Change-Number: 36042 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/gfx: Add generic graphics with SSDT generator
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36041 ) Change subject: drivers/gfx: Add generic graphics with SSDT generator ...................................................................... drivers/gfx: Add generic graphics with SSDT generator This change adds a generic graphics driver that can be added to a devicetree which populates graphics related ACPI table. It will write the _DOD method (Enumerate All Devices Attached to the Display Adapter) and a device object for each device defined. The device may optionally have a connected privacy screen which can be controlled with a _DSM. Example: chip drivers/generic/gfx register "device_count" = "1" register "device[0].name" = ""LCD"" register "device[0].addr" = "0x0400" register "device[0].privacy.enabled" = "1" register "device[0].privacy.detect_function" = ""\\_SB.PCI0.PVSC.GPVD"" register "device[0].privacy.status_function" = ""\\_SB.PCI0.PVSC.GPVX"" register "device[0].privacy.enable_function" = ""\\_SB.PCI0.PVSC.EPVX"" register "device[0].privacy.disable_function" = ""\\_SB.PCI0.LPCB.EC0.DPVX"" device generic 0 on end end ASL Scope (\_SB.PCI0.GFX0) { Method (_DOD, 0, NotSerialized) // _DOD: Display Output Devices { Return (Package (0x01) { 0x00000400 }) } Device (LCD) { Name (_HID, "GOOG0010") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_ADR, 0x0400) // _ADR: Address Name (_STA, 0x0F) // _STA: Status Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("c7033113-8720-4ceb-9090-9d52b3e52d73"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Local2 = \_SB.PCI0.PVSC.GPVD () If ((Local2 == One)) { Return (Buffer (One) { 0x0F }) } } If ((Local1 == One)) { ToBuffer (\_SB.PCI0.PVSC.GPVX (), Local2) Return (Local2) } If ((Local1 == 0x02)) { \_SB.PCI0.PVSC.EPVX () } If ((Local1 == 0x03)) { \_SB.PCI0.PVSC.DPVX () } Return (Buffer (One) { 0x00 }) } Return (Buffer (One) { 0x00 }) } } } BUG=b:142237145 TEST=Added gfx to devicetree on sarien_cml and correct ASL in SSDT Change-Id: Ida520dd7aad81ee7c1e5f2d0d3f5cc1a766d78a0 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- A src/drivers/generic/gfx/Kconfig A src/drivers/generic/gfx/Makefile.inc A src/drivers/generic/gfx/chip.h A src/drivers/generic/gfx/gfx.c 4 files changed, 174 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/36041/1 diff --git a/src/drivers/generic/gfx/Kconfig b/src/drivers/generic/gfx/Kconfig new file mode 100644 index 0000000..f59275a --- /dev/null +++ b/src/drivers/generic/gfx/Kconfig @@ -0,0 +1,4 @@ +config DRIVERS_GENERIC_GFX + bool + default n + depends on HAVE_ACPI_TABLES \ No newline at end of file diff --git a/src/drivers/generic/gfx/Makefile.inc b/src/drivers/generic/gfx/Makefile.inc new file mode 100644 index 0000000..c31986b --- /dev/null +++ b/src/drivers/generic/gfx/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_GFX) += gfx.c diff --git a/src/drivers/generic/gfx/chip.h b/src/drivers/generic/gfx/chip.h new file mode 100644 index 0000000..1d8f909 --- /dev/null +++ b/src/drivers/generic/gfx/chip.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRIVERS_GENERIC_GFX_CHIP_H__ +#define __DRIVERS_GENERIC_GFX_CHIP_H__ + +struct drivers_generic_gfx_privacy_screen_config +{ + int enabled; + const char *detect_function; + const char *status_function; + const char *enable_function; + const char *disable_function; +}; + +struct drivers_generic_gfx_device_config +{ + const char *name; + int addr; + struct drivers_generic_gfx_privacy_screen_config privacy; +}; + + +struct drivers_generic_gfx_config { + int device_count; + struct drivers_generic_gfx_device_config device[5]; +}; + +#endif /* __DRIVERS_GENERIC_GFX_CHIP_H__ */ diff --git a/src/drivers/generic/gfx/gfx.c b/src/drivers/generic/gfx/gfx.c new file mode 100644 index 0000000..40fc871 --- /dev/null +++ b/src/drivers/generic/gfx/gfx.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <device/device.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#define ACPI_DSM_PRIVACY_SCREEN_UUID "C7033113-8720-4CEB-9090-9D52B3E52D73" + +static void privacy_screen_detect_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_write_store(); + acpigen_emit_namestring(config->detect_function); + acpigen_emit_byte(LOCAL2_OP); + acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); + acpigen_write_return_singleton_buffer(0xF); + acpigen_pop_len(); +} +static void privacy_screen_get_status_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_emit_byte(TO_BUFFER_OP); + acpigen_emit_namestring(config->status_function); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(LOCAL2_OP); +} +static void privacy_screen_enable_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_emit_namestring(config->enable_function); +} +static void privacy_screen_disable_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_emit_namestring(config->disable_function); +} + +static void (*privacy_screen_callbacks[])(void *) = { + privacy_screen_detect_cb, + privacy_screen_get_status_cb, + privacy_screen_enable_cb, + privacy_screen_disable_cb, +}; + +static void gfx_fill_ssdt_generator(struct device *dev) +{ + size_t i; + struct drivers_generic_gfx_config *config = dev->chip_info; + + const char *scope = acpi_device_scope(dev); + + acpigen_write_scope(scope); + + /* Method (_DOD, 0) */ + acpigen_write_method("_DOD", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(config->device_count); + for (i = 0; i < config->device_count; i++) { + acpigen_write_dword (config->device[i].addr); + } + acpigen_pop_len(); /* End Package. */ + acpigen_pop_len(); /* End Method. */ + + for (i = 0; i < config->device_count; i++) { + acpigen_write_device(config->device[i].name); + + acpigen_write_name_integer("_ADR", config->device[i].addr); + acpigen_write_name_integer("_STA", 0xF); + + if (config->device[i].privacy.enabled) { + acpigen_write_dsm(ACPI_DSM_PRIVACY_SCREEN_UUID, + privacy_screen_callbacks, + ARRAY_SIZE(privacy_screen_callbacks), + &config->device[i].privacy); + } + + acpigen_pop_len(); /* Device */ + } + acpigen_pop_len(); /* Scope */ +} + +static const char *gfx_acpi_name(const struct device *dev) +{ + return "GFX0"; +} + +static struct device_operations gfx_ops = { + .acpi_name = gfx_acpi_name, + .acpi_fill_ssdt_generator = gfx_fill_ssdt_generator, +}; + +static void gfx_enable(struct device *dev) +{ + struct drivers_generic_gfx_config *config = dev->chip_info; + + if (!config) + return; + + dev->ops = &gfx_ops; +} + +struct chip_operations drivers_generic_gfx_ops = { + CHIP_NAME("Graphics Device") + .enable_dev = gfx_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/36041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida520dd7aad81ee7c1e5f2d0d3f5cc1a766d78a0 Gerrit-Change-Number: 36041 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Move 'static' is at beginning of declaration
by HAOUAS Elyes (Code Review) 02 Dec '19

02 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33673 Change subject: src: Move 'static' is at beginning of declaration ...................................................................... src: Move 'static' is at beginning of declaration Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gizmosphere/gizmo/platform_cfg.h M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_crtm.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/intel/fsp_broadwell_de/gpio.c 7 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33673/1 diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index 57b1aec..c56b537 100644 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -212,7 +212,7 @@ */ #define GEC_CONFIG 0 -const static CODECENTRY gizmo_codec_alc272[] = +static const CODECENTRY gizmo_codec_alc272[] = { /* NID, PinConfig */ {0x11, 0x411111F0}, /* S/PDIF-OUT2 unused */ diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index ed372b5..a1ba310 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -88,7 +88,7 @@ } } -const static u8 max_tap[3] = {12, 10, 13}; +static const u8 max_tap[3] = {12, 10, 13}; static int increment_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting) @@ -540,7 +540,7 @@ u32 emrs1; /* Is shifted by bits 2 later so u8 can be used to reduce size */ - const static u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */ + static const u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */ { /* Config 0: 2R2R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x11, 0x91, 0x00}, diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 32618e8..8ca6ec1 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -437,7 +437,7 @@ 5200 }; - const static u8 ddr3_turnaround_tab[3][6][4] = { + static const u8 ddr3_turnaround_tab[3][6][4] = { { /* DDR3 800 */ {0x9, 0x7, 0x7, 0x9}, /* CL = 5 */ {0x9, 0x7, 0x8, 0x8}, /* CL = 6 */ @@ -459,7 +459,7 @@ }; /* [DDR freq][0x26F & 1][pagemod] */ - const static u8 ddr2_x252_tab[2][2][2] = { + static const u8 ddr2_x252_tab[2][2][2] = { { /* DDR2 667 */ {12, 16}, {14, 18} @@ -470,7 +470,7 @@ } }; - const static u8 ddr3_x252_tab[3][2][2] = { + static const u8 ddr3_x252_tab[3][2][2] = { { /* DDR3 800 */ {16, 20}, {18, 22} diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 39cd614..50da155 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -173,7 +173,7 @@ * i.e. those which should not be possible to delete or modify once * the RO exits, and the rest of the NVRAM spaces. */ -const static TPMA_NV ro_space_attributes = { +static const TPMA_NV ro_space_attributes = { .TPMA_NV_PPWRITE = 1, .TPMA_NV_AUTHREAD = 1, .TPMA_NV_PPREAD = 1, @@ -182,7 +182,7 @@ .TPMA_NV_POLICY_DELETE = 1, }; -const static TPMA_NV rw_space_attributes = { +static const TPMA_NV rw_space_attributes = { .TPMA_NV_PPWRITE = 1, .TPMA_NV_AUTHREAD = 1, .TPMA_NV_PPREAD = 1, @@ -193,7 +193,7 @@ * This policy digest was obtained using TPM2_PolicyPCR * selecting only PCR_0 with a value of all zeros. */ -const static uint8_t pcr0_unchanged_policy[] = { +static const uint8_t pcr0_unchanged_policy[] = { 0x09, 0x93, 0x3C, 0xCE, 0xEB, 0xB4, 0x41, 0x11, 0x18, 0x81, 0x1D, 0xD4, 0x47, 0x78, 0x80, 0x08, 0x88, 0x86, 0x62, 0x2D, 0xD7, 0x79, 0x94, 0x46, 0x62, 0x26, 0x68, 0x8E, 0xEE, 0xE6, 0x6A, 0xA1}; diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index e4266b2..f68ab0a4 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -29,7 +29,7 @@ { int i; struct region_device fmap; - const static char *fmap_cbfs_names[] = { + static const char *fmap_cbfs_names[] = { "COREBOOT", "FW_MAIN_A", "FW_MAIN_B", diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 45408ea..e1df91f 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -44,7 +44,7 @@ * waiting for each device to become available, a single delay will be * executed. */ -const static struct stoneyridge_aoac aoac_devs[] = { +static const struct stoneyridge_aoac aoac_devs[] = { { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, @@ -116,7 +116,7 @@ * amd_pci_int_defs.h, just add the pair at the end of this table. * Order is not important. */ -const static struct irq_idx_name irq_association[] = { +static const struct irq_idx_name irq_association[] = { { PIRQ_A, "INTA#" }, { PIRQ_B, "INTB#" }, { PIRQ_C, "INTC#" }, diff --git a/src/soc/intel/fsp_broadwell_de/gpio.c b/src/soc/intel/fsp_broadwell_de/gpio.c index 41100e9..01c4d9e 100644 --- a/src/soc/intel/fsp_broadwell_de/gpio.c +++ b/src/soc/intel/fsp_broadwell_de/gpio.c @@ -24,7 +24,7 @@ #include <soc/gpio.h> /* Use a wrapper for register addresses for different banks. */ -const static struct gpio_config_regs regs[GPIO_NUM_BANKS] = { +static const struct gpio_config_regs regs[GPIO_NUM_BANKS] = { [0] = { .use_sel = GPIO_1_USE_SEL, .io_sel = GPIO_1_IO_SEL, .level = GPIO_1_LVL, .nmi_en = GPIO_1_NMI_EN, .blink_en = GPIO_1_BLINK, .invert_input = GPIO_1_INVERT }, -- To view, visit https://review.coreboot.org/c/coreboot/+/33673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Gerrit-Change-Number: 33673 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/icelake_rvp: Remove unused mainboard ACPI write table
by Aamir Bohra (Code Review) 02 Dec '19

02 Dec '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37354 ) Change subject: mb/intel/icelake_rvp: Remove unused mainboard ACPI write table ...................................................................... mb/intel/icelake_rvp: Remove unused mainboard ACPI write table Change-Id: I19040cca064c2ce063aab77391e0577271c6e9dc Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/mainboard.c 1 file changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/37354/1 diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c index 36d6a3e..8e51e45 100644 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ b/src/mainboard/intel/icelake_rvp/mainboard.c @@ -29,20 +29,8 @@ gpio_configure_pads(pads, num); } -static unsigned long mainboard_write_acpi_tables(struct device *device, - unsigned long current, - acpi_rsdp_t *rsdp) -{ - uintptr_t start_addr; - - start_addr = current; - - return start_addr; -} - static void mainboard_enable(struct device *dev) { - dev->ops->write_acpi_tables = mainboard_write_acpi_tables; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19040cca064c2ce063aab77391e0577271c6e9dc Gerrit-Change-Number: 37354 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/coreboot_table: Add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot table
by Yu-Ping Wu (Code Review) 02 Dec '19

02 Dec '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37234 ) Change subject: lib/coreboot_table: Add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot table ...................................................................... lib/coreboot_table: Add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot table Since struct vb2_shared_data already contains workbuf_size and vboot_workbuf_size is never used in depthcharge, remove it from struct sysinfo_t. In addition, remove lb_vboot_workbuf() and add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot table with add_cbmem_pointers(). Parsing of coreboot table in libpayload is modified accordingly. BRANCH=none BUG=chromium:1021452 TEST=emerge-nami coreboot libpayload depthcharge; Akali booted correctly Change-Id: I890df3ff93fa44ed6d3f9ad05f9c6e49780a8ecb Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/lib/coreboot_table.c 3 files changed, 4 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/37234/1 diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index c05be7c..4b929f1 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -96,7 +96,6 @@ struct cb_mainboard *mainboard; void *vboot_workbuf; - uint32_t vboot_workbuf_size; #if CONFIG(LP_ARCH_X86) int x86_rom_var_mtrr_index; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 2ff2090..f6e9379 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -86,10 +86,7 @@ static void cb_parse_vboot_workbuf(unsigned char *ptr, struct sysinfo_t *info) { - struct lb_range *vbwb = (struct lb_range *)ptr; - - info->vboot_workbuf = (void *)(uintptr_t)vbwb->range_start; - info->vboot_workbuf_size = vbwb->range_size; + info->vboot_workbuf = get_cbmem_ptr(ptr); } static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 8b18dfb..2083b2a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -218,23 +218,6 @@ } #endif /* CONFIG_CHROMEOS */ -static void lb_vboot_workbuf(struct lb_header *header) -{ - struct lb_range *vbwb; - void *wb = vboot_get_workbuf(); - - vbwb = (struct lb_range *)lb_new_record(header); - vbwb->tag = LB_TAG_VBOOT_WORKBUF; - vbwb->size = sizeof(*vbwb); - vbwb->range_start = (uintptr_t)wb; - /* - * TODO(chromium:1021452): Since cbmem size of vboot workbuf is now - * always a known value, we hardcode the value of range_size here. - * Ultimately we'll want to move this to add_cbmem_pointers() below. - */ - vbwb->range_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE; -} - __weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t ram_code(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t sku_id(void) { return UNDEFINED_STRAPPING_ID; } @@ -349,6 +332,9 @@ {CBMEM_ID_WIFI_CALIBRATION, LB_TAG_WIFI_CALIBRATION}, {CBMEM_ID_TCPA_LOG, LB_TAG_TCPA_LOG}, {CBMEM_ID_FMAP, LB_TAG_FMAP}, +#if CONFIG(VBOOT) + {CBMEM_ID_VBOOT_WORKBUF, LB_TAG_VBOOT_WORKBUF}, +#endif }; int i; @@ -558,11 +544,6 @@ lb_vbnv(head); #endif - if (CONFIG(VBOOT)) { - /* pass along the vboot workbuf address. */ - lb_vboot_workbuf(head); - } - /* Add strapping IDs if available */ lb_board_id(head); lb_ram_code(head); -- To view, visit https://review.coreboot.org/c/coreboot/+/37234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I890df3ff93fa44ed6d3f9ad05f9c6e49780a8ecb Gerrit-Change-Number: 37234 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: security/vboot: Remove struct vboot_working_data
by Yu-Ping Wu (Code Review) 02 Dec '19

02 Dec '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37231 ) Change subject: security/vboot: Remove struct vboot_working_data ...................................................................... security/vboot: Remove struct vboot_working_data After CB:36808, CB:36844 and CB:36845, all fields except buffer_offset were removed from struct vboot_working_data. Since buffer_offset is used to record the offset of the workbuf relative to the whole structure, it is no longer needed. This patch removes the structure, and renames vboot_get_working_data() to vboot_get_workbuf(). BRANCH=none BUG=chromium:1021452 TEST=emerge-nami coreboot Change-Id: I304a5e4236f13b1aecd64b88ca5c8fbc1526e592 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/lib/coreboot_table.c M src/security/vboot/common.c M src/security/vboot/misc.h 3 files changed, 24 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/37231/1 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 7245a63..8b18dfb 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -221,20 +221,18 @@ static void lb_vboot_workbuf(struct lb_header *header) { struct lb_range *vbwb; - struct vboot_working_data *wd = vboot_get_working_data(); + void *wb = vboot_get_workbuf(); vbwb = (struct lb_range *)lb_new_record(header); vbwb->tag = LB_TAG_VBOOT_WORKBUF; vbwb->size = sizeof(*vbwb); - vbwb->range_start = (uintptr_t)wd + wd->buffer_offset; + vbwb->range_start = (uintptr_t)wb; /* * TODO(chromium:1021452): Since cbmem size of vboot workbuf is now * always a known value, we hardcode the value of range_size here. - * Ultimately we'll want to move this to add_cbmem_pointers() below, - * but we'll have to get rid of the vboot_working_data struct first. + * Ultimately we'll want to move this to add_cbmem_pointers() below. */ - vbwb->range_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE - - wd->buffer_offset; + vbwb->range_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE; } __weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index bad01ff..cb4c569 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -27,58 +27,43 @@ static struct vb2_context *vboot_ctx CAR_GLOBAL; -struct vboot_working_data *vboot_get_working_data(void) +void *vboot_get_workbuf(void) { - struct vboot_working_data *wd = NULL; + void *wb = NULL; if (cbmem_possibly_online()) - wd = cbmem_find(CBMEM_ID_VBOOT_WORKBUF); + wb = cbmem_find(CBMEM_ID_VBOOT_WORKBUF); - if (wd == NULL && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) && + if (wb == NULL && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) && preram_symbols_available()) - wd = (struct vboot_working_data *)_vboot2_work; + wb = (void *)_vboot2_work; - assert(wd != NULL); + assert(wb != NULL); - return wd; -} - -static inline void *vboot_get_workbuf(struct vboot_working_data *wd) -{ - return (void *)((uintptr_t)wd + wd->buffer_offset); + return wb; } struct vb2_context *vboot_get_context(void) { struct vb2_context **vboot_ctx_ptr = car_get_var_ptr(&vboot_ctx); - struct vboot_working_data *wd; + void *wb; /* Return if context has already been initialized/restored. */ if (*vboot_ctx_ptr) return *vboot_ctx_ptr; - wd = vboot_get_working_data(); + wb = vboot_get_workbuf(); /* Restore context from a previous stage. */ if (vboot_logic_executed()) { - assert(vb2api_reinit(vboot_get_workbuf(wd), - vboot_ctx_ptr) == VB2_SUCCESS); + assert(vb2api_reinit(wb, vboot_ctx_ptr) == VB2_SUCCESS); return *vboot_ctx_ptr; } assert(verification_should_run()); - /* - * vboot prefers 16-byte alignment. This takes away 16 bytes - * from the VBOOT2_WORK region, but the vboot devs said that's okay. - */ - memset(wd, 0, sizeof(*wd)); - wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16); - /* Initialize vb2_shared_data and friends. */ - assert(vb2api_init(vboot_get_workbuf(wd), - VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE - - wd->buffer_offset, + assert(vb2api_init(wb, VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE, vboot_ctx_ptr) == VB2_SUCCESS); return *vboot_ctx_ptr; @@ -102,30 +87,24 @@ * For platforms that do not employ VBOOT_STARTS_IN_ROMSTAGE, vboot * verification occurs before CBMEM is brought online, using pre-RAM. * In order to make vboot data structures available downstream, copy - * vboot_working_data from SRAM/CAR into CBMEM. + * vboot workbuf from SRAM/CAR into CBMEM. */ static void vboot_migrate_cbmem(int unused) { const size_t cbmem_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE; - struct vboot_working_data *wd_preram = - (struct vboot_working_data *)_vboot2_work; - struct vboot_working_data *wd_cbmem = - cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); - assert(wd_cbmem != NULL); - memcpy(wd_cbmem, wd_preram, sizeof(struct vboot_working_data)); - vb2api_relocate(vboot_get_workbuf(wd_cbmem), - vboot_get_workbuf(wd_preram), - cbmem_size - wd_cbmem->buffer_offset, + void *wb_preram = (void *)_vboot2_work; + void *wb_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); + assert(wb_cbmem != NULL); + vb2api_relocate(wb_cbmem, wb_preram, cbmem_size, car_get_var_ptr(&vboot_ctx)); } ROMSTAGE_CBMEM_INIT_HOOK(vboot_migrate_cbmem) #else static void vboot_setup_cbmem(int unused) { - struct vboot_working_data *wd_cbmem = - cbmem_add(CBMEM_ID_VBOOT_WORKBUF, - VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE); - assert(wd_cbmem != NULL); + const void *wb_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, + VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE); + assert(wb_cbmem != NULL); } ROMSTAGE_CBMEM_INIT_HOOK(vboot_setup_cbmem) #endif diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 1b14799..ccaccb2 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -24,21 +24,9 @@ struct vb2_shared_data; /* - * Stores vboot-related information. selected_region is used by verstage to - * store the location of the selected slot. buffer is used by vboot to store - * its work buffer. vb2_context is contained within this work buffer, and is - * accessible via vboot_get_context() declared below. - * Keep the struct CPU architecture agnostic as it crosses stage boundaries. - */ -struct vboot_working_data { - /* offset of the buffer from the start of this struct */ - uint16_t buffer_offset; -}; - -/* * Source: security/vboot/common.c */ -struct vboot_working_data *vboot_get_working_data(void); +void *vboot_get_workbuf(void); struct vb2_context *vboot_get_context(void); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/37231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I304a5e4236f13b1aecd64b88ca5c8fbc1526e592 Gerrit-Change-Number: 37231 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: sb/amd/cimx: replace cimx_util with common ACPIMMIO AMD block
by Michał Żygowski (Code Review) 02 Dec '19

02 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37328 ) Change subject: sb/amd/cimx: replace cimx_util with common ACPIMMIO AMD block ...................................................................... sb/amd/cimx: replace cimx_util with common ACPIMMIO AMD block Drop the redundant cimx_util, remove the includes when appropriate and replace the implementation with amdblocks/acpimmio where needed. TEST=boot PC Engines apu1 and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I66b1f82926372b6ebb570893b6eb73c7f2935b9d --- M src/mainboard/amd/inagua/mainboard.c M src/mainboard/amd/persimmon/mainboard.c M src/mainboard/amd/south_station/mainboard.c M src/mainboard/amd/union_station/mainboard.c M src/mainboard/asrock/e350m1/mainboard.c M src/mainboard/elmex/pcm205400/mainboard.c M src/mainboard/gizmosphere/gizmo/mainboard.c M src/mainboard/jetway/nf81-t56n-lf/mainboard.c M src/mainboard/lippert/frontrunner-af/mainboard.c M src/mainboard/lippert/toucan-af/mainboard.c M src/mainboard/pcengines/apu1/gpio_ftns.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu1/romstage.c M src/mainboard/pcengines/apu2/gpio_ftns.c M src/southbridge/amd/cimx/Makefile.inc D src/southbridge/amd/cimx/cimx_util.c D src/southbridge/amd/cimx/cimx_util.h M src/southbridge/amd/cimx/sb800/Kconfig M src/southbridge/amd/cimx/sb800/fan.c 19 files changed, 45 insertions(+), 145 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37328/1 diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index cf40e26..83fe394 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> -#include <southbridge/amd/cimx/cimx_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */ static void init_gpios(void) @@ -63,8 +63,8 @@ * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 43be863..0e89ffd 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> #include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/cimx/cimx_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> @@ -139,8 +139,8 @@ * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index c6f2196..9b041e0 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <delay.h> #include <device/device.h> -#include <southbridge/amd/cimx/cimx_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */ /** @@ -59,8 +59,8 @@ * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index e2c0ac7..d680520 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> -#include <southbridge/amd/cimx/cimx_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */ /********************************************** @@ -31,8 +31,8 @@ * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index b83a57f..e2f4f2b 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> -#include <southbridge/amd/cimx/cimx_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /********************************************** @@ -46,8 +46,8 @@ * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index 43be863..0e89ffd 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> #include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/cimx/cimx_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> @@ -139,8 +139,8 @@ * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 36fa5f9..8196922 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <southbridge/amd/cimx/cimx_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /********************************************** diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index 3439d2f..0a12c3f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ - +#include <amdblocks/acpimmio.h> #include <device/mmio.h> #include <console/console.h> #include <device/device.h> @@ -23,7 +23,6 @@ #include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/pci_devs.h> -#include <southbridge/amd/cimx/cimx_util.h> #include <northbridge/amd/agesa/family14/pci_devs.h> /*********************************************************** @@ -142,8 +141,8 @@ * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 44d0104..ea473c0 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -14,6 +14,7 @@ */ #include <stdlib.h> +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -21,7 +22,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <southbridge/amd/cimx/cimx_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <vendorcode/amd/cimx/sb800/OEM.h> /* SMBUS0_BASE_ADDRESS */ #include <southbridge/amd/cimx/sb800/gpio_oem.h> @@ -136,8 +136,8 @@ * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 746b195..b000688 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -14,13 +14,13 @@ */ #include <stdlib.h> +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <southbridge/amd/cimx/cimx_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <vendorcode/amd/cimx/sb800/OEM.h> /* SMBUS0_BASE_ADDRESS */ #include <southbridge/amd/cimx/sb800/gpio_oem.h> @@ -101,8 +101,8 @@ * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c index 7a988e7..f0b64ac 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.c +++ b/src/mainboard/pcengines/apu1/gpio_ftns.c @@ -14,23 +14,16 @@ */ #include <stdint.h> +#include <amdblocks/acpimmio.h> #include <arch/io.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/cimx/cimx_util.h> #include "gpio_ftns.h" uintptr_t find_gpio_base(void) { - u8 pm_index, pm_data; - uintptr_t base_addr = 0; - - /* Find the ACPImmioAddr base address */ - for (pm_index = 0x27; pm_index > 0x23; pm_index--) { - outb(pm_index, PM_INDEX); - pm_data = inb(PM_DATA); - base_addr <<= 8; - base_addr |= (u32)pm_data; - } + uintptr_t base_addr; + /* Get the ACPIMMIO base address */ + base_addr = pm_read32(0x24); base_addr &= 0xFFFFF000; return (base_addr); } diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 088c839..1c30291 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/cimx/cimx_util.h> #include <smbios.h> #include <string.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index ab48943..89bf304 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/cimx/cimx_util.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5104d/nct5104d.h> #include "gpio_ftns.h" @@ -33,16 +33,16 @@ * controlled in PM_REG 5Bh register. "Always Power On" works by writing a * value of 05h. */ - u8 bdata = pm_ioread(SB_PMIOA_REG5B); + u8 bdata = pm_read8(SB_PMIOA_REG5B); bdata &= 0xf8; //clear bits 0-2 bdata |= 0x05; //set bits 0,2 - pm_iowrite(SB_PMIOA_REG5B, bdata); + pm_write8(SB_PMIOA_REG5B, bdata); /* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins */ - bdata = pm_ioread(SB_PMIOA_REGEA); + bdata = pm_read8(SB_PMIOA_REGEA); bdata &= 0xfe; //clear bit 0 bdata |= 0x01; //set bit 0 - pm_iowrite(SB_PMIOA_REGEA, bdata); + pm_write8(SB_PMIOA_REGEA, bdata); //configure required GPIOs mmio_base = find_gpio_base(); diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index a1e2e51..249ecc3 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -15,7 +15,6 @@ #include <stdint.h> #include <device/mmio.h> -#include <southbridge/amd/cimx/cimx_util.h> #include <FchPlatform.h> #include "gpio_ftns.h" diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index 5d1d3f6..6161c14 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -14,7 +14,3 @@ # subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 - -romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c - -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c diff --git a/src/southbridge/amd/cimx/cimx_util.c b/src/southbridge/amd/cimx/cimx_util.c deleted file mode 100644 index 1db04d8..0000000 --- a/src/southbridge/amd/cimx/cimx_util.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci.h> -#include <arch/io.h> -#include "cimx_util.h" - -static void pmio_write_index(u16 port_base, u8 reg, u8 value) -{ - outb(reg, port_base); - outb(value, port_base + 1); -} - -static u8 pmio_read_index(u16 port_base, u8 reg) -{ - outb(reg, port_base); - return inb(port_base + 1); -} - -void pm_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM_INDEX, reg, value); -} - -u8 pm_ioread(u8 reg) -{ - return pmio_read_index(PM_INDEX, reg); -} - -void pm2_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM2_INDEX, reg, value); -} - -u8 pm2_ioread(u8 reg) -{ - return pmio_read_index(PM2_INDEX, reg); -} diff --git a/src/southbridge/amd/cimx/cimx_util.h b/src/southbridge/amd/cimx/cimx_util.h deleted file mode 100644 index bf41e8a..0000000 --- a/src/southbridge/amd/cimx/cimx_util.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CIMX_UTIL_H -#define CIMX_UTIL_H - -#include <stdint.h> - -/* FCH index/data registers */ -#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 -#define PM2_INDEX 0xcd0 -#define PM2_DATA 0xcd1 -#define PCI_INTR_INDEX 0xc00 -#define PCI_INTR_DATA 0xc01 - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -#endif /* CIMX_UTIL_H */ diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index aa5160b..0b790b0 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -21,6 +21,9 @@ select AMD_SB_CIMX select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index a8dfa31..42c13d7 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <southbridge/amd/cimx/cimx_util.h> +#include <amdblocks/acpimmio.h> #include <device/device.h> #include <device/pci.h> /* device_operations */ #include <device/pci_ops.h> @@ -31,27 +31,27 @@ /* Init Fan 0 */ if (sb_chip->fan0_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]); + pm2_write8(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]); /* Init Fan 1 */ if (sb_chip->fan1_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]); + pm2_write8(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]); /* Init Fan 2 */ if (sb_chip->fan2_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]); + pm2_write8(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]); /* Init Fan 3 */ if (sb_chip->fan3_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]); + pm2_write8(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]); /* Init Fan 4 */ if (sb_chip->fan4_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]); + pm2_write8(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b1f82926372b6ebb570893b6eb73c7f2935b9d Gerrit-Change-Number: 37328 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: mb/google/poppy: Remove useless ifs around voltage and GPIO direction...
by Sakari Ailus (Code Review) 02 Dec '19

02 Dec '19

Sakari Ailus has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36746 ) Change subject: mb/google/poppy: Remove useless ifs around voltage and GPIO direction configuration ...................................................................... mb/google/poppy: Remove useless ifs around voltage and GPIO direction configuration The methods generally tested OP region settings and only changed them if they were not in their desired values. Instead, assign them directly without checking them. Signed-off-by: Sakari Ailus <sakari.ailus(a)linux.intel.com> Tested-by: Jacopo Mondi <jacopo(a)jmondi.org> Change-Id: I3ceca4bd51c4410c7020431f4fd682c4ca925110 --- M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl 1 file changed, 11 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/36746/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index d70726f..d15f5c6 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -438,10 +438,6 @@ } } - /* C0GP is used to indicate if CAM0 - * GPIOs are configured as input. - */ - Name (C0GP, 0) /* Power resource methods for CAM0 */ PowerResource (OVTH, 0, 0) { Name (STA, 0) @@ -453,22 +449,15 @@ daisy chain */ DOVD(1) - If (LEqual (C0GP, 0)) { - \_SB.PCI0.I2C2.PMIC.CGP1() - \_SB.PCI0.I2C2.PMIC.CGP2() - C0GP = 1 - } + \_SB.PCI0.I2C2.PMIC.CGP1() + \_SB.PCI0.I2C2.PMIC.CGP2() - if (LNotEqual (ACVA, 109)) { - /* Set ANA at 2.8152V */ - ACVA = 109 - } + /* Set ANA at 2.8152V */ + ACVA = 109 VACT = 1 - if (LNotEqual (DCVA, 12)) { - /* Set CORE at 1.2V */ - DCVA = 12 - } + /* Set CORE at 1.2V */ + DCVA = 12 VDCT = 1 \_SB.PCI0.I2C2.PMIC.CLKE() @@ -527,11 +516,8 @@ daisy chain */ DOVD(1) - if (LNotEqual (AX2V, 52)) { - /* Set VAUX2 as - 1.8006 V */ - AX2V = 52 - } + /* Set VAUX2 as 1.8006 V */ + AX2V = 52 VAX2 = 1 /* Enable VAUX2 */ \_SB.PCI0.I2C2.PMIC.CGP4(1) @@ -542,10 +528,8 @@ */ Sleep(1) - if (LNotEqual (AX1V, 19)) { /* Set VAUX1 as 1.2132V */ - AX1V = 19 - } + AX1V = 19 VAX1 = 1 /* Enable VAUX1 */ /* Wait for VDD to settle. */ @@ -603,11 +587,8 @@ /* Enable VCM regulator */ VCMC = 1 - if (LNotEqual (VCMV, 109)) { - /* Set VCM value at - 2.8152 V */ - VCMV = 109 - } + /* Set VCM value at 2.8152 V */ + VCMV = 109 Sleep(3) STA = 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ceca4bd51c4410c7020431f4fd682c4ca925110 Gerrit-Change-Number: 36746 Gerrit-PatchSet: 1 Gerrit-Owner: Sakari Ailus <sakari.ailus+coreboot.org(a)linux.intel.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/poppy: Remove redundant mutex
by Sakari Ailus (Code Review) 02 Dec '19

02 Dec '19

Sakari Ailus has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36745 ) Change subject: mb/google/poppy: Remove redundant mutex ...................................................................... mb/google/poppy: Remove redundant mutex The mutex is only used in one method and that method is serialised. Remove the mutex. Reported-by: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> Signed-off-by: Sakari Ailus <sakari.ailus(a)linux.intel.com> Tested-by: Jacopo Mondi <jacopo(a)jmondi.org> Change-Id: Ic173d557f4b49cc9e860d13b782fc4940fd80869 --- M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl 1 file changed, 30 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/36745/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index fc23d06..d70726f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -400,50 +400,41 @@ } /* Reference count for VSIO */ - Mutex (MUTV, 0) Name (VSIC, 0) Method (DOVD, 1, Serialized) { - /* Save Acquire result so we can check for - Mutex acquired */ - Store (Acquire (MUTV, 1000), Local0) - /* Check for Mutex acquired */ - If (LEqual (Local0, Zero)) { - /* Turn off VSIO */ - If (LEqual (Arg0, Zero)) { - /* Decrement only if VSIC > 0 */ - if (LGreater (VSIC, 0)) { - Decrement (VSIC) - If (LEqual (VSIC, Zero)) { - VSIO = 0 - Sleep(1) - PMOF() - } - } - } ElseIf (LEqual (Arg0, 1)) { - /* Increment only if VSIC < 4 */ - If (LLess (VSIC, 4)) { - /* Turn on VSIO */ - If (LEqual (VSIC, Zero)) { - PMON() - VSIO = 3 - - if (LNotEqual (IOVA, 52)) { - /* Set VSIO value as - 1.8006 V */ - IOVA = 52 - } - if (LNotEqual (SIOV, 52)) { - /* Set VSIO value as - 1.8006 V */ - SIOV = 52 - } - Sleep(3) - } - Increment (VSIC) + /* Turn off VSIO */ + If (LEqual (Arg0, Zero)) { + /* Decrement only if VSIC > 0 */ + if (LGreater (VSIC, 0)) { + Decrement (VSIC) + If (LEqual (VSIC, Zero)) { + VSIO = 0 + Sleep(1) + PMOF() } } + } ElseIf (LEqual (Arg0, 1)) { + /* Increment only if VSIC < 4 */ + If (LLess (VSIC, 4)) { + /* Turn on VSIO */ + If (LEqual (VSIC, Zero)) { + PMON() + VSIO = 3 - Release (MUTV) + if (LNotEqual (IOVA, 52)) { + /* Set VSIO value as + 1.8006 V */ + IOVA = 52 + } + if (LNotEqual (SIOV, 52)) { + /* Set VSIO value as + 1.8006 V */ + SIOV = 52 + } + Sleep(3) + } + Increment (VSIC) + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/36745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic173d557f4b49cc9e860d13b782fc4940fd80869 Gerrit-Change-Number: 36745 Gerrit-PatchSet: 1 Gerrit-Owner: Sakari Ailus <sakari.ailus+coreboot.org(a)linux.intel.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/google/poppy: Rework OV13858 power on sequence
by Sakari Ailus (Code Review) 02 Dec '19

02 Dec '19

Sakari Ailus has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36744 ) Change subject: mb/google/poppy: Rework OV13858 power on sequence ...................................................................... mb/google/poppy: Rework OV13858 power on sequence In particular: - Set voltage before enabling regulators - Enable regulators and the clock without any sleeping in between. There's no need to wait there. - Sleep 1 ms in order to wait for regulator voltages settling before lifting xshutdown. Signed-off-by: Sakari Ailus <sakari.ailus(a)linux.intel.com> Tested-by: Jacopo Mondi <jacopo(a)jmondi.org> Change-Id: I0f8857ae369d5038f293a0e2c48c681df535ad86 --- M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl 1 file changed, 17 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/36744/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 355b255..fc23d06 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -468,23 +468,33 @@ C0GP = 1 } - VACT = 1 if (LNotEqual (ACVA, 109)) { /* Set ANA at 2.8152V */ ACVA = 109 } - Sleep(3) + VACT = 1 - \_SB.PCI0.I2C2.PMIC.CLKE() - CLE0 = 1 - - VDCT = 1 if (LNotEqual (DCVA, 12)) { /* Set CORE at 1.2V */ DCVA = 12 } - Sleep(3) + VDCT = 1 + + \_SB.PCI0.I2C2.PMIC.CLKE() + CLE0 = 1 + + /* + * Wait for all regulator + * outputs to settle. + */ + Sleep(1) + \_SB.PCI0.I2C2.PMIC.CRST(1) + + /* + * 5 ms needed before + * streaming on. + */ Sleep(5) STA = 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f8857ae369d5038f293a0e2c48c681df535ad86 Gerrit-Change-Number: 36744 Gerrit-PatchSet: 1 Gerrit-Owner: Sakari Ailus <sakari.ailus+coreboot.org(a)linux.intel.com> Gerrit-MessageType: newchange

3 5

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