coreboot-gerrit November 2019

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Change in coreboot[master]: sc7180: Add SPI-NOR support
by mturney mturney (Code Review) 05 Dec '19

05 Dec '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35501 ) Change subject: sc7180: Add SPI-NOR support ...................................................................... sc7180: Add SPI-NOR support This implements the SPI-NOR driver for the Qualcomm QSPI core. Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/27483/58 Change-Id: I2eb8cf90aa4559541ba293b3fd2870896bed20b7 Signed-off-by: Akash Asthana <akashast(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/include/soc/qspi.h A src/soc/qualcomm/sc7180/qspi.c M src/soc/qualcomm/sc7180/spi.c 6 files changed, 452 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/35501/1 diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index a1a7f03..df5d116 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -28,4 +28,13 @@ help Select the QUP instance to be used for UART console output. +config SC7180_QSPI + bool + default y if COMMON_CBFS_SPI_WRAPPER + prompt "Build Flash Using SPI-NOR" + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 16 + endif diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 5a4b68c..7ad0328 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -12,6 +12,7 @@ bootblock-y += qupv3_fw_config.c bootblock-y += qupv3_config.c bootblock-y += qcom_qup_se.c +bootblock-$(CONFIG_SC7180_QSPI) += qspi.c ################################################################################ verstage-y += timer.c @@ -20,6 +21,7 @@ verstage-y += clock.c verstage-y += qcom_qup_se.c verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-$(CONFIG_SC7180_QSPI) += qspi.c ################################################################################ romstage-y += cbmem.c @@ -32,6 +34,7 @@ romstage-y += clock.c romstage-y += qcom_qup_se.c romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-$(CONFIG_SC7180_QSPI) += qspi.c ################################################################################ ramstage-y += soc.c @@ -44,6 +47,7 @@ ramstage-y += qupv3_config.c ramstage-y += qcom_qup_se.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-$(CONFIG_SC7180_QSPI) += qspi.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index b0cd9f2..8ee04d2 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -18,10 +18,12 @@ #include <soc/mmu.h> #include <soc/clock.h> #include <soc/qupv3_fw_config.h> +#include <soc/qspi.h> void bootblock_soc_init(void) { sc7180_mmu_init(); clock_init(); + quadspi_init(25 * MHz); qupv3_fw_init(); } diff --git a/src/soc/qualcomm/sc7180/include/soc/qspi.h b/src/soc/qualcomm/sc7180/include/soc/qspi.h new file mode 100644 index 0000000..c3d1f78 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/qspi.h @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Qualcomm Technologies. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <types.h> +#include <soc/addressmap.h> +#include <spi-generic.h> + +#ifndef __SOC_QUALCOMM_SC7180_QSPI_H__ +#define __SOC_QUALCOMM_SC7180_QSPI_H__ + +struct sc7180_qspi_regs { + u32 mstr_cfg; + u32 ahb_mstr_cfg; + u32 reserve_0; + u32 mstr_int_en; + u32 mstr_int_sts; + u32 pio_xfer_ctrl; + u32 pio_xfer_cfg; + u32 pio_xfer_sts; + u32 pio_dataout_1byte; + u32 pio_dataout_4byte; + u32 rd_fifo_cfg; + u32 rd_fifo_sts; + u32 rd_fifo_rst; + u32 reserve_1[3]; + u32 next_dma_desc_addr; + u32 current_dma_desc_addr; + u32 current_mem_addr; + u32 hw_version; + u32 rd_fifo[16]; +}; + +check_member(sc7180_qspi_regs, rd_fifo, 0x50); +static struct sc7180_qspi_regs * const sc7180_qspi = (void *) QSPI_BASE; + +// MSTR_CONFIG register + +#define TX_DATA_OE_DELAY_SHIFT 24 +#define TX_DATA_OE_DELAY_MASK (0x3 << TX_DATA_OE_DELAY_SHIFT) +#define TX_CS_N_DELAY_SHIFT 22 +#define TX_CS_N_DELAY_MASK (0x3 << TX_CS_N_DELAY_SHIFT) +#define TX_CLK_DELAY_SHIFT 20 +#define TX_CLK_DELAY_MASK (0x3 << TX_CLK_DELAY_SHIFT) +#define TX_DATA_DELAY_SHIFT 18 +#define TX_DATA_DELAY_MASK (0x3 << TX_DATA_DELAY_SHIFT) +#define LPA_BASE_SHIFT 14 +#define LPA_BASE_MASK (0xF << LPA_BASE_SHIFT) +#define SBL_EN BIT(13) +#define CHIP_SELECT_NUM BIT(12) +#define SPI_MODE_SHIFT 10 +#define SPI_MODE_MASK (0x3 << SPI_MODE_SHIFT) +#define BIG_ENDIAN_MODE BIT(9) +#define DMA_ENABLE BIT(8) +#define PIN_WPN BIT(7) +#define PIN_HOLDN BIT(6) +#define FB_CLK_EN BIT(4) +#define FULL_CYCLE_MODE BIT(3) + +// MSTR_INT_ENABLE and MSTR_INT_STATUS register + +#define DMA_CHAIN_DONE BIT(31) +#define TRANSACTION_DONE BIT(16) +#define WRITE_FIFO_OVERRUN BIT(11) +#define WRITE_FIFO_FULL BIT(10) +#define HRESP_FROM_NOC_ERR BIT(3) +#define RESP_FIFO_RDY BIT(2) +#define RESP_FIFO_NOT_EMPTY BIT(1) +#define RESP_FIFO_UNDERRUN BIT(0) + +// PIO_TRANSFER_CONFIG register + +#define TRANSFER_FRAGMENT BIT(8) +#define MULTI_IO_MODE_SHIFT 1 +#define MULTI_IO_MODE_MASK (0x7 << MULTI_IO_MODE_SHIFT) +#define TRANSFER_DIRECTION BIT(0) + +// PIO_TRANSFER_STATUS register + +#define WR_FIFO_BYTES_SHIFT 16 +#define WR_FIFO_BYTES_MASK (0xFFFF << WR_FIFO_BYTES_SHIFT) + +// RD_FIFO_CONFIG register + +#define CONTINUOUS_MODE BIT(0) + +// RD_FIFO_STATUS register + +#define FIFO_EMPTY BIT(11) +#define WR_CNTS_SHIFT 4 +#define WR_CNTS_MASK (0x7F << WR_CNTS_SHIFT) +#define RDY_64BYTE BIT(3) +#define RDY_32BYTE BIT(2) +#define RDY_16BYTE BIT(1) +#define FIFO_RDY BIT(0) + +// RD_FIFO_RESET register + +#define RESET_FIFO BIT(0) + +#define QSPI_MAX_PACKET_COUNT 0xFFC0 + +void quadspi_init(uint32_t hz); +int sc7180_claim_bus(const struct spi_slave *slave); +int sc7180_setup_bus(const struct spi_slave *slave); +void sc7180_release_bus(const struct spi_slave *slave); +int sc7180_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes); +int sc7180_xfer_dual(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes); +#endif /* __SOC_QUALCOMM_SC7180_QSPI_H__ */ diff --git a/src/soc/qualcomm/sc7180/qspi.c b/src/soc/qualcomm/sc7180/qspi.c new file mode 100644 index 0000000..c589415 --- /dev/null +++ b/src/soc/qualcomm/sc7180/qspi.c @@ -0,0 +1,306 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <spi-generic.h> +#include <spi_flash.h> +#include <arch/cache.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/qspi.h> +#include <soc/gpio.h> +#include <soc/clock.h> +#include <symbols.h> +#include <assert.h> +#include <gpio.h> +#include <string.h> + +#define CACHE_LINE_SIZE 64 + +static int curr_desc_idx = -1; + +struct cmd_desc { + uint32_t data_address; + uint32_t next_descriptor; + uint32_t direction:1; + uint32_t multi_io_mode:3; + uint32_t reserved1:4; + uint32_t fragment:1; + uint32_t reserved2:7; + uint32_t length:16; + //------------------------// + uint32_t bounce_src; + uint32_t bounce_dst; + uint32_t bounce_length; + uint64_t padding[5]; +}; + +enum qspi_mode { + SDR_1BIT = 1, + SDR_2BIT = 2, + SDR_4BIT = 3, + DDR_1BIT = 5, + DDR_2BIT = 6, + DDR_4BIT = 7, +}; + +enum cs_state { + CS_DEASSERT, + CS_ASSERT +}; + +struct xfer_cfg { + enum qspi_mode mode; +}; + +enum bus_xfer_direction { + MASTER_READ = 0, + MASTER_WRITE = 1, +}; + +struct { + struct cmd_desc descriptors[3]; + uint8_t buffers[3][CACHE_LINE_SIZE]; +} *dma = (void *)_dma_coherent; + +static void dma_transfer_chain(struct cmd_desc *chain) +{ + uint32_t mstr_int_status; + + write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF); + write32(&sc7180_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain); + + while (1) { + mstr_int_status = read32(&sc7180_qspi->mstr_int_sts); + if (mstr_int_status & DMA_CHAIN_DONE) + break; + } +} + +static void flush_chain(void) +{ + struct cmd_desc *desc = &dma->descriptors[0]; + uint8_t *src; + uint8_t *dst; + + dma_transfer_chain(desc); + + while (desc) { + if (desc->direction == MASTER_READ) { + if (desc->bounce_length == 0) + dcache_invalidate_by_mva( + (void *)(uintptr_t) desc->data_address, + desc->length); + else { + src = (void *)(uintptr_t) desc->bounce_src; + dst = (void *)(uintptr_t) desc->bounce_dst; + memcpy(dst, src, desc->bounce_length); + } + } + desc = (void *)(uintptr_t) desc->next_descriptor; + } + curr_desc_idx = -1; +} + +static struct cmd_desc *allocate_descriptor(void) +{ + struct cmd_desc *current; + struct cmd_desc *next; + uint8_t index; + + current = (curr_desc_idx == -1) ? + NULL : &dma->descriptors[curr_desc_idx]; + + index = ++curr_desc_idx; + next = &dma->descriptors[index]; + + next->data_address = (uint32_t) (uintptr_t) dma->buffers[index]; + + next->next_descriptor = 0; + next->direction = MASTER_READ; + next->multi_io_mode = 0; + next->reserved1 = 0; + next->fragment = 0; + next->reserved2 = 0; + next->length = 0; + next->bounce_src = 0; + next->bounce_dst = 0; + next->bounce_length = 0; + + if (current) { + current->next_descriptor = (uint32_t)(uintptr_t) next; + current->fragment = 1; + } + + return next; +} + +static void cs_change(enum cs_state state) +{ + gpio_set(GPIO(68), state == CS_DEASSERT); +} + +static void configure_gpios(void) +{ + gpio_output(GPIO(68), 1); + + gpio_configure(GPIO(64), GPIO64_FUNC_QSPI_DATA_0, + GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); + + gpio_configure(GPIO(65), GPIO65_FUNC_QSPI_DATA_1, + GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); + + gpio_configure(GPIO(63), GPIO63_FUNC_QSPI_CLK, + GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); +} + +static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + struct cmd_desc *desc; + uint8_t *ptr; + + desc = allocate_descriptor(); + desc->direction = write; + desc->multi_io_mode = data_mode; + ptr = (void *)(uintptr_t) desc->data_address; + + if (write) { + memcpy(ptr, data, data_bytes); + } else { + desc->bounce_src = (uint32_t)(uintptr_t) ptr; + desc->bounce_dst = (uint32_t)(uintptr_t) data; + desc->bounce_length = data_bytes; + } + + desc->length = data_bytes; +} + +static void queue_direct_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + struct cmd_desc *desc; + + desc = allocate_descriptor(); + desc->direction = write; + desc->multi_io_mode = data_mode; + desc->data_address = (uint32_t)(uintptr_t) data; + desc->length = data_bytes; + + if (write) + dcache_clean_by_mva(data, data_bytes); + else + dcache_invalidate_by_mva(data, data_bytes); +} + +static void queue_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + uint8_t *aligned_ptr; + uint8_t *epilog_ptr; + uint32_t prolog_bytes, aligned_bytes, epilog_bytes; + + if (data_bytes == 0) + return; + + aligned_ptr = + (uint8_t *)ALIGN_UP((uintptr_t)data, CACHE_LINE_SIZE); + + prolog_bytes = MIN(data_bytes, aligned_ptr - data); + aligned_bytes = ALIGN_DOWN(data_bytes - prolog_bytes, CACHE_LINE_SIZE); + epilog_bytes = data_bytes - prolog_bytes - aligned_bytes; + + epilog_ptr = data + prolog_bytes + aligned_bytes; + + if (prolog_bytes) + queue_bounce_data(data, prolog_bytes, data_mode, write); + if (aligned_bytes) + queue_direct_data(aligned_ptr, aligned_bytes, data_mode, write); + if (epilog_bytes) + queue_bounce_data(epilog_ptr, epilog_bytes, data_mode, write); +} + +static void reg_init(void) +{ + uint32_t spi_mode; + uint32_t tx_data_oe_delay, tx_data_delay; + uint32_t mstr_config; + + spi_mode = 0; + + tx_data_oe_delay = 0; + tx_data_delay = 0; + + mstr_config = (tx_data_oe_delay << TX_DATA_OE_DELAY_SHIFT) | + (tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) | + (spi_mode << SPI_MODE_SHIFT) | + (PIN_HOLDN) | + (FB_CLK_EN) | + (DMA_ENABLE) | + (FULL_CYCLE_MODE); + + write32(&sc7180_qspi->mstr_cfg, mstr_config); + write32(&sc7180_qspi->ahb_mstr_cfg, 0xA42); + write32(&sc7180_qspi->mstr_int_en, 0x0); + write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF); + write32(&sc7180_qspi->rd_fifo_cfg, 0x0); + write32(&sc7180_qspi->rd_fifo_rst, RESET_FIFO); +} + +void quadspi_init(uint32_t hz) +{ + assert(dcache_line_bytes() == CACHE_LINE_SIZE); + clock_configure_qspi(hz * 4); + configure_gpios(); + reg_init(); +} + +int sc7180_claim_bus(const struct spi_slave *slave) +{ + cs_change(CS_ASSERT); + return 0; +} + +void sc7180_release_bus(const struct spi_slave *slave) +{ + cs_change(CS_DEASSERT); +} + +static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes, + void *din, size_t in_bytes) +{ + if ((out_bytes && !dout) || (in_bytes && !din) || + (in_bytes && out_bytes)) { + return -1; + } + + queue_data((uint8_t *) (out_bytes ? dout : din), + in_bytes | out_bytes, mode, !!out_bytes); + + flush_chain(); + + return 0; +} + +int sc7180_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + return xfer(SDR_1BIT, dout, out_bytes, din, in_bytes); +} + +int sc7180_xfer_dual(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + return xfer(SDR_2BIT, dout, out_bytes, din, in_bytes); +} diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c index 5abb81a..c6d4cb1 100644 --- a/src/soc/qualcomm/sc7180/spi.c +++ b/src/soc/qualcomm/sc7180/spi.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -15,12 +15,19 @@ #include <spi-generic.h> #include <spi_flash.h> +#include <soc/qspi.h> -static const struct spi_ctrlr spi_ctrlr; +static const struct spi_ctrlr qspi_ctrlr = { + .claim_bus = sc7180_claim_bus, + .release_bus = sc7180_release_bus, + .xfer = sc7180_xfer, + .xfer_dual = sc7180_xfer_dual, + .max_xfer_size = QSPI_MAX_PACKET_COUNT, +}; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { - .ctrlr = &spi_ctrlr, + .ctrlr = &qspi_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/35501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2eb8cf90aa4559541ba293b3fd2870896bed20b7 Gerrit-Change-Number: 35501 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: x86/tsc: Only call tsc_freq_mhz once to init clock
by Mathew King (Code Review) 05 Dec '19

05 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36664 ) Change subject: x86/tsc: Only call tsc_freq_mhz once to init clock ...................................................................... x86/tsc: Only call tsc_freq_mhz once to init clock This change partially reverts https://review.coreboot.org/c/coreboot/+/33928 by only calling tsc_freq_mhz on timer init and storing the result. The change caused an error on Drallion where coreboot could not communicate with the TPM on a cold boot causing the system to not boot. BUG=b:144002424 TEST=Repeatedly cold boot drallion without TPM errors Change-Id: I8e9edafa3007568e8d27e3c19c9fd6fa7637786c Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/cpu/x86/tsc/delay_tsc.c 1 file changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36664/1 diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 7aa887a..dcec4fb 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -18,9 +18,18 @@ #include <delay.h> #include <thread.h> +static unsigned long clocks_per_usec CAR_GLOBAL; + void init_timer(void) { - (void)tsc_freq_mhz(); + if (!car_get_var(clocks_per_usec)) + car_set_var(clocks_per_usec, tsc_freq_mhz()); +} + +static inline unsigned long get_clocks_per_usec(void) +{ + init_timer(); + return car_get_var(clocks_per_usec); } void udelay(unsigned int us) @@ -34,7 +43,7 @@ start = rdtscll(); clocks = us; - clocks *= tsc_freq_mhz(); + clocks *= get_clocks_per_usec(); current = rdtscll(); while ((current - start) < clocks) { cpu_relax(); @@ -72,7 +81,7 @@ current_tick = rdtscll(); ticks_elapsed = current_tick - mono_counter->last_value; - ticks_per_usec = tsc_freq_mhz(); + ticks_per_usec = get_clocks_per_usec(); /* Update current time and tick values only if a full tick occurred. */ if (ticks_elapsed >= ticks_per_usec) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e9edafa3007568e8d27e3c19c9fd6fa7637786c Gerrit-Change-Number: 36664 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: mb/asrock/h110m: fix bug with onboard LAN
by Maxim Polyakov (Code Review) 05 Dec '19

05 Dec '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36377 ) Change subject: mb/asrock/h110m: fix bug with onboard LAN ...................................................................... mb/asrock/h110m: fix bug with onboard LAN Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36377/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 4323028..8f64d02 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -219,10 +219,6 @@ # Enable Root port 6(x1) for LAN. register "PcieRpEnable[5]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[5]" = "1" - # Use SRCCLKREQ1# - register "PcieRpClkReqNumber[5]" = "1" # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[5]" = "1" # Enable Latency Tolerance Reporting Mechanism -- To view, visit https://review.coreboot.org/c/coreboot/+/36377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f Gerrit-Change-Number: 36377 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in em100[master]: WIP: code coverage
by Stefan Reinauer (Code Review) 05 Dec '19

05 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37123 ) Change subject: WIP: code coverage ...................................................................... WIP: code coverage Change-Id: I8752482bb89587bc448fe1c966bca40d8d1bdbb0 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M .gitignore M Makefile 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/23/37123/1 diff --git a/.gitignore b/.gitignore index c89766e..c111945 100644 --- a/.gitignore +++ b/.gitignore @@ -6,3 +6,5 @@ /EM100Pro.msi .dependencies *.o +*.gcda +*.gcno diff --git a/Makefile b/Makefile index 481dc02..ccb73c6 100644 --- a/Makefile +++ b/Makefile @@ -32,6 +32,8 @@ CFLAGS += -DXZ_DEC_X86 -DXZ_DEC_POWERPC -DXZ_DEC_IA64 -DXZ_DEC_ARM -DXZ_DEC_ARMTHUMB -DXZ_DEC_SPARC -DXZ_USE_CRC64 -DXZ_DEC_ANY_CHECK -Ixz # Remove after fixing CFLAGS += -Wno-sign-compare -Wno-discarded-qualifiers +# Code Coverage +CFLAGS += -fprofile-arcs -ftest-coverage LDFLAGS ?= LDFLAGS += $(shell $(PKG_CONFIG) --libs libusb-1.0) -- To view, visit https://review.coreboot.org/c/em100/+/37123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I8752482bb89587bc448fe1c966bca40d8d1bdbb0 Gerrit-Change-Number: 37123 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: sc7180: Add clock driver
by mturney mturney (Code Review) 04 Dec '19

04 Dec '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35496 ) Change subject: sc7180: Add clock driver ...................................................................... sc7180: Add clock driver Add support for clock driver for SC7180 Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/31083/6 Change-Id: I3f39252c887c36e8af43bc49289795000e4638d8 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Signed-off-by: srimuc <srimuc(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/clock.h 5 files changed, 468 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/35496/1 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index a973724..60ad516 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -7,12 +7,14 @@ bootblock-y += timer.c bootblock-y += gpio.c bootblock-y += spi.c +bootblock-y += clock.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ verstage-y += timer.c verstage-y += gpio.c verstage-y += spi.c +verstage-y += clock.c verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ @@ -23,6 +25,7 @@ romstage-y += ../common/mmu.c romstage-y += mmu.c romstage-y += spi.c +romstage-y += clock.c romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ @@ -31,6 +34,7 @@ ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += spi.c +ramstage-y += clock.c ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index b9b8660..f073449 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -14,9 +14,12 @@ */ #include <bootblock_common.h> +#include <soc/clock.h> #include <soc/mmu.h> +#include <soc/clock.h> void bootblock_soc_init(void) { sc7180_mmu_init(); + clock_init(); } diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c new file mode 100644 index 0000000..0ccbaa6 --- /dev/null +++ b/src/soc/qualcomm/sc7180/clock.c @@ -0,0 +1,251 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <commonlib/helpers.h> +#include <device/mmio.h> +#include <soc/clock.h> +#include <types.h> + +#define DIV(div) (2 * div - 1) + +struct clock_config qup_cfg[] = { + { + .hz = 7372800, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 384, + .n = 15625, + .d_2 = 15625, + }, + { + .hz = 19200 * KHz, + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + } +}; + +struct clock_config qspi_core_cfg[] = { + { + .hz = 19200 * KHz, + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(3), + }, + { + .hz = 150 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(2), + }, + { + .hz = 300 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + } +}; + +static int clock_configure_gpll0(void) +{ + write32(&gcc->gpll0.user_ctl_u, 0x00004805); + + /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ + setbits_le32(&gcc->gpll0.user_ctl, + 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); + + return 0; +} + +static int clock_configure_mnd(struct sc7180_clock *clk, uint32_t m, uint32_t n, + uint32_t d_2) +{ + setbits_le32(&clk->rcg.cfg, + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + + write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK); + write32(&clk->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); + write32(&clk->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); + + return 0; +} + +static int clock_configure_rcg(struct sc7180_rcg *clk, + struct clock_config *clk_cfg, + uint32_t hz, uint32_t num_perfs) +{ + uint32_t reg_val; + uint32_t idx; + + for (idx = 0; idx < num_perfs; idx++) + if (hz <= clk_cfg[idx].hz) + break; + + assert(hz == clk_cfg[idx].hz); + + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + /* Set clock config */ + write32(&clk->cfg, reg_val); + + /* Commit config to RCG */ + setbits_le32(&clk->cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return 0; +} + +static int clock_configure(struct sc7180_clock *clk, + struct clock_config *clk_cfg, + uint32_t hz, uint32_t num_perfs) +{ + uint32_t reg_val; + uint32_t idx; + + for (idx = 0; idx < num_perfs; idx++) + if (hz <= clk_cfg[idx].hz) + break; + + assert(hz == clk_cfg[idx].hz); + + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + /* Set clock config */ + write32(&clk->rcg.cfg, reg_val); + + if (clk_cfg[idx].m != 0) + clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, + clk_cfg[idx].d_2); + + /* Commit config to RCG*/ + setbits_le32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return 0; +} + +static bool clock_is_off(u32 *cbcr_addr) +{ + return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK); +} + +static int clock_enable_vote(void *cbcr_addr, void *vote_addr, + uint32_t vote_bit) +{ + /* Set clock vote bit */ + setbits_le32(vote_addr, BIT(vote_bit)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)) + ; + + return 0; +} + +static int clock_enable(void *cbcr_addr) +{ + /* Set clock enable bit */ + setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)) + ; + + return 0; +} + +void clock_reset_aop(void) +{ + /* Bring AOP out of RESET */ + clrbits_le32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); +} + +void clock_configure_qspi(uint32_t hz) +{ + clock_configure_rcg(&gcc->qspi_core, + qspi_core_cfg, hz, + ARRAY_SIZE(qspi_core_cfg)); + clock_enable(&gcc->qspi_cnoc_ahb_cbcr); + clock_enable(&gcc->qspi_core_cbcr); +} + +int clock_reset_bcr(void *bcr_addr, bool reset) +{ + struct sc7180_bcr *bcr = bcr_addr; + + if (reset) + setbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + else + clrbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + + return 0; +} + +void clock_configure_qup(int qup, uint32_t hz) +{ + int s = qup % QUP_WRAP1_S0; + struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + (struct sc7180_qupv3_clock *)&gcc->qup_wrap0_s[s] : + (struct sc7180_qupv3_clock *)&gcc->qup_wrap1_s[s]; + + clock_configure(&qup_clk->clk, qup_cfg, hz, ARRAY_SIZE(qup_cfg)); +} + +void clock_enable_qup(int qup) +{ + int s = qup % QUP_WRAP1_S0; + int clk_en_off = qup < QUP_WRAP1_S0 ? + QUPV3_WRAP0_CLK_ENA_S(s) : QUPV3_WRAP1_CLK_ENA_S(s); + struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + clock_enable_vote(&qup_clk->clk, &gcc->apcs_clk_br_en1, + clk_en_off); +} + +void clock_init(void) +{ + clock_configure_gpll0(); + + clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_S_AHB_CLK_ENA); + + clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_S_AHB_CLK_ENA); +} diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index 93f0481..308b2fb 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2018-2019 Qualcomm Technologies + * Copyright (c) 2019 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,4 +18,8 @@ #include <stdint.h> -#endif /* _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ */ +#define AOSS_CC_BASE 0x0C2A0000 +#define GCC_BASE 0x00100000 +#define QSPI_BASE 0x088DC000 + +#endif /* __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h new file mode 100644 index 0000000..d90779b --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/addressmap.h> +#include <types.h> + +#ifndef __SOC_QUALCOMM_SC7180_CLOCK_H__ +#define __SOC_QUALCOMM_SC7180_CLOCK_H__ + +#define QUPV3_WRAP_0_M_AHB_CLK_ENA 6 +#define QUPV3_WRAP_0_S_AHB_CLK_ENA 7 +#define QUPV3_WRAP0_CORE_2X_CLK_ENA 9 +#define QUPV3_WRAP0_CORE_CLK_ENA 8 +#define QUPV3_WRAP1_CORE_2X_CLK_ENA 18 +#define QUPV3_WRAP1_CORE_CLK_ENA 19 +#define QUPV3_WRAP_1_M_AHB_CLK_ENA 20 +#define QUPV3_WRAP_1_S_AHB_CLK_ENA 21 +#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) +#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) + +#define GPLL0_EVEN_HZ (300 * MHz) +#define GPLL0_MAIN_HZ (600 * MHz) +#define QUP_WRAP_CORE_2X_19_2MHZ (19200 * KHz) + +#define SRC_XO_19_2MHZ 0 +#define SRC_GPLL0_MAIN_600MHZ 1 +#define SRC_GPLL0_EVEN_300MHZ 6 + +#define AOP_RESET_SHFT 0 +#define RCG_MODE_DUAL_EDGE 2 + +struct sc7180_rcg { + u32 cmd; + u32 cfg; +}; + +struct sc7180_clock { + u32 cbcr; + struct sc7180_rcg rcg; + u32 m; + u32 n; + u32 d_2; +}; + +struct sc7180_qupv3_clock { + struct sc7180_clock clk; + u8 _res[0x130 - 0x18]; +}; + +struct sc7180_gpll { + u32 mode; + u32 l_val; + u32 cal_l_val; + u32 user_ctl; + u32 user_ctl_u; + u32 config_ctl; + u32 config_ctl_u; + u32 test_ctl; + u32 test_ctl_u; + u8 _res[0x1000 - 0x24]; +}; + +struct sc7180_gcc { + struct sc7180_gpll gpll0; + u8 _res0[0xf000 - 0x1000]; + u32 usb30_prim_bcr; + u8 _res3[0x17000 - 0xf004]; + u32 qup_wrap0_bcr; + u32 qup_wrap0_m_ahb_cbcr; + u32 qup_wrap0_s_ahb_cbcr; + u32 qup_wrap0_core_cbcr; + u32 qup_wrap0_core_cdivr; + u32 qup_wrap0_core_2x_cbcr; + struct sc7180_rcg qup_wrap0_core_2x; + u8 _res4[0x17030 - 0x17020]; + struct sc7180_qupv3_clock qup_wrap0_s[6]; + u8 _res5[0x18000 - 0x17750]; + u32 qup_wrap1_bcr; + u32 qup_wrap1_core_2x_cbcr; + u32 qup_wrap1_core_cbcr; + u32 qup_wrap1_m_ahb_cbcr; + u32 qup_wrap1_s_ahb_cbcr; + struct sc7180_qupv3_clock qup_wrap1_s[6]; + u8 _res6[0x18994 - 0x18734]; + u32 qup_wrap1_core_cdivr; + u8 _res7[0x4b000 - 0x18998]; + u32 qspi_bcr; + u32 qspi_cnoc_ahb_cbcr; + u32 qspi_core_cbcr; + struct sc7180_rcg qspi_core; + u8 _res8[0x50000 - 0x4b014]; + u32 usb3_phy_prim_bcr; + u32 usb3phy_phy_prim_bcr; + u32 usb3_dp_phy_prim_bcr; + u32 usb3_phy_sec_bcr; + u32 usb3phy_phy_sec_bcr; + u32 usb3_dp_phy_sec_bcr; + u8 _res9[0x52008 - 0x50018]; + u32 apcs_clk_br_en1; + u8 _res10[0x1000000 - 0x5200c]; +}; + +struct sc7180_aoss { + u8 _res[0x5002c]; + u32 aoss_cc_apcs_misc; +}; + +enum clk_ctl_gpll_user_ctl { + CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, + CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0, + CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1, + CLK_CTL_GPLL_PLLOUT_ODD_SHFT = 2 +}; + +enum clk_ctl_cfg_rcgr { + CLK_CTL_CFG_HW_CTL_BMSK = 0x100000, + CLK_CTL_CFG_HW_CTL_SHFT = 20, + CLK_CTL_CFG_MODE_BMSK = 0x3000, + CLK_CTL_CFG_MODE_SHFT = 12, + CLK_CTL_CFG_SRC_SEL_BMSK = 0x700, + CLK_CTL_CFG_SRC_SEL_SHFT = 8, + CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F, + CLK_CTL_CFG_SRC_DIV_SHFT = 0 +}; + +enum clk_ctl_cmd_rcgr { + CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000, + CLK_CTL_CMD_ROOT_OFF_SHFT = 31, + CLK_CTL_CMD_ROOT_EN_BMSK = 0x2, + CLK_CTL_CMD_ROOT_EN_SHFT = 1, + CLK_CTL_CMD_UPDATE_BMSK = 0x1, + CLK_CTL_CMD_UPDATE_SHFT = 0 +}; + +enum clk_ctl_cbcr { + CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000, + CLK_CTL_CBC_CLK_OFF_SHFT = 31, + CLK_CTL_CBC_CLK_EN_BMSK = 0x1, + CLK_CTL_CBC_CLK_EN_SHFT = 0 +}; + +enum clk_ctl_rcg_mnd { + CLK_CTL_RCG_MND_BMSK = 0xFFFF, + CLK_CTL_RCG_MND_SHFT = 0, +}; + +enum clk_ctl_bcr { + CLK_CTL_BCR_BLK_ARES_BMSK = 0x1, + CLK_CTL_BCR_BLK_ARES_SHFT = 0, +}; + +enum clk_qup { + QUP_WRAP0_S0, + QUP_WRAP0_S1, + QUP_WRAP0_S2, + QUP_WRAP0_S3, + QUP_WRAP0_S4, + QUP_WRAP0_S5, + QUP_WRAP1_S0, + QUP_WRAP1_S1, + QUP_WRAP1_S2, + QUP_WRAP1_S3, + QUP_WRAP1_S4, + QUP_WRAP1_S5, +}; + +struct clock_config { + uint32_t hz; + uint8_t src; + uint8_t div; + uint16_t m; + uint16_t n; + uint16_t d_2; +}; + +struct mdss_clock_config { + const char *clk_name; + uintptr_t rcgr; + uintptr_t cbcr; +}; + +static struct sc7180_gcc *const gcc = (void *)GCC_BASE; +static struct sc7180_aoss *const aoss = (void *)AOSS_CC_BASE; + +void clock_init(void); +void clock_reset_aop(void); +void clock_configure_qspi(uint32_t hz); +int clock_reset_bcr(void *bcr_addr, bool reset); +void clock_configure_qup(int qup, uint32_t hz); +void clock_enable_qup(int qup); + +#endif // __SOC_QUALCOMM_SC7180_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/35496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f39252c887c36e8af43bc49289795000e4638d8 Gerrit-Change-Number: 35496 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

5 21

Change in coreboot[master]: WIP: disable gpio gating
by Mathew King (Code Review) 04 Dec '19

04 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37253 ) Change subject: WIP: disable gpio gating ...................................................................... WIP: disable gpio gating Change-Id: I08be8e9db0e4c0c70e5adaf99e48bd76664150e0 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 5 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37253/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index ed44f4f..1ecd3f5 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -207,15 +207,11 @@ register "gpio_override_pm" = "1" # GPIO community PM configuration - register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | - MISCCFG_GPRTCDLCGEN | - MISCCFG_GSXSLCGEN | - MISCCFG_GPDPCGEN | - MISCCFG_GPDLCGEN" - register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" device cpu_cluster 0 on device lapic 0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/37253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08be8e9db0e4c0c70e5adaf99e48bd76664150e0 Gerrit-Change-Number: 37253 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: sb/amd/cimx/sb800: add C bootblock southbridge initialization
by Michał Żygowski (Code Review) 04 Dec '19

04 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37329 ) Change subject: sb/amd/cimx/sb800: add C bootblock southbridge initialization ...................................................................... sb/amd/cimx/sb800: add C bootblock southbridge initialization TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie81198f5034a84d319ee7143aa032433f82be254 --- M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/bootblock.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/37329/1 diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 418110b..ccb3a2a 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -16,6 +16,10 @@ # SB800 Platform Files +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +endif + romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c smbus_spd.c diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 28b37c3..110b7e10 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -114,3 +114,13 @@ enable_spi_fast_mode(); enable_clocks(); } + +#if !CONFIG(ROMCC_BOOTBLOCK) +#include <bootblock_common.h> +#include <arch/io.h> + +void bootblock_soc_early_init(void) +{ + bootblock_southbridge_init(); +} +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie81198f5034a84d319ee7143aa032433f82be254 Gerrit-Change-Number: 37329 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: src/southbridge/amd/pi/hudson: add southbridge C bootblock initializa...
by Michał Żygowski (Code Review) 04 Dec '19

04 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37168 ) Change subject: src/southbridge/amd/pi/hudson: add southbridge C bootblock initialization ...................................................................... src/southbridge/amd/pi/hudson: add southbridge C bootblock initialization Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af --- M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/hudson.h 3 files changed, 55 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 0eccadb..8c47328 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,7 +28,12 @@ # #***************************************************************************** -bootblock-y += enable_usbdebug.c + +ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +bootblock-y += bootblock.c +bootblock-y += early_setup.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +endif romstage-y += early_setup.c romstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index f12cec8..d5faeb3 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -60,3 +60,48 @@ { hudson_enable_rom(); } + +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) + +#include <bootblock_common.h> +#include <arch/io.h> +#include <device/pci_ids.h> +#include <southbridge/amd/pi/hudson/hudson.h> + +void bootblock_soc_early_init(void) +{ + pci_devfn_t dev; + u32 data; + + bootblock_southbridge_init(); + hudson_lpc_decode(); + + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding for SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + + /* + * Enable FCH to decode TPM associated Memory and IO regions for vboot + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + */ + + data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); + data |= TPM_12_EN | TPM_LEGACY_EN; + pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xd2, 0xcd6); + outb(0x00, 0xcd7); +} +#endif diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 9511a6a..08adb84 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -117,6 +117,10 @@ #define LPC_ALT_WIDEIO1_ENABLE BIT(2) #define LPC_ALT_WIDEIO0_ENABLE BIT(0) +#define LPC_TRUSTED_PLATFORM_MODULE 0x7c +#define TPM_12_EN BIT(0) +#define TPM_LEGACY_EN BIT(2) + #define LPC_WIDEIO2_GENERIC_PORT 0x90 #define SPI_CNTRL0 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

5 34

Change in coreboot[master]: amd/agesa/family14: implement C bootblock
by Michał Żygowski (Code Review) 04 Dec '19

04 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37331 ) Change subject: amd/agesa/family14: implement C bootblock ...................................................................... amd/agesa/family14: implement C bootblock TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ibcaedba030d80a230eecfda6244ca54f7635d0b4 --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/Kconfig M src/northbridge/amd/agesa/family14/Makefile.inc A src/northbridge/amd/agesa/family14/bootblock.c A src/northbridge/amd/agesa/family14/nb_util.c M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family16kb/Kconfig 8 files changed, 104 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/37331/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 9956579..7e180df 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -59,7 +59,7 @@ config S3_DATA_POS hex - default 0xFFFF0000 + default 0xFFFE0000 config S3_DATA_SIZE int diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 518235b..6957b13 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -21,4 +21,16 @@ int default 36 +config AGESA_CAR_HEAP_BASE + hex + default 0x400000 + +config AGESA_HEAP_SIZE + hex + default 0x10000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + endif diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 50dba25..e1e129a 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -17,7 +17,6 @@ bool default CPU_AMD_AGESA select CBMEM_TOP_BACKUP - select ROMCC_BOOTBLOCK if NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc index ad39325..ca6439f 100644 --- a/src/northbridge/amd/agesa/family14/Makefile.inc +++ b/src/northbridge/amd/agesa/family14/Makefile.inc @@ -13,6 +13,13 @@ # GNU General Public License for more details. # +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +endif + +bootblock-y += nb_util.c +romstage-y += nb_util.c + romstage-y += dimmSpd.c ramstage-y += northbridge.c diff --git a/src/northbridge/amd/agesa/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c new file mode 100644 index 0000000..8ab789f --- /dev/null +++ b/src/northbridge/amd/agesa/family14/bootblock.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/amd/msr.h> +#include <device/pci_ops.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 + +#define AGESA_EARLY_VMTRR_FLASH 1 +#define AGESA_EARLY_VMTRR_CAR_HEAP 2 + +void amd_initmmio(void) +{ + msr_t msr; + msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); + int mtrr; + pci_devfn_t dev; + + msr.hi = 0; + msr.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN + | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; + wrmsr(MMIO_CONF_BASE, msr); + + /* Set Ontario Link Data */ + dev = PCI_DEV(0, 0, 0); + pci_write_config32(dev, 0xE0, 0x01308002); + pci_write_config32(dev, 0xE4, (AMD_APU_SSID << 0x10) | AMD_APU_SVID); + + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - AGESA_EARLY_VMTRR_FLASH; + set_var_mtrr(mtrr, OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - AGESA_EARLY_VMTRR_CAR_HEAP; + set_var_mtrr(mtrr, CONFIG_AGESA_CAR_HEAP_BASE, + CONFIG_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK); + + /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ + msr.lo = 0; + msr.hi = 0; + wrmsr(PS_CTL_REG, msr); +} diff --git a/src/northbridge/amd/agesa/family14/nb_util.c b/src/northbridge/amd/agesa/family14/nb_util.c new file mode 100644 index 0000000..cfb9afc --- /dev/null +++ b/src/northbridge/amd/agesa/family14/nb_util.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#define BIOSRAM_AP_ENTRY 0xec /* 4 bytes */ + +void *get_ap_entry_ptr(void) +{ + return (void *)biosram_read32(BIOSRAM_AP_ENTRY); +} + +void set_ap_entry_ptr(void *entry) +{ + biosram_write32(BIOSRAM_AP_ENTRY, (uintptr_t)entry); +} diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index a0841eb..32530f4 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -14,6 +14,7 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN bool + select ROMCC_BOOTBLOCK if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index 2be2fd3..c7e01ed 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -15,6 +15,7 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB bool + select ROMCC_BOOTBLOCK if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB -- To view, visit https://review.coreboot.org/c/coreboot/+/37331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcaedba030d80a230eecfda6244ca54f7635d0b4 Gerrit-Change-Number: 37331 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: google/endeavour: update GPIOs from schematic
by Jeff Chase (Code Review) 04 Dec '19

04 Dec '19

Jeff Chase has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36792 ) Change subject: google/endeavour: update GPIOs from schematic ...................................................................... google/endeavour: update GPIOs from schematic BUG=b:144307303 TEST=build Change-Id: Ide216ce1b393c1f49d6e59aa2c84a9a15d009794 --- M src/mainboard/google/fizz/variants/endeavour/gpio.c 1 file changed, 63 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36792/1 diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c index c11055c..42b0c34 100644 --- a/src/mainboard/google/fizz/variants/endeavour/gpio.c +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google Inc. + * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -40,10 +40,10 @@ /* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */ -/* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */ -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP0 */ PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), /* 7322_INTO */ +/* ISH_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */ +/* ISH_GP2 */ PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), /* 7322_INTO */ +/* ISH_GP3 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */ /* ISH_GP4 */ PAD_CFG_NC(GPP_A22), /* ISH_GP5 */ PAD_CFG_NC(GPP_A23), @@ -57,9 +57,11 @@ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_CLKREQ_SSD# */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, - NF1), /* PCIE_CLKREQ_NGFF1# */ -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */ -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */ + NF1), /* PCIE_CLKREQ_TPU# */ +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, + NF1), /* PCIE_CLKREQ_POE# */ +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, + NF1), /* PCIE_CLKREQ_TPU1# */ /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* PCIE_CLKREQ_WLAN# */ /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ @@ -74,13 +76,11 @@ NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ -/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU, - DEEP), /* VR_DISABLE_L */ -/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU, - DEEP), /* HWA_TRST_N */ +/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP98 */ +/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), +/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), /* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ -/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */ +/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP44 */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ @@ -90,15 +90,11 @@ /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), /* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */ -/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU, - DEEP), /* GPIO1 */ -/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU, - DEEP), /* GPIO2 */ -/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU, - DEEP), /* GPIO3 */ -/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU, - DEEP), /* GPIO4 */ +/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP99 */ +/* UART0_RXD */ PAD_CFG_NC(GPP_C8), +/* UART0_TXD */ PAD_CFG_NC(GPP_C9), +/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, @@ -107,21 +103,21 @@ DEEP), /* SKU_ID2 */ /* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* SKU_ID3 */ -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TPU_SDA */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* PCH_I2C_TPU_SCL */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SDA */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SCL */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ +/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP93 */ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */ -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */ -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */ -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */ +/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP106 */ +/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP102 */ +/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP104 */ +/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP105 */ +/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP91 */ /* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), /* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), /* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), @@ -140,57 +136,53 @@ /* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), /* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), /* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), -/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP121 */ -/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP122 */ -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */ -/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP258 */ +/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP100 */ +/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP90 */ +/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP101 */ +/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP94 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, - NF1), /* DB_PCIE_SATA#_DET */ -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* CPU_GP0 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 0, DEEP, + NONE), /* TPU_RST_PIN40 */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ -/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), -/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */ -/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */ -/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, - NF1), /* Rear Dual-Stack USB Ports */ +/* CPU_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E7, 0, DEEP, + NONE), /* TPU_RST_PIN42 */ +/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP96 */ +/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), /* T1037 */ +/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* T1025 */ /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, - NF1), /* Front USB Ports */ + NF1), /* Rear Dual-Stack USB Ports */ /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* Rear Single USB Port */ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, - NF1), /* INT_HDMI_HPD */ + NF1), /* DDI1_HDMI_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, - NF1), /* DDI2_HPD */ -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */ + NF1), /* DDI2_HDMI_HPD */ +/* DDPD_HPD2 */ PAD_CFG_GPI_APIC(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */ +/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP1021 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, - NF1), /* HDMI_DDCCLK_SW */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, - NF1), /* HDMI_DDCCLK_DATA */ -/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */ -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */ +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_DDCCLK_SW */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_DDCCLK_DATA */ +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDI2_DDCCLK_SW */ +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDI2_DDCDATA_SW */ /* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), /* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP191 */ -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP192 */ -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP190 */ -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */ -/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, - NF1), /* PCH_I2C2_H1_3V3_SDA */ -/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, - NF1), /* PCH_I2C2_H1_3V3_SCL */ -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP43 */ +/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP48 */ +/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP42 */ +/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP37 */ +/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), +/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), +/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* DDI1_I2C_7322_SDA */ +/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* DDI1_I2C_7322_SCL */ /* I2C4_SDA */ PAD_CFG_NC(GPP_F8), /* I2C4_SCL */ PAD_CFG_NC(GPP_F9), /* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, @@ -217,19 +209,19 @@ /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */ /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */ +/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP40 */ -/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */ +/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP23 */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ /* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */ +/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP22 */ /* RSVD */ PAD_CFG_NC(GPD7), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */ +/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP83 */ +/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP84 */ /* LANPHYC */ PAD_CFG_NC(GPD11), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/36792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide216ce1b393c1f49d6e59aa2c84a9a15d009794 Gerrit-Change-Number: 36792 Gerrit-PatchSet: 1 Gerrit-Owner: Jeff Chase <jnchase(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019