Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36377 )
Change subject: mb/asrock/h110m: fix bug with onboard LAN ......................................................................
mb/asrock/h110m: fix bug with onboard LAN
Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36377/1
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 4323028..8f64d02 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -219,10 +219,6 @@
# Enable Root port 6(x1) for LAN. register "PcieRpEnable[5]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[5]" = "1" - # Use SRCCLKREQ1# - register "PcieRpClkReqNumber[5]" = "1" # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[5]" = "1" # Enable Latency Tolerance Reporting Mechanism
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36377 )
Change subject: mb/asrock/h110m: disable CLKREQ to use onboard LAN ......................................................................
Patch Set 3:
This change is ready for review.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36377 )
Change subject: mb/asrock/h110m: disable CLKREQ to use onboard LAN ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36377/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36377/2//COMMIT_MSG@8 PS2, Line 8:
what's the bug and what's fixed with this commit?
Ack
Hello Patrick Rudolph, Felix Held, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36377
to look at the new patch set (#4).
Change subject: mb/asrock/h110m: disable CLKREQ to use onboard LAN ......................................................................
mb/asrock/h110m: disable CLKREQ to use onboard LAN
The PCH uses the SRCCLKREQ# pin to detect PCIe device in the slot in order to send clock signal to it. However, this logic is not required for the Realtek LAN device, since this chip is soldered to the board and always uses clocking. The chipset can't receive the clock request signal (most likely this pin isn't connected) and doesn't enable the CLK. Patch disables clock request logic for the PCIe root port 6 (x1) that is connected to the onboard Realtek LAN chip.
Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36377/4
Hello Patrick Rudolph, Felix Held, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36377
to look at the new patch set (#5).
Change subject: mb/asrock/h110m: disable CLKREQ to use onboard LAN ......................................................................
mb/asrock/h110m: disable CLKREQ to use onboard LAN
The PCH uses the SRCCLKREQ# pin to detect PCIe device in the slot in order to send clock signal to it. However, this logic is not required for the Realtek LAN device, since this chip is soldered to the board and always uses clocking. The chipset can't receive the clock request signal (most likely this pin isn't connected) and doesn't enable the CLK. For this reason, the device is broken during the initialization phase. The patch disables clock request logic for the PCH PCIe port 6 to initialize the onboard LAN device correctly.
Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36377/5
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36377 )
Change subject: mb/asrock/h110m: disable CLKREQ to use onboard LAN ......................................................................
Patch Set 5: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36377 )
Change subject: mb/asrock/h110m: disable CLKREQ to use onboard LAN ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/36377/5/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/36377/5/src/mainboard/asrock/h110m/... PS5, Line 221: register "PcieRpEnable[5]" = "1" I would be explicit and state that clock request is disabled.
# Disable CLKREQ#, onboard LAN is always present register "PcieRpClkReqSupport[5]" = "0"
Hello Patrick Rudolph, Felix Held, Angel Pons, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36377
to look at the new patch set (#6).
Change subject: mb/asrock/h110m: disable CLKREQ to use onboard LAN ......................................................................
mb/asrock/h110m: disable CLKREQ to use onboard LAN
The PCH uses the SRCCLKREQ# pin to detect PCIe device in the slot in order to send clock signal to it. However, this logic is not required for the Realtek LAN device, since this chip is soldered to the board and always uses clocking. The chipset can't receive the clock request signal (most likely this pin isn't connected) and doesn't enable the CLK. For this reason, the device is broken during the initialization phase. The patch disables clock request logic for the PCH PCIe port 6 to initialize the onboard LAN device correctly.
Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 2 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36377/6
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36377 )
Change subject: mb/asrock/h110m: disable CLKREQ to use onboard LAN ......................................................................
Patch Set 6:
(1 comment)
Thanks for the review
https://review.coreboot.org/c/coreboot/+/36377/5/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/36377/5/src/mainboard/asrock/h110m/... PS5, Line 221: register "PcieRpEnable[5]" = "1"
I would be explicit and state that clock request is disabled. […]
Done
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36377 )
Change subject: mb/asrock/h110m: disable CLKREQ to use onboard LAN ......................................................................
Patch Set 6: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36377 )
Change subject: mb/asrock/h110m: disable CLKREQ to use onboard LAN ......................................................................
mb/asrock/h110m: disable CLKREQ to use onboard LAN
The PCH uses the SRCCLKREQ# pin to detect PCIe device in the slot in order to send clock signal to it. However, this logic is not required for the Realtek LAN device, since this chip is soldered to the board and always uses clocking. The chipset can't receive the clock request signal (most likely this pin isn't connected) and doesn't enable the CLK. For this reason, the device is broken during the initialization phase. The patch disables clock request logic for the PCH PCIe port 6 to initialize the onboard LAN device correctly.
Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36377 Reviewed-by: Patrick Rudolph siro@das-labor.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 2 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index bd51e40..bf4bec0 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -219,10 +219,8 @@
# Enable Root port 6(x1) for LAN. register "PcieRpEnable[5]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[5]" = "1" - # Use SRCCLKREQ1# - register "PcieRpClkReqNumber[5]" = "1" + # Disable CLKREQ#, since onboard LAN is always present + register "PcieRpClkReqSupport[5]" = "0" # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[5]" = "1" # Enable Latency Tolerance Reporting Mechanism
-
Angel Pons (Code Review) -
Felix Held (Code Review)
-
Maxim Polyakov (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)