coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

1 participants
2418 discussions

Change in coreboot[master]: mb/google/poppy: add VBTs for remaining variants
by Matt DeVillier (Code Review) 17 Dec '19

17 Dec '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37311 ) Change subject: mb/google/poppy: add VBTs for remaining variants ...................................................................... mb/google/poppy: add VBTs for remaining variants Add VBT files for Atlas, Nocturne, Rammus, and Soraka variants. Extracted from ChromeOS recovery images for the respective boards. Change-Id: Icba2741e0b7309c22c027f956cd20cec78f34052 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/poppy/Kconfig A src/mainboard/google/poppy/variants/atlas/data.vbt A src/mainboard/google/poppy/variants/nocturne/data.vbt A src/mainboard/google/poppy/variants/rammus/data.vbt A src/mainboard/google/poppy/variants/soraka/data.vbt 5 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37311/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index e8fb38d..9fafef7 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -10,7 +10,6 @@ select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_NAMI || BOARD_GOOGLE_NAUTILUS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_KABYLAKE @@ -145,6 +144,7 @@ select EXCLUDE_NATIVE_SD_INTERFACE select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select INCLUDE_NHLT_BLOBS_ATLAS if USE_BLOBS + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_SPI_TPM_CR50 select VARIANT_HAS_CAMERA_ACPI @@ -163,6 +163,7 @@ select DRIVERS_SPI_ACPI select EXCLUDE_NATIVE_SD_INTERFACE select INCLUDE_NHLT_BLOBS_NAMI if USE_BLOBS + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_SPI_TPM_CR50 config VARIANT_SPECIFIC_OPTIONS_NAUTILUS @@ -171,6 +172,7 @@ select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 select INCLUDE_NHLT_BLOBS_NAUTILUS if USE_BLOBS + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_I2C_TPM_CR50 select VARIANT_HAS_CAMERA_ACPI @@ -185,6 +187,7 @@ select EXCLUDE_NATIVE_SD_INTERFACE select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select INCLUDE_NHLT_BLOBS_NOCTURNE if USE_BLOBS + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_SPI_TPM_CR50 select NO_FADT_8042 select VARIANT_HAS_CAMERA_ACPI @@ -197,6 +200,7 @@ select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select INCLUDE_NHLT_BLOBS_RAMMUS if USE_BLOBS + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_SPI_TPM_CR50 config VARIANT_SPECIFIC_OPTIONS_SORAKA @@ -204,6 +208,7 @@ select DRIVERS_I2C_MAX98927 select NO_FADT_8042 select MAINBOARD_HAS_I2C_TPM_CR50 + select INTEL_GMA_HAVE_VBT select VARIANT_HAS_CAMERA_ACPI config VBOOT diff --git a/src/mainboard/google/poppy/variants/atlas/data.vbt b/src/mainboard/google/poppy/variants/atlas/data.vbt new file mode 100644 index 0000000..850375e --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nocturne/data.vbt b/src/mainboard/google/poppy/variants/nocturne/data.vbt new file mode 100644 index 0000000..4d9293e --- /dev/null +++ b/src/mainboard/google/poppy/variants/nocturne/data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/rammus/data.vbt b/src/mainboard/google/poppy/variants/rammus/data.vbt new file mode 100644 index 0000000..5fc6e1c --- /dev/null +++ b/src/mainboard/google/poppy/variants/rammus/data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/soraka/data.vbt b/src/mainboard/google/poppy/variants/soraka/data.vbt new file mode 100644 index 0000000..4156bde --- /dev/null +++ b/src/mainboard/google/poppy/variants/soraka/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/37311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icba2741e0b7309c22c027f956cd20cec78f34052 Gerrit-Change-Number: 37311 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: security/vboot: Boot to Recovery Mode if no RW slot present
by Bill XIE (Code Review) 17 Dec '19

17 Dec '19

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34977 ) Change subject: security/vboot: Boot to Recovery Mode if no RW slot present ...................................................................... security/vboot: Boot to Recovery Mode if no RW slot present Currently, even if there is no RW slot present, vboot will still try to find one to boot, result in an infinite boot loop. This change explicitly allows a coreboot build with vboot but without RW slot to make use of vboot only for measured boot, by performing "Recovery mode" boot, with stages and payloads in the RO slot. Change-Id: Ica98afd6aeb5328515df0c11e974cc9b3e8cdde1 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/security/vboot/vboot_logic.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/34977/1 diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 7f00df5..48fd6db 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -347,7 +347,9 @@ "Initializing measured boot mode failed!"); } - if (get_recovery_mode_switch()) { + /* Boot to Recovery Mode if no RW slot present */ + if (!CONFIG(VBOOT_SLOTS_RW_A) || + get_recovery_mode_switch()) { ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; if (CONFIG(VBOOT_DISABLE_DEV_ON_RECOVERY)) ctx.flags |= VB2_CONTEXT_DISABLE_DEVELOPER_MODE; -- To view, visit https://review.coreboot.org/c/coreboot/+/34977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica98afd6aeb5328515df0c11e974cc9b3e8cdde1 Gerrit-Change-Number: 34977 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: src/soc/intel/(cnl,skl,icl): Remove, and call send_heci_reset_message...
by Sridhar Siricilla (Code Review) 16 Dec '19

16 Dec '19

Hello Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35228 to review the following change. Change subject: src/soc/intel/(cnl,skl,icl): Remove, and call send_heci_reset_message() defined in common code ...................................................................... src/soc/intel/(cnl,skl,icl): Remove, and call send_heci_reset_message() defined in common code Removed send_heci_reset_message() from socs(cnl/skl/icl), and made changes to call function send_heci_reset_req_message() defined in the common code. Change-Id: I691fc0610356ef1f64ffa7cc4fe7a39b1344cc16 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: sridhar <sridhar.siricilla(a)intel.com> --- M src/soc/intel/cannonlake/reset.c M src/soc/intel/icelake/reset.c M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/me.c 4 files changed, 3 insertions(+), 166 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35228/1 diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index e92396f3..e01c22c 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -22,65 +22,10 @@ #include <string.h> #include <soc/pci_devs.h> -/* Reset Request */ -#define MKHI_GLOBAL_RESET 0x0b -#define MKHI_STATUS_SUCCESS 0 - -#define GR_ORIGIN_BIOS_MEM_INIT 0x01 -#define GR_ORIGIN_BIOS_POST 0x02 -#define GR_ORIGIN_MEBX 0x03 - -#define GLOBAL_RST_TYPE 0x01 - -#define BIOS_HOST_ADD 0x00 -#define HECI_MKHI_ADD 0x07 - -static int send_heci_reset_message(void) -{ - int status; - struct reset_reply { - u8 group_id; - u8 command; - u8 reserved; - u8 result; - } __packed reply; - struct reset_message { - u8 group_id; - u8 cmd; - u8 reserved; - u8 result; - u8 req_origin; - u8 reset_type; - } __packed; - struct reset_message msg = { - .cmd = MKHI_GLOBAL_RESET, - .req_origin = GR_ORIGIN_BIOS_POST, - .reset_type = GLOBAL_RST_TYPE - }; - size_t reply_size; - - heci_reset(); - - status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADD, HECI_MKHI_ADD); - if (status != 1) - return -1; - - reply_size = sizeof(reply); - memset(&reply, 0, reply_size); - if (!heci_receive(&reply, &reply_size)) - return -1; - if (reply.result != MKHI_STATUS_SUCCESS) { - printk(BIOS_DEBUG, "Returned Mkhi Status is not success!\n"); - return -1; - } - printk(BIOS_DEBUG, "Heci receive success!\n"); - return 0; -} - void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (!send_heci_reset_message()) + if (!send_heci_reset_req_message(GLOBAL_RESET)) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c index 470b5f4..d83b3ee 100644 --- a/src/soc/intel/icelake/reset.c +++ b/src/soc/intel/icelake/reset.c @@ -22,65 +22,10 @@ #include <string.h> #include <soc/pci_devs.h> -/* Reset Request */ -#define MKHI_GLOBAL_RESET 0x0b -#define MKHI_STATUS_SUCCESS 0 - -#define GR_ORIGIN_BIOS_MEM_INIT 0x01 -#define GR_ORIGIN_BIOS_POST 0x02 -#define GR_ORIGIN_MEBX 0x03 - -#define GLOBAL_RST_TYPE 0x01 - -#define BIOS_HOST_ADD 0x00 -#define HECI_MKHI_ADD 0x07 - -static int send_heci_reset_message(void) -{ - int status; - struct reset_reply { - u8 group_id; - u8 command; - u8 reserved; - u8 result; - } __packed reply; - struct reset_message { - u8 group_id; - u8 cmd; - u8 reserved; - u8 result; - u8 req_origin; - u8 reset_type; - } __packed; - struct reset_message msg = { - .cmd = MKHI_GLOBAL_RESET, - .req_origin = GR_ORIGIN_BIOS_POST, - .reset_type = GLOBAL_RST_TYPE - }; - size_t reply_size; - - heci_reset(); - - status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADD, HECI_MKHI_ADD); - if (status != 1) - return -1; - - reply_size = sizeof(reply); - memset(&reply, 0, reply_size); - if (!heci_receive(&reply, &reply_size)) - return -1; - if (reply.result != MKHI_STATUS_SUCCESS) { - printk(BIOS_DEBUG, "Returned Mkhi Status is not success!\n"); - return -1; - } - printk(BIOS_DEBUG, "Heci receive success!\n"); - return 0; -} - void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (!send_heci_reset_message()) + if (!send_heci_reset_req_message(GLOBAL_RESET)) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index fbe5033..bec54d8 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -197,17 +197,8 @@ #define MKHI_GEN_GROUP_ID 0xff -/* Reset Request */ -#define MKHI_GLOBAL_RESET 0x0b - #define MKHI_GET_FW_VERSION 0x02 -#define GR_ORIGIN_BIOS_MEM_INIT 0x01 -#define GR_ORIGIN_BIOS_POST 0x02 -#define GR_ORIGIN_MEBX 0x03 - -#define GLOBAL_RST_TYPE 0x01 - #define BIOS_HOST_ADD 0x00 #define HECI_MKHI_ADD 0x07 diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index e8d75e3..fde4b13 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -431,50 +431,6 @@ } } -static int send_heci_reset_message(void) -{ - int status; - struct reset_reply { - u8 group_id; - u8 command; - u8 reserved; - u8 result; - } __packed reply; - struct reset_message { - u8 group_id; - u8 cmd; - u8 reserved; - u8 result; - u8 req_origin; - u8 reset_type; - } __packed; - struct reset_message msg = { - .cmd = MKHI_GLOBAL_RESET, - .req_origin = GR_ORIGIN_BIOS_POST, - .reset_type = GLOBAL_RST_TYPE - }; - size_t reply_size; - - heci_reset(); - - status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADD, HECI_MKHI_ADD); - if (!status) - return -1; - - reply_size = sizeof(reply); - memset(&reply, 0, reply_size); - status = heci_receive(&reply, &reply_size); - if (!status) - return -1; - /* get reply result from HECI MSG */ - if (reply.result) { - printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); - return -1; - } - printk(BIOS_DEBUG, "%s: Exit with Success\n", __func__); - return 0; -} - int send_global_reset(void) { int status = -1; @@ -486,7 +442,7 @@ goto ret; /* ME should be in Normal Mode for this command */ - status = send_heci_reset_message(); + status = send_heci_reset_req_message(GLOBAL_RESET); ret: return status; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I691fc0610356ef1f64ffa7cc4fe7a39b1344cc16 Gerrit-Change-Number: 35228 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

7 44

Change in coreboot[master]: drivers/intel/fsp1_1: Drop unused function
by Arthur Heymans (Code Review) 16 Dec '19

16 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36370 ) Change subject: drivers/intel/fsp1_1: Drop unused function ...................................................................... drivers/intel/fsp1_1: Drop unused function Change-Id: Ide336fb900360c446bffcc5ca31bf51e7746cae1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/include/fsp/util.h 2 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/36370/1 diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 2889f3f..f2c8a4d 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -280,10 +280,3 @@ } } } - -__attribute__((cdecl)) size_t fsp_write_line(uint8_t *buffer, - size_t number_of_bytes) -{ - console_write_line(buffer, number_of_bytes); - return number_of_bytes; -} diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index dca6d56..73b156f 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -96,15 +96,6 @@ void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start); void *get_first_guid_hob(const EFI_GUID *guid); -/* - * Writes number_of_bytes data bytes from buffer to the console. - * The number of bytes actually written to the console is returned. - * - * If number_of_bytes is zero, don't output any data but instead wait until - * the console has output all data, then return 0. - */ -__attribute__((cdecl)) size_t fsp_write_line(uint8_t *buffer, - size_t number_of_bytes); asmlinkage void chipset_teardown_car_main(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/36370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide336fb900360c446bffcc5ca31bf51e7746cae1 Gerrit-Change-Number: 36370 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sc7180: clock: Add support for QUP DFSR configuration
by mturney mturney (Code Review) 16 Dec '19

16 Dec '19

Hello Taniya Das, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37305 to review the following change. Change subject: sc7180: clock: Add support for QUP DFSR configuration ...................................................................... sc7180: clock: Add support for QUP DFSR configuration Support configuring the qup dfsr registers. Tested: validated DFSR clock configuration and M/N/D values. Change-Id: I146ac7c2197606965265f2a770769312af76041e Signed-off-by: Taniya Das <tdas(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/include/soc/clock.h 2 files changed, 108 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/37305/1 diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 97b7b28..658f883 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -60,6 +60,61 @@ } }; +struct clock_config qup_wrap_cfg[] = { + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = 32 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 8, + .n = 75, + .d_2 = 150, + }, + { + .hz = 48 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 4, + .n = 25, + .d_2 = 50, + }, + { + .hz = 64 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 16, + .n = 75, + .d_2 = 150, + }, + { + .hz = 96 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 8, + .n = 25, + .d_2 = 50, + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(3), + }, + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, +}; + static int clock_configure_gpll0(void) { setbits_le32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT); @@ -173,6 +228,39 @@ return 0; } +void clock_configure_dfsr(int qup) +{ + int idx, s = qup % QUP_WRAP1_S0; + uint32_t reg_val; + struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + setbits_le32(&qup_clk->dfsr_clk.cmd_dfsr, BIT(CLK_CTL_CMD_DFSR_SHFT)); + + for (idx = 0; idx < ARRAY_SIZE(qup_wrap_cfg); idx++) { + reg_val = (qup_wrap_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (qup_wrap_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + write32(&qup_clk->dfsr_clk.perf_dfsr[idx], reg_val); + + if (qup_wrap_cfg[idx].m == 0) + continue; + + setbits_le32(&qup_clk->dfsr_clk.cmd_dfsr, + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + + reg_val = qup_wrap_cfg[idx].m & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_m_dfsr[idx], reg_val); + + reg_val = ~(qup_wrap_cfg[idx].n - qup_wrap_cfg[idx].m) + & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_n_dfsr[idx], reg_val); + + reg_val = ~(qup_wrap_cfg[idx].d_2) & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_d_dfsr[idx], reg_val); + } +} + void clock_configure_qup(int qup, uint32_t hz) { int s = qup % QUP_WRAP1_S0; diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index 39cde8c..2e44b60 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -56,9 +56,22 @@ u32 d_2; }; +struct sc7180_dfsr_clock { + u32 cmd_dfsr; + u8 _res0[0x20 - 0x1c]; + u32 perf_dfsr[8]; + u8 _res1[0x60 - 0x40]; + u32 perf_m_dfsr[8]; + u8 _res2[0xa0 - 0x80]; + u32 perf_n_dfsr[8]; + u8 _res3[0xe0 - 0xc0]; + u32 perf_d_dfsr[8]; + u8 _res4[0x130 - 0x100]; +}; + struct sc7180_qupv3_clock { struct sc7180_mnd_clock mnd_clk; - u8 _res[0x130 - 0x18]; + struct sc7180_dfsr_clock dfsr_clk; }; struct sc7180_gpll { @@ -171,6 +184,11 @@ CLK_CTL_BCR_BLK_ARES_SHFT = 0, }; +enum clk_ctl_dfsr { + CLK_CTL_CMD_DFSR_BMSK = 0x1, + CLK_CTL_CMD_DFSR_SHFT = 0, +}; + enum clk_qup { QUP_WRAP0_S0, QUP_WRAP0_S1, @@ -210,5 +228,6 @@ int clock_reset_bcr(void *bcr_addr, bool reset); void clock_configure_qup(int qup, uint32_t hz); void clock_enable_qup(int qup); +void clock_configure_dfsr(int qup); #endif // __SOC_QUALCOMM_SC7180_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/37305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I146ac7c2197606965265f2a770769312af76041e Gerrit-Change-Number: 37305 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/common/block/chip/Kconfig: Fix minor whitespace
by HIMANSHU SAHDEV (Code Review) 16 Dec '19

16 Dec '19

HIMANSHU SAHDEV has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35291 ) Change subject: soc/intel/common/block/chip/Kconfig: Fix minor whitespace ...................................................................... soc/intel/common/block/chip/Kconfig: Fix minor whitespace Change-Id: I662420e6e05a6489950c583dfd37df5826153214 Signed-off-by: Himanshu Sahdev aka CunningLearner <sahdev.himan(a)gmail.com> --- M src/soc/intel/common/block/chip/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/35291/1 diff --git a/src/soc/intel/common/block/chip/Kconfig b/src/soc/intel/common/block/chip/Kconfig index 273d088..8021c24 100644 --- a/src/soc/intel/common/block/chip/Kconfig +++ b/src/soc/intel/common/block/chip/Kconfig @@ -1,4 +1,4 @@ config SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG bool help - Intel Processor common soc/ chip configuration support + Intel Processor common soc/chip configuration support -- To view, visit https://review.coreboot.org/c/coreboot/+/35291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I662420e6e05a6489950c583dfd37df5826153214 Gerrit-Change-Number: 35291 Gerrit-PatchSet: 1 Gerrit-Owner: HIMANSHU SAHDEV <sahdev.himan(a)gmail.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: AGESA,binaryPI: Disable boards from build
by Kyösti Mälkki (Code Review) 15 Dec '19

15 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37355 ) Change subject: AGESA,binaryPI: Disable boards from build ...................................................................... AGESA,binaryPI: Disable boards from build As per the 4.11 release requirement, C_ENVIRONMENT_BOOTBLOCK=y is a mandatory feature, which most AGESA and binaryPI boards lack. Disable all AGESA and binaryPI platforms, (except xxxx), from the build for the time being. The Kconfig symbol has been flipped, ROMCC_BOOTBLOCK=n is the same mandated feature as C_ENVIRONMENT_BOOTBLOCK=y. If a platform does not reach ROMCC_BOOTBLOCK=n within a reasonable timeframe both the mainboard and the respective unused platform support code will get removed. Change-Id: I7fceb0370f7f4f5f52080277c5d21615d3ab3454 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/bettong/Kconfig M src/mainboard/amd/db-ft3b-lc/Kconfig M src/mainboard/amd/inagua/Kconfig M src/mainboard/amd/inagua/Kconfig.name M src/mainboard/amd/lamar/Kconfig M src/mainboard/amd/olivehill/Kconfig M src/mainboard/amd/olivehill/Kconfig.name M src/mainboard/amd/olivehillplus/Kconfig M src/mainboard/amd/parmer/Kconfig M src/mainboard/amd/parmer/Kconfig.name M src/mainboard/amd/persimmon/Kconfig M src/mainboard/amd/persimmon/Kconfig.name M src/mainboard/amd/south_station/Kconfig M src/mainboard/amd/south_station/Kconfig.name M src/mainboard/amd/thatcher/Kconfig M src/mainboard/amd/thatcher/Kconfig.name M src/mainboard/amd/union_station/Kconfig M src/mainboard/amd/union_station/Kconfig.name M src/mainboard/asrock/e350m1/Kconfig M src/mainboard/asrock/e350m1/Kconfig.name M src/mainboard/asrock/imb-a180/Kconfig M src/mainboard/asrock/imb-a180/Kconfig.name M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/am1i-a/Kconfig.name M src/mainboard/asus/f2a85-m/Kconfig M src/mainboard/asus/f2a85-m/Kconfig.name M src/mainboard/bap/Kconfig M src/mainboard/bap/ode_e20XX/Kconfig M src/mainboard/bap/ode_e20XX/Kconfig.name M src/mainboard/biostar/Kconfig M src/mainboard/biostar/a68n_5200/Kconfig M src/mainboard/biostar/a68n_5200/Kconfig.name M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/biostar/am1ml/Kconfig.name M src/mainboard/elmex/Kconfig M src/mainboard/elmex/pcm205400/Kconfig M src/mainboard/elmex/pcm205400/Kconfig.name M src/mainboard/elmex/pcm205401/Kconfig M src/mainboard/elmex/pcm205401/Kconfig.name M src/mainboard/gizmosphere/Kconfig M src/mainboard/gizmosphere/gizmo/Kconfig M src/mainboard/gizmosphere/gizmo/Kconfig.name M src/mainboard/gizmosphere/gizmo2/Kconfig M src/mainboard/gizmosphere/gizmo2/Kconfig.name M src/mainboard/hp/abm/Kconfig M src/mainboard/hp/abm/Kconfig.name M src/mainboard/hp/pavilion_m6_1035dx/Kconfig M src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name M src/mainboard/jetway/Kconfig M src/mainboard/jetway/nf81-t56n-lf/Kconfig M src/mainboard/jetway/nf81-t56n-lf/Kconfig.name M src/mainboard/lenovo/g505s/Kconfig M src/mainboard/lenovo/g505s/Kconfig.name M src/mainboard/lippert/Kconfig M src/mainboard/lippert/frontrunner-af/Kconfig M src/mainboard/lippert/frontrunner-af/Kconfig.name M src/mainboard/lippert/toucan-af/Kconfig M src/mainboard/lippert/toucan-af/Kconfig.name M src/mainboard/msi/ms7721/Kconfig M src/mainboard/msi/ms7721/Kconfig.name M src/mainboard/pcengines/Kconfig M src/mainboard/pcengines/apu1/Kconfig M src/mainboard/pcengines/apu1/Kconfig.name M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Kconfig.name 65 files changed, 212 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/37355/1 diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index f5f37ce..fb78610 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00660F01 select NORTHBRIDGE_AMD_PI_00660F01 select SOUTHBRIDGE_AMD_PI_KERN diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index b83a525..7c6a9c6 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 541868b..a5ba07e 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_INAGUA + def_bool n + if BOARD_AMD_INAGUA config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/inagua/Kconfig.name b/src/mainboard/amd/inagua/Kconfig.name index 668b22a..1784fe6 100644 --- a/src/mainboard/amd/inagua/Kconfig.name +++ b/src/mainboard/amd/inagua/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_INAGUA - bool "Inagua" +#config BOARD_AMD_INAGUA +# bool"Inagua" diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index 1d3e0f6..e6990de 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00630F01 select NORTHBRIDGE_AMD_PI_00630F01 select SOUTHBRIDGE_AMD_PI_BOLTON diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 806fdbd..2b2ea3d 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_OLIVEHILL + def_bool n + if BOARD_AMD_OLIVEHILL config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/amd/olivehill/Kconfig.name b/src/mainboard/amd/olivehill/Kconfig.name index fd1a713..d065472 100644 --- a/src/mainboard/amd/olivehill/Kconfig.name +++ b/src/mainboard/amd/olivehill/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_OLIVEHILL - bool "Olive Hill" +#config BOARD_AMD_OLIVEHILL +# bool"Olive Hill" diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 230dc4b..e250fd9 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index dde58a6..acf2918 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_PARMER + def_bool n + if BOARD_AMD_PARMER config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/parmer/Kconfig.name b/src/mainboard/amd/parmer/Kconfig.name index 3aedc95..0771468 100644 --- a/src/mainboard/amd/parmer/Kconfig.name +++ b/src/mainboard/amd/parmer/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_PARMER - bool "Parmer" +#config BOARD_AMD_PARMER +# bool"Parmer" diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 005741e..f243f0f 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_PERSIMMON + def_bool n + if BOARD_AMD_PERSIMMON config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/persimmon/Kconfig.name b/src/mainboard/amd/persimmon/Kconfig.name index ba24b13a..d50ebbe 100644 --- a/src/mainboard/amd/persimmon/Kconfig.name +++ b/src/mainboard/amd/persimmon/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_PERSIMMON - bool "Persimmon" +#config BOARD_AMD_PERSIMMON +# bool"Persimmon" diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index f10ff7a..42841cb 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_SOUTHSTATION + def_bool n + if BOARD_AMD_SOUTHSTATION config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/south_station/Kconfig.name b/src/mainboard/amd/south_station/Kconfig.name index 0cc745e..f8f1404 100644 --- a/src/mainboard/amd/south_station/Kconfig.name +++ b/src/mainboard/amd/south_station/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_SOUTHSTATION - bool "Southstation" +#config BOARD_AMD_SOUTHSTATION +# bool"Southstation" diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index e11d0ea..a700be4 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_THATCHER + def_bool n + if BOARD_AMD_THATCHER config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/thatcher/Kconfig.name b/src/mainboard/amd/thatcher/Kconfig.name index aff5246..b57bdb9 100644 --- a/src/mainboard/amd/thatcher/Kconfig.name +++ b/src/mainboard/amd/thatcher/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_THATCHER - bool "Thatcher" +#config BOARD_AMD_THATCHER +# bool"Thatcher" diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index f03fb08..1532d34 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_UNIONSTATION + def_bool n + if BOARD_AMD_UNIONSTATION config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/union_station/Kconfig.name b/src/mainboard/amd/union_station/Kconfig.name index 9af3c82..b4dc5365 100644 --- a/src/mainboard/amd/union_station/Kconfig.name +++ b/src/mainboard/amd/union_station/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_UNIONSTATION - bool "Unionstation" +#config BOARD_AMD_UNIONSTATION +# bool"Unionstation" diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 86eaac8..44782a2 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_ASROCK_E350M1 + def_bool n + if BOARD_ASROCK_E350M1 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/asrock/e350m1/Kconfig.name b/src/mainboard/asrock/e350m1/Kconfig.name index a9a6ec5..f2f3058 100644 --- a/src/mainboard/asrock/e350m1/Kconfig.name +++ b/src/mainboard/asrock/e350m1/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ASROCK_E350M1 - bool "E350M1" +#config BOARD_ASROCK_E350M1 +# bool"E350M1" diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index 883b1c0..a059823 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_ASROCK_IMB_A180 + def_bool n + if BOARD_ASROCK_IMB_A180 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/asrock/imb-a180/Kconfig.name b/src/mainboard/asrock/imb-a180/Kconfig.name index 9680e4d..880d4eb 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig.name +++ b/src/mainboard/asrock/imb-a180/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ASROCK_IMB_A180 - bool "IMB-A180" +#config BOARD_ASROCK_IMB_A180 +# bool"IMB-A180" diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index c3f21e9..3271956 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -1,9 +1,12 @@ +config BOARD_ASUS_AM1I_A + def_bool n + if BOARD_ASUS_AM1I_A config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/asus/am1i-a/Kconfig.name b/src/mainboard/asus/am1i-a/Kconfig.name index 840e821..57c6227 100644 --- a/src/mainboard/asus/am1i-a/Kconfig.name +++ b/src/mainboard/asus/am1i-a/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ASUS_AM1I_A - bool "AM1I-A" +#config BOARD_ASUS_AM1I_A +# bool"AM1I-A" diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index cd10e53..15ecff1 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -14,11 +14,20 @@ # GNU General Public License for more details. # +config BOARD_ASUS_F2A85_M + def_bool n + +config BOARD_ASUS_F2A85_M_PRO + def_bool n + +config BOARD_ASUS_F2A85_M_LE + def_bool n + if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/asus/f2a85-m/Kconfig.name b/src/mainboard/asus/f2a85-m/Kconfig.name index 8a3d7ef..a35b2de 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig.name +++ b/src/mainboard/asus/f2a85-m/Kconfig.name @@ -1,8 +1,8 @@ -config BOARD_ASUS_F2A85_M - bool "F2A85-M" +#config BOARD_ASUS_F2A85_M +# bool"F2A85-M" -config BOARD_ASUS_F2A85_M_PRO - bool "F2A85-M PRO" +#config BOARD_ASUS_F2A85_M_PRO +# bool"F2A85-M PRO" -config BOARD_ASUS_F2A85_M_LE - bool "F2A85-M LE" +#config BOARD_ASUS_F2A85_M_LE +# bool"F2A85-M LE" diff --git a/src/mainboard/bap/Kconfig b/src/mainboard/bap/Kconfig index 9af496d..a638509 100644 --- a/src/mainboard/bap/Kconfig +++ b/src/mainboard/bap/Kconfig @@ -13,6 +13,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## + if VENDOR_BAP choice @@ -20,6 +21,9 @@ source "src/mainboard/bap/*/Kconfig.name" +config BAP_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/bap/*/Kconfig" diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index a62fba8..d172bc6 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_ODE_E20XX + def_bool n + if BOARD_ODE_E20XX config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/bap/ode_e20XX/Kconfig.name b/src/mainboard/bap/ode_e20XX/Kconfig.name index a482846..54ddcac 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig.name +++ b/src/mainboard/bap/ode_e20XX/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ODE_E20XX - bool "ODE_e20xx" +#config BOARD_ODE_E20XX +# bool"ODE_e20xx" diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 43896a3..6469d4e 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -20,6 +20,9 @@ source "src/mainboard/biostar/*/Kconfig.name" +config BIOSTAR_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/biostar/*/Kconfig" diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig index a452569..f608513 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ b/src/mainboard/biostar/a68n_5200/Kconfig @@ -15,11 +15,14 @@ # GNU General Public License for more details. # +config BOARD_BIOSTAR_A68N5200 + def_bool n + if BOARD_BIOSTAR_A68N5200 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/biostar/a68n_5200/Kconfig.name b/src/mainboard/biostar/a68n_5200/Kconfig.name index 52a7f15..6d765d2 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig.name +++ b/src/mainboard/biostar/a68n_5200/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_BIOSTAR_A68N5200 - bool "A68N-5200" +#config BOARD_BIOSTAR_A68N5200 +# bool"A68N-5200" diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 4ea5ddc..995d479 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -14,12 +14,15 @@ # GNU General Public License for more details. # +config BOARD_BIOSTAR_AM1ML + def_bool n + if BOARD_BIOSTAR_AM1ML config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/biostar/am1ml/Kconfig.name b/src/mainboard/biostar/am1ml/Kconfig.name index ccfa6fe..0980c2e 100644 --- a/src/mainboard/biostar/am1ml/Kconfig.name +++ b/src/mainboard/biostar/am1ml/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_BIOSTAR_AM1ML - bool "AM1ML" +#config BOARD_BIOSTAR_AM1ML +# bool"AM1ML" diff --git a/src/mainboard/elmex/Kconfig b/src/mainboard/elmex/Kconfig index d1fc9ad..54217ea 100644 --- a/src/mainboard/elmex/Kconfig +++ b/src/mainboard/elmex/Kconfig @@ -5,6 +5,9 @@ source "src/mainboard/elmex/*/Kconfig.name" +config ELMEX_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/elmex/*/Kconfig" diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index 14254ca..e94a6d8 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -13,6 +13,9 @@ # GNU General Public License for more details. # +config BOARD_ELMEX_PCM205400 + def_bool n + if BOARD_ELMEX_PCM205400 config MAINBOARD_PART_NUMBER @@ -29,7 +32,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/elmex/pcm205400/Kconfig.name b/src/mainboard/elmex/pcm205400/Kconfig.name index 445b588..6488992 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig.name +++ b/src/mainboard/elmex/pcm205400/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ELMEX_PCM205400 - bool "pcm205400" +#config BOARD_ELMEX_PCM205400 +# bool"pcm205400" diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig index a9bbe6e..15c741a 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -13,6 +13,9 @@ # GNU General Public License for more details. # +config BOARD_ELMEX_PCM205401 + def_bool n + if BOARD_ELMEX_PCM205401 config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name index f70b215..050b94c 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig.name +++ b/src/mainboard/elmex/pcm205401/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ELMEX_PCM205401 - bool "pcm205401" +#config BOARD_ELMEX_PCM205401 +# bool "pcm205401" diff --git a/src/mainboard/gizmosphere/Kconfig b/src/mainboard/gizmosphere/Kconfig index 6022bf6..00781ef 100644 --- a/src/mainboard/gizmosphere/Kconfig +++ b/src/mainboard/gizmosphere/Kconfig @@ -20,6 +20,9 @@ source "src/mainboard/gizmosphere/*/Kconfig.name" +config GIZMOSPHERE_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/gizmosphere/*/Kconfig" diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index e1c286b..4ba3e04 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_GIZMOSPHERE_GIZMO + def_bool n + if BOARD_GIZMOSPHERE_GIZMO config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig.name b/src/mainboard/gizmosphere/gizmo/Kconfig.name index 97c1f79..a57495c 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig.name +++ b/src/mainboard/gizmosphere/gizmo/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_GIZMOSPHERE_GIZMO - bool "Gizmo" +#config BOARD_GIZMOSPHERE_GIZMO +# bool"Gizmo" diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 27a3b35..5e26052 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_GIZMOSPHERE_GIZMO2 + def_bool n + if BOARD_GIZMOSPHERE_GIZMO2 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig.name b/src/mainboard/gizmosphere/gizmo2/Kconfig.name index a3bae57..29688e2 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig.name +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_GIZMOSPHERE_GIZMO2 - bool "Gizmo2" +#config BOARD_GIZMOSPHERE_GIZMO2 +# bool"Gizmo2" diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index a179dbe..12c1c90 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_HP_ABM + def_bool n + if BOARD_HP_ABM config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/hp/abm/Kconfig.name b/src/mainboard/hp/abm/Kconfig.name index 4ace573..27eda0c 100644 --- a/src/mainboard/hp/abm/Kconfig.name +++ b/src/mainboard/hp/abm/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_HP_ABM - bool "ABM" +#config BOARD_HP_ABM +# bool"ABM" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 05ea52f..12c3bd0 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -13,12 +13,15 @@ # GNU General Public License for more details. # +config BOARD_HP_PAVILION_M6_1035DX + def_bool n + if BOARD_HP_PAVILION_M6_1035DX config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name index a736970..0ba7278 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_HP_PAVILION_M6_1035DX - bool "Pavilion m6 1035dx" +#config BOARD_HP_PAVILION_M6_1035DX +# bool"Pavilion m6 1035dx" diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig index 63b3acc..530700d 100644 --- a/src/mainboard/jetway/Kconfig +++ b/src/mainboard/jetway/Kconfig @@ -5,6 +5,9 @@ source "src/mainboard/jetway/*/Kconfig.name" +config JETWAY_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/jetway/*/Kconfig" diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index 95d3b7e..dfa01b9 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_JETWAY_NF81_T56N_LF + def_bool n + if BOARD_JETWAY_NF81_T56N_LF config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name index 2e660f9..0b67627 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_JETWAY_NF81_T56N_LF - bool "NF81_T56N_LF" +#config BOARD_JETWAY_NF81_T56N_LF +# bool"NF81_T56N_LF" diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 815c7d5..0579bd4 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -13,12 +13,15 @@ # GNU General Public License for more details. # +config BOARD_LENOVO_G505S + def_bool n + if BOARD_LENOVO_G505S config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/lenovo/g505s/Kconfig.name b/src/mainboard/lenovo/g505s/Kconfig.name index ff3ca28..a2182d9 100644 --- a/src/mainboard/lenovo/g505s/Kconfig.name +++ b/src/mainboard/lenovo/g505s/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_LENOVO_G505S - bool "AMD G505s" +#config BOARD_LENOVO_G505S +# bool"AMD G505s" diff --git a/src/mainboard/lippert/Kconfig b/src/mainboard/lippert/Kconfig index 76cf305..e45fc3e 100644 --- a/src/mainboard/lippert/Kconfig +++ b/src/mainboard/lippert/Kconfig @@ -5,6 +5,9 @@ choice prompt "Mainboard model" +config LIPPERT_BOARDS_DISABLED + bool "Boards from vendor are disabled" + source "src/mainboard/lippert/*/Kconfig.name" endchoice diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 8b33810..4a007bf 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_LIPPERT_FRONTRUNNER_AF + def_bool n + if BOARD_LIPPERT_FRONTRUNNER_AF config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig.name b/src/mainboard/lippert/frontrunner-af/Kconfig.name index 2a8cba5..1939264 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig.name +++ b/src/mainboard/lippert/frontrunner-af/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_LIPPERT_FRONTRUNNER_AF - bool "FrontRunner-AF aka ADLINK CoreModule2-GF" +#config BOARD_LIPPERT_FRONTRUNNER_AF +# bool"FrontRunner-AF aka ADLINK CoreModule2-GF" diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index 146af07..b62da2e 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_LIPPERT_TOUCAN_AF + def_bool n + if BOARD_LIPPERT_TOUCAN_AF config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/toucan-af/Kconfig.name b/src/mainboard/lippert/toucan-af/Kconfig.name index 3481f92..6eceb51 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig.name +++ b/src/mainboard/lippert/toucan-af/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_LIPPERT_TOUCAN_AF - bool "Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" +#config BOARD_LIPPERT_TOUCAN_AF +# bool"Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig index 779d3b1..5f68e75 100644 --- a/src/mainboard/msi/ms7721/Kconfig +++ b/src/mainboard/msi/ms7721/Kconfig @@ -16,11 +16,14 @@ # GNU General Public License for more details. # +config BOARD_MSI_MS7721 + def_bool n + if BOARD_MSI_MS7721 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/msi/ms7721/Kconfig.name b/src/mainboard/msi/ms7721/Kconfig.name index bce5b99..9ed5473 100644 --- a/src/mainboard/msi/ms7721/Kconfig.name +++ b/src/mainboard/msi/ms7721/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_MSI_MS7721 - bool "MS-7721 (FM2-A75MA-E35)" +#config BOARD_MSI_MS7721 +# bool"MS-7721 (FM2-A75MA-E35)" diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig index e173054..6bb4a60 100644 --- a/src/mainboard/pcengines/Kconfig +++ b/src/mainboard/pcengines/Kconfig @@ -5,6 +5,9 @@ source "src/mainboard/pcengines/*/Kconfig.name" +config PCENGINES_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/pcengines/*/Kconfig" diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 1684236..5c968c8 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_PCENGINES_APU1 + def_bool n + if BOARD_PCENGINES_APU1 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/pcengines/apu1/Kconfig.name b/src/mainboard/pcengines/apu1/Kconfig.name index 265f7a6..d7546ba 100644 --- a/src/mainboard/pcengines/apu1/Kconfig.name +++ b/src/mainboard/pcengines/apu1/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_PCENGINES_APU1 - bool "APU1" +#config BOARD_PCENGINES_APU1 +# bool"APU1" diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 5ecdb88..8670eea 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -15,12 +15,24 @@ # GNU General Public License for more details. # +config BOARD_PCENGINES_APU2 + def_bool n + +config BOARD_PCENGINES_APU3 + def_bool n + +config BOARD_PCENGINES_APU4 + def_bool n + +config BOARD_PCENGINES_APU5 + def_bool n + if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \ BOARD_PCENGINES_APU5 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name index 45ec16f..857a782 100644 --- a/src/mainboard/pcengines/apu2/Kconfig.name +++ b/src/mainboard/pcengines/apu2/Kconfig.name @@ -1,11 +1,11 @@ -config BOARD_PCENGINES_APU2 - bool "APU2" +#config BOARD_PCENGINES_APU2 +# bool"APU2" -config BOARD_PCENGINES_APU3 - bool "APU3" +#config BOARD_PCENGINES_APU3 +# bool"APU3" -config BOARD_PCENGINES_APU4 - bool "APU4" +#config BOARD_PCENGINES_APU4 +# bool"APU4" -config BOARD_PCENGINES_APU5 - bool "APU5" +#config BOARD_PCENGINES_APU5 +# bool"APU5" -- To view, visit https://review.coreboot.org/c/coreboot/+/37355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fceb0370f7f4f5f52080277c5d21615d3ab3454 Gerrit-Change-Number: 37355 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: sb/intel/*: Remove romcc guards
by Arthur Heymans (Code Review) 14 Dec '19

14 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37217 ) Change subject: sb/intel/*: Remove romcc guards ...................................................................... sb/intel/*: Remove romcc guards These platforms now use a GCC compiled bootblock. Change-Id: I9a0139f497fe84860664195ed6584f90daecec16 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/ibexpeak/pch.h 4 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37217/1 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 127fb61..089d458 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -90,10 +90,8 @@ int oc_pin; }; -#ifndef __ROMCC__ void pch_enable(struct device *dev); extern const struct southbridge_usb_port mainboard_usb_ports[14]; -#endif void early_usb_init(const struct southbridge_usb_port *portmap); diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 77931cb..d35b215 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,10 +19,8 @@ #if !defined(__ACPI__) -#ifndef __ROMCC__ #include <device/device.h> void i82371eb_enable(struct device *dev); -#endif void i82371eb_hard_reset(void); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3d27faa..0516a7a 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -34,10 +34,8 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#ifndef __ROMCC__ #include <device/device.h> void i82801gx_enable(struct device *dev); -#endif void enable_smbus(void); void i82801gx_lpc_setup(void); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 9ee76f2..5785ef1 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -89,11 +89,9 @@ void early_usb_init(const struct southbridge_usb_port *portmap); -#ifndef __ROMCC__ extern const struct southbridge_usb_port mainboard_usb_ports[14]; #include <device/device.h> void pch_enable(struct device *dev); -#endif #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a0139f497fe84860664195ed6584f90daecec16 Gerrit-Change-Number: 37217 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: AGESA: Select CBMEM_STAGE_CACHE with HAVE_ACPI_RESUME
by Kyösti Mälkki (Code Review) 13 Dec '19

13 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36708 ) Change subject: AGESA: Select CBMEM_STAGE_CACHE with HAVE_ACPI_RESUME ...................................................................... AGESA: Select CBMEM_STAGE_CACHE with HAVE_ACPI_RESUME Fix regression with commit 0a4457f lib/stage_cache: Refactor Kconfig options AGESA platforms fail to resume from S3 suspend with CBMEM_STAGE_CACHE=n. For the time being the root cause is unknown. Change-Id: I11db0c883b6e39473d02e92b14cb3c6302aa728e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/36708/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index b1fde2d..d14eb40 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -27,6 +27,7 @@ select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME + select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE -- To view, visit https://review.coreboot.org/c/coreboot/+/36708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11db0c883b6e39473d02e92b14cb3c6302aa728e Gerrit-Change-Number: 36708 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: Doc/mb/gigabyte/ga-h61m-s2pv: Correct IFD section
by Angel Pons (Code Review) 13 Dec '19

13 Dec '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36301 ) Change subject: Doc/mb/gigabyte/ga-h61m-s2pv: Correct IFD section ...................................................................... Doc/mb/gigabyte/ga-h61m-s2pv: Correct IFD section Change-Id: Ic94dd7381e9a107081011d083286d27005148557 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/mainboard/gigabyte/ga-h61m-s2pv.md 1 file changed, 7 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/36301/1 diff --git a/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md b/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md index 06c0ff7..501f38d 100644 --- a/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md +++ b/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md @@ -39,27 +39,22 @@ The original IFD defines the BIOS region as the whole flash chip. While this is not an issue if flashing a complete image, it confuses flashrom and trashes the -flash chip's contents when using the --ifd option. However, this can be easily -fixed by reading the IFD with flashrom, editing the correct values into it with -ifdtool and then reflashing it. - -Create a layout.txt with the following contents: +flash chip's contents when using the `--ifd` option. A possible workaround is +to create a `layout.txt` file with a non-overlapping BIOS region: 00000000:00000fff fd 00180000:003fffff bios 00001000:0017ffff me -After that, simply run: +After that, use flashrom with the new layout file. For example, to backup the +BIOS region and then flash a `coreboot.rom` to it, do: ```bash -sudo flashrom -p internal --ifd -i fd -r ifd.rom -ifdtool -n layout.txt ifd.rom -sudo flashrom -p internal --ifd -i fd -w ifd.rom.new +sudo flashrom -p internal -l layout.txt -i bios -r backup.rom +sudo flashrom -p internal -l layout.txt -i bios -w coreboot.rom ``` -After flashing, power cycle the computer to ensure the new IFD is being used. -If only a reboot is done, the old IFD layout is still seen by flashrom, even if -the IFD on the flash chip is correctly defining the new region layout. +Modifying the ## Technology -- To view, visit https://review.coreboot.org/c/coreboot/+/36301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic94dd7381e9a107081011d083286d27005148557 Gerrit-Change-Number: 36301 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 11

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2019