coreboot-gerrit November 2019

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Change in coreboot[master]: [WIP]Docs/project_ideas.md: Add a memtest libpayload based payload
by Arthur Heymans (Code Review) 28 Feb '20

28 Feb '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36747 ) Change subject: [WIP]Docs/project_ideas.md: Add a memtest libpayload based payload ...................................................................... [WIP]Docs/project_ideas.md: Add a memtest libpayload based payload Change-Id: Iebdb75b99e18fe92aa4c801769532781edf44d9a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/contributing/project_ideas.md 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/36747/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 21a756d..d2134ce 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -201,3 +201,21 @@ ### Mentors * Ron Minnich <rminnich(a)google.com> + +## Libpayload based memtest payload +[Memtest86+](https://www.memtest.org/) has some limitations: first and +foremost it only works on x86, while it can print to serial console the +GUI only works in legacy VGA mode. + +This project would involve porting the memtest suite to libpayload and +build a payload around it. + +### Requirements +* coreboot knowledge: Should know how to build coreboot images and + include payloads. +* other knowledge: Knowledge on how dram works is a plus. +* hardware requirements: Initial work can happen on qemu targets, + being able to test on coreboot supported hardware is a plus. + +### Mentors +* TODO -- To view, visit https://review.coreboot.org/c/coreboot/+/36747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebdb75b99e18fe92aa4c801769532781edf44d9a Gerrit-Change-Number: 36747 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: src/soc/intel/common/cse: Add helper functions to support CSE FW update
by Sridhar Siricilla (Code Review) 18 Feb '20

18 Feb '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36786 ) Change subject: src/soc/intel/common/cse: Add helper functions to support CSE FW update ...................................................................... src/soc/intel/common/cse: Add helper functions to support CSE FW update Below helper functions are added: * cse_wait_opmode_soft_temp_disable() - It polls for CSE's operation mode 'Soft Temporary Disable". The CSE enters this mode when it boots from RO_BP1 region. * cse_check_opmode_soft_temp_disable() - It reads CSE's FWSTS1 register and checks for CSE's operation mode 'Soft Temporary Disable'. Change-Id: Ibdcf01f31b0310932b8e834ae83144f8a67f1fef Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/36786/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 247e60a..d7fd21b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -294,6 +294,35 @@ return 1; } +static int cse_check_opmode_soft_temp_disable(void) +{ + union me_hfsts1 hfs1; + + hfs1.data = me_read_config32(PCI_ME_HFSTS1); + + if (hfs1.fields.operation_mode == ME_HFS_TEMP_DISABLE) + return 1; + else + return 0; +} + +/* + * Polls for CSE's operation mode 'Soft Temporary Disable'. + * The CSE enters the operation mode when it boots from RO_BP1 region. + */ +uint8_t cse_wait_opmode_soft_temp_disable(void) +{ + struct stopwatch sw; + stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); + while (!check_cse_opmode_soft_disable_state()) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) + return 0; + } + + return 1; +} + static int wait_heci_ready(void) { struct stopwatch sw; -- To view, visit https://review.coreboot.org/c/coreboot/+/36786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdcf01f31b0310932b8e834ae83144f8a67f1fef Gerrit-Change-Number: 36786 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3
by Nicola Corna (Code Review) 17 Feb '20

17 Feb '20

Nicola Corna has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31470 Change subject: mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3 ...................................................................... mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3 thinkpad_acpi expects the battery hotkey (KEY_BATTERY) on scancode 0x01 (Fn-F2) and the lock hotkey (KEY_COFFEE) on scancode 0x02 (Fn-F3). This is true for most of the Thinkpads, however on the X1 Carbon Gen1 (and possibly others), the battery hotkey is not present and the lock one is instead on Fn-F3. Swap the RHK calls in _Q11 (Fn-F2) and _Q12 (Fn-F3) to fix the issue, so that the lock hotkey is on F3 and the battery one is on F2 (even if it's not marked so). Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Signed-off-by: Nicola Corna <nicola(a)corna.info> --- M src/ec/lenovo/h8/acpi/ec.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/31470/1 diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 327a2cf..6ffba5e 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -197,12 +197,20 @@ Method (_Q11, 0, NotSerialized) { +#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3) + ^HKEY.RHK (0x03) +#else ^HKEY.RHK (0x02) +#endif } Method (_Q12, 0, NotSerialized) { +#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3) + ^HKEY.RHK (0x02) +#else ^HKEY.RHK (0x03) +#endif } Method (_Q64, 0, NotSerialized) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index 8c9bd5a..2696607 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -20,6 +20,7 @@ #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 +#define EC_LENOVO_H8_SWAP_FNF2_FNF3 1 #include <arch/acpi.h> DefinitionBlock( -- To view, visit https://review.coreboot.org/c/coreboot/+/31470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Gerrit-Change-Number: 31470 Gerrit-PatchSet: 1 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: src/northbridge/amd/pi/00730F01/northbridge.c: enable ACS and AER for...
by Michał Żygowski (Code Review) 17 Feb '20

17 Feb '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35313 ) Change subject: src/northbridge/amd/pi/00730F01/northbridge.c: enable ACS and AER for PCIe ports ...................................................................... src/northbridge/amd/pi/00730F01/northbridge.c: enable ACS and AER for PCIe ports Currently it is impossible to enable ACS with AGESA by setting the correct bit for AmdInitMid phase. AGESA code path does not call the right function that enables these functionalities. Disabled ACS result in multiple PCIe devices to be assigned to the same IOMMU group. Without IOMMU group separation the devices cannot be passed through independently. Enable Access Control Services and Advanced Error Reporting for PCI Express bridges in order to have PCIe devices in separate IOMMU groups for correct passthrough. TEST=run dmesg on Debian Buster and check whether PCIe devices have separate groups Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I10a8eff0ba37196692f9db6519e498fe535ecd15 --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/35313/1 diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index ba17c61..fede1e9 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -783,6 +783,25 @@ pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + /* Select GPP link core IO Link Strap Control register 0xB0 */ + pci_write_config32(dev, 0xE0, 0x014000B0); + value = pci_read_config32(dev, 0xE4); + + /* Enable AER (bit 5) and ACS (bit 6 undocumented) */ + value |= (BIT(5) | BIT(6)); + pci_write_config32(dev, 0xE4, value); + + /* Select GPP link core Wrapper register 0x00 (undocumented) */ + pci_write_config32(dev, 0xE0, 0x01300000); + value = pci_read_config32(dev, 0xE4); + + /* Enable ACS capabilities straps including sub-items. From lspci it + * looks like these bits enable: Source Validation and Translation + * Blocking + */ + value |= (BIT(24) | BIT(25) | BIT(26)); + pci_write_config32(dev, 0xE4, value); + /* disable No Snoop */ dev = pcidev_on_root(1, 1); if (dev != NULL) { -- To view, visit https://review.coreboot.org/c/coreboot/+/35313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10a8eff0ba37196692f9db6519e498fe535ecd15 Gerrit-Change-Number: 35313 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/k8resdump: Remove util
by Arthur Heymans (Code Review) 17 Feb '20

17 Feb '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36085 ) Change subject: util/k8resdump: Remove util ...................................................................... util/k8resdump: Remove util AMD K8 support dropped. Change-Id: I94c38e588c0ebdc6b9e830067c935814a5d26b0a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D util/k8resdump/Makefile D util/k8resdump/description.md D util/k8resdump/k8resdump.c 3 files changed, 0 insertions(+), 177 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/36085/1 diff --git a/util/k8resdump/Makefile b/util/k8resdump/Makefile deleted file mode 100644 index a1d4dfa..0000000 --- a/util/k8resdump/Makefile +++ /dev/null @@ -1,61 +0,0 @@ -## -## Makefile for k8resdump utility -## -## (C) 2005 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -PROGRAM = k8resdump - -CC = gcc -INSTALL = /usr/bin/env install -PREFIX = /usr/local -#CFLAGS = -O2 -g -Wall -Werror -CFLAGS = -Os -Wall -Werror -OS_ARCH = $(shell uname) -ifeq ($(OS_ARCH), SunOS) -LDFLAGS = -lpci -else -LDFLAGS = -lpci -lz -static -endif - -OBJS = k8resdump.o - -all: pciutils dep $(PROGRAM) - -$(PROGRAM): $(OBJS) - $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) - -clean: - rm -f *.o *~ - -distclean: clean - rm -f $(PROGRAM) .dependencies - -dep: - @$(CC) -MM *.c > .dependencies - -pciutils: - @echo; echo -n "Checking for pciutils and zlib... " - @$(shell ( echo "#include <pci/pci.h>"; \ - echo "struct pci_access *pacc;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c ) - @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ - echo "found." || ( echo "not found."; echo; \ - echo "Please install pciutils-devel and zlib-devel."; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test; exit 1) - @rm -f .test.c .test - -.PHONY: all clean distclean dep pciutils - --include .dependencies diff --git a/util/k8resdump/description.md b/util/k8resdump/description.md deleted file mode 100644 index dd1f144..0000000 --- a/util/k8resdump/description.md +++ /dev/null @@ -1,2 +0,0 @@ -This program will dump the IO/memory/PCI resources from the K8 memory -controller `C` diff --git a/util/k8resdump/k8resdump.c b/util/k8resdump/k8resdump.c deleted file mode 100644 index 66d7060..0000000 --- a/util/k8resdump/k8resdump.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License v2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This program will dump the IO/memory/PCI resources from the K8 - * memory controller - */ - -#include <stdio.h> -#include <stdlib.h> -#include <stdint.h> -#include <unistd.h> -#include <sys/types.h> -#include <pci/pci.h> - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -static uint8_t dram_bases[] = - { 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78 }; -static uint8_t dram_limits[] = - { 0x44, 0x4C, 0x54, 0x5C, 0x64, 0x6C, 0x74, 0x7C }; -static uint8_t iomem_bases[] = - { 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0, 0xB8 }; -static uint8_t iomem_limits[] = - { 0x84, 0x8C, 0x94, 0x9C, 0xA4, 0xAC, 0xB4, 0xBC }; - -static uint8_t pciio_bases[] = { 0xC0, 0xC8, 0xD0, 0xD8 }; -static uint8_t pciio_limits[] = { 0xC4, 0xCC, 0xD4, 0xDC }; - -void print_info(struct pci_dev *dev) -{ - int i; - uint32_t regb, regl; - - for (i = 0; i < ARRAY_SIZE(dram_bases); i++) { - regb = pci_read_long(dev, dram_bases[i]); - regl = pci_read_long(dev, dram_limits[i]); - - printf - ("DRAM map: #%d 0x%04x000000 - 0x%04xffffff Access: %s/%s" - " IntlvEN:0x%x IntlvSEL:0x%x Dstnode:%d\n", - i, regb >> 16, regl >> 16, regb & 1 ? "R" : "", - regb & 2 ? "W" : "", (regb & 0x700) >> 8, - (regl & 0x700) >> 8, (regl & 0x7)); - } - - - for (i = 0; i < ARRAY_SIZE(iomem_bases); i++) { - regb = pci_read_long(dev, iomem_bases[i]); - regl = pci_read_long(dev, iomem_limits[i]); - - printf - ("MMIO map: #%d 0x%06x0000 - 0x%06xffff Access: %s/%s %s %s" - " %s Dstnode:%d DstLink %d\n", - i, regb >> 8, regl >> 8, regb & 1 ? "R" : "", - regb & 2 ? "W" : "", regb & 4 ? "CPU Dis" : "", - regb & 8 ? "Locked" : "", - regl & 0x80 ? "NonPosted" : "", regl & 0x7, - (regl & 0x30) >> 4); - } - - for (i = 0; i < ARRAY_SIZE(pciio_bases); i++) { - regb = pci_read_long(dev, pciio_bases[i]); - regl = pci_read_long(dev, pciio_limits[i]); - - printf - (" IO map: #%d 0x%03x000 - 0x%03xfff Access: %s/%s %s %s" - " Dstnode:%d DstLink %d\n", - i, (regb & ~0xff000000) >> 12, - (regl & ~0xff000000) >> 12, regb & 1 ? "R" : "", - regb & 2 ? "W" : "", regb & 0x20 ? "ISA" : "", - regb & 0x10 ? "VGA" : "", regl & 0x7, - (regl & 0x30) >> 4); - } - - -} - -int main(void) -{ - struct pci_access *pacc; - struct pci_dev *dev; - - if (getuid()) { - fprintf(stderr, "Please run me root, need access to all" - " PCI regs!\n"); - exit(1); - } - - pacc = pci_alloc(); - pci_init(pacc); - pci_scan_bus(pacc); - for (dev = pacc->devices; dev; dev = dev->next) { - pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_BASES | - PCI_FILL_CLASS); - if ((dev->vendor_id == 0x1022) /* AMD */ - && (dev->device_id == 0x1101)) { /* Address MAP */ - print_info(dev); - } - } - pci_cleanup(pacc); - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94c38e588c0ebdc6b9e830067c935814a5d26b0a Gerrit-Change-Number: 36085 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/apple/macbookair4_2: Add CMOS support
by Evgeny Zinoviev (Code Review) 17 Feb '20

17 Feb '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33045 Change subject: mb/apple/macbookair4_2: Add CMOS support ...................................................................... mb/apple/macbookair4_2: Add CMOS support Added CMOS support for MacBook Air 4,2. In future, I hope there will be more useful options available, because I'm working on macbooks support. Also, it may be necessary for hyper_threading support (#29669) once it will be ready. Change-Id: I369ed9aeff2098a4840918531be6a34cfc8d2a1e Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/apple/macbookair4_2/Kconfig A src/mainboard/apple/macbookair4_2/cmos.default A src/mainboard/apple/macbookair4_2/cmos.layout 3 files changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/33045/1 diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 4b2ee8f..263d550 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -14,6 +14,8 @@ select SYSTEM_TYPE_LAPTOP select GFX_GMA_INTERNAL_IS_EDP select MAINBOARD_HAS_LIBGFXINIT + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE config MAINBOARD_DIR string diff --git a/src/mainboard/apple/macbookair4_2/cmos.default b/src/mainboard/apple/macbookair4_2/cmos.default new file mode 100644 index 0000000..53e85a3 --- /dev/null +++ b/src/mainboard/apple/macbookair4_2/cmos.default @@ -0,0 +1 @@ +debug_level=Debug diff --git a/src/mainboard/apple/macbookair4_2/cmos.layout b/src/mainboard/apple/macbookair4_2/cmos.layout new file mode 100644 index 0000000..86d55b4 --- /dev/null +++ b/src/mainboard/apple/macbookair4_2/cmos.layout @@ -0,0 +1,97 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +# ----------------------------------------------------------------- +entries +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused +#400 8 r 0 reserved for century byte +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +# coreboot config options: EC +#411 1 e 8 first_battery +#412 1 e 1 bluetooth +#413 1 e 1 wwan +#414 1 e 1 touchpad +#415 1 e 1 wlan +#416 1 e 1 trackpoint +#417 1 e 1 fn_ctrl_swap +#418 1 e 1 sticky_fn +#419 2 e 13 usb_always_on +#421 1 e 9 sata_mode +#422 2 e 10 backlight +# coreboot config options: cpu +#424 8 r 0 unused +# coreboot config options: northbridge +#432 5 e 11 gfx_uma_size +#437 3 r 0 unused +#440 8 h 0 volume +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk +# coreboot config options: check sums +984 16 h 0 check_sum +# ----------------------------------------------------------------- +enumerations +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums +checksum 392 447 984 -- To view, visit https://review.coreboot.org/c/coreboot/+/33045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I369ed9aeff2098a4840918531be6a34cfc8d2a1e Gerrit-Change-Number: 33045 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: src/soc/intel/byatrail: Add minimal SMBus support
by Angel Pons (Code Review) 11 Feb '20

11 Feb '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34464 ) Change subject: src/soc/intel/byatrail: Add minimal SMBus support ...................................................................... src/soc/intel/byatrail: Add minimal SMBus support Change-Id: I6b7bdbc94cfbc9fbd8eda92ca924c74638388bfb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc A src/soc/intel/baytrail/smbus.c 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/34464/1 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 4b816a2..f5a1d81 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -40,6 +40,7 @@ select POSTCAR_CONSOLE select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR + select SOUTHBRIDGE_INTEL_COMMON_SMBUS config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 3ad6a8f..55af6e6 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -12,6 +12,7 @@ romstage-y += iosf.c romstage-y += memmap.c romstage-y += pmutil.c +romstage-y += smbus.c romstage-y += spi.c romstage-y += stage_cache.c romstage-y += tsc_freq.c @@ -42,6 +43,7 @@ ramstage-y += sata.c ramstage-y += scc.c ramstage-y += sd.c +ramstage-y += smbus.c ramstage-y += smm.c ramstage-y += southcluster.c ramstage-y += spi.c diff --git a/src/soc/intel/baytrail/smbus.c b/src/soc/intel/baytrail/smbus.c new file mode 100644 index 0000000..91dd173 --- /dev/null +++ b/src/soc/intel/baytrail/smbus.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2019 3mdeb + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/early_smbus.h> +#include <soc/iomap.h> +#include <southbridge/intel/common/smbus.h> + +u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) +{ + return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset); +} + +u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) +{ + return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7bdbc94cfbc9fbd8eda92ca924c74638388bfb Gerrit-Change-Number: 34464 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch: Override CPU flex ratio
by Subrata Banik (Code Review) 11 Feb '20

11 Feb '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36865 ) Change subject: mb/google/hatch: Override CPU flex ratio ...................................................................... mb/google/hatch: Override CPU flex ratio This patch overrides CPU flex ration on hatch in order to get better boot time numbers in vboot_reference TEST=Able to save ~100ms of platform boot time while running with lower cpu flex ratio Without this CL 1100:finished vboot kernel verification 802,443 (148,108) With this CL 1100:finished vboot kernel verification 698,382 (46,496) Change-Id: Idd1d1c0c04b1f742f17227a1335f27a956ee940d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/36865/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 6c0a94a..6db4581 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -22,6 +22,7 @@ select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_COMETLAKE select SYSTEM_TYPE_LAPTOP + select OVERRIDE_CPU_FLEX_RATIO if BOARD_GOOGLE_BASEBOARD_HATCH @@ -129,4 +130,8 @@ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH +config CPU_FLEX_RATIO + hex + default 5 + endif # BOARD_GOOGLE_BASEBOARD_HATCH -- To view, visit https://review.coreboot.org/c/coreboot/+/36865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd1d1c0c04b1f742f17227a1335f27a956ee940d Gerrit-Change-Number: 36865 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel: Drop unused file
by HAOUAS Elyes (Code Review) 09 Feb '20

09 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37161 ) Change subject: cpu/intel: Drop unused file ...................................................................... cpu/intel: Drop unused file Change-Id: I1b41ddc5e99838f0585089974e995f3de7be1791 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/cpu/intel/thermal_monitoring/thermal_monitoring.h 1 file changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/37161/1 diff --git a/src/cpu/intel/thermal_monitoring/thermal_monitoring.h b/src/cpu/intel/thermal_monitoring/thermal_monitoring.h deleted file mode 100644 index 5bb9cc2..0000000 --- a/src/cpu/intel/thermal_monitoring/thermal_monitoring.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define THERMAL_MONITORING_OFF 0 -#define THERMAL_MONITORING_SET 0x00000008 -#define MISC_ENABLE 0x01a0 -- To view, visit https://review.coreboot.org/c/coreboot/+/37161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b41ddc5e99838f0585089974e995f3de7be1791 Gerrit-Change-Number: 37161 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: src/southbridge/amd/pi/hudson/sata.c: set SATA in AHCI mode
by Piotr Kleinschmidt (Code Review) 09 Feb '20

09 Feb '20

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35891 ) Change subject: src/southbridge/amd/pi/hudson/sata.c: set SATA in AHCI mode ...................................................................... src/southbridge/amd/pi/hudson/sata.c: set SATA in AHCI mode The attempt to install pfSense ended up in a SATA driver error. Changing SATA mode from IDE to AHCI solved that issue. Change-Id: I1b0322392712d797dd5a8931150c8d0ff1b60940 Signed-off-by: Piotr Kleinschmidt <piotr.kleins(a)gmail.com> --- M src/southbridge/amd/pi/hudson/sata.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/35891/1 diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 08e967d..8e58390 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -32,6 +32,9 @@ #define UNLOCK_BIT (1<<0) #define SATA_CAPABILITIES_REG 0xFC #define CFG_CAP_SPM (1<<12) + #define SATA_REV_SUBCLASS_REG 0x08 + #define SUBCLASS_AHCI_MODE 0x60000 + #define SATA_PROGRAMIF_AHCI 0x100 volatile u32 *ahci_ptr = (u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00); @@ -45,6 +48,11 @@ /* set the SATA AHCI mode to allow port expanders */ *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM; + /* enable AHCI mode */ + temp = pci_read_config32(dev, SATA_REV_SUBCLASS_REG); + temp = (temp & 0xFF0070FF) | SUBCLASS_AHCI_MODE | SATA_PROGRAMIF_AHCI; + pci_write_config32(dev, SATA_REV_SUBCLASS_REG, temp); + /* lock the write-protect */ temp = pci_read_config32(dev, MISC_CONTROL_REG); temp &= ~UNLOCK_BIT; -- To view, visit https://review.coreboot.org/c/coreboot/+/35891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b0322392712d797dd5a8931150c8d0ff1b60940 Gerrit-Change-Number: 35891 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019