coreboot-gerrit November 2019

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Change in coreboot[master]: soc/intel/common/block/cse: Rename set_host_ready() to cse_set_host_r...
by Sridhar Siricilla (Code Review) 09 Feb '20

09 Feb '20

Hello Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37282 to review the following change. Change subject: soc/intel/common/block/cse: Rename set_host_ready() to cse_set_host_ready() ...................................................................... soc/intel/common/block/cse: Rename set_host_ready() to cse_set_host_ready() Below changes are done: 1. Rename set_host_ready() function to cse_set_host_ready() 2. Additional debug messages are added TEST=Build and Boot hatch board. Change-Id: Icfcf1631cc37faacdea9ad84be55f5710104bad5 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37282/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index f81411a..46ad8ce 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -272,7 +272,7 @@ } /* Makes the host ready to communicate with CSE */ -void set_host_ready(void) +void cse_set_host_ready(void) { uint32_t csr; csr = read_host_csr(); @@ -286,10 +286,13 @@ { struct stopwatch sw; stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); + printk(BIOS_ERR, "HECI: Wait 15 secs for CSE to enter SEC_OVERRIDE mode!\n"); while (!check_cse_sec_override_mode()) { udelay(HECI_DELAY); - if (stopwatch_expired(&sw)) + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: Timed out!\n"); return 0; + } } return 1; @@ -545,7 +548,7 @@ if (wait_heci_ready()) { /* Device is back on its imaginary feet, clear reset */ - set_host_ready(); + cse_set_host_ready(); return 1; } diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 4c00006..3c00b87 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -112,7 +112,7 @@ /* Makes the host ready to communicate with CSE*/ -void set_host_ready(void); +void cse_set_host_ready(void); /* * Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds. -- To view, visit https://review.coreboot.org/c/coreboot/+/37282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfcf1631cc37faacdea9ad84be55f5710104bad5 Gerrit-Change-Number: 37282 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

6 26

Change in ...coreboot[master]: security/intel/stm STM support
by Name of user not set (Code Review) 08 Feb '20

08 Feb '20

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33234 Change subject: security/intel/stm STM support ...................................................................... security/intel/stm STM support Initial commit for Coreboot STM supporX Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec --- M src/security/Kconfig M src/security/Makefile.inc A src/security/intel/stm/Kconfig A src/security/intel/stm/Makefile.inc A src/security/intel/stm/SmmStm.c A src/security/intel/stm/SmmStm.h A src/security/intel/stm/StmApi.h A src/security/intel/stm/StmPlatformResource.c A src/security/intel/stm/StmPlatformResource.h A src/security/intel/stm/StmPlatformSmm.c 10 files changed, 2,235 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/33234/1 diff --git a/src/security/Kconfig b/src/security/Kconfig index 6a334ac..e9b5225 100644 --- a/src/security/Kconfig +++ b/src/security/Kconfig @@ -14,3 +14,4 @@ source "src/security/vboot/Kconfig" source "src/security/tpm/Kconfig" +source "src/security/intel/stm/Kconfig" diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc index a940b82..e49c172 100644 --- a/src/security/Makefile.inc +++ b/src/security/Makefile.inc @@ -1,2 +1,4 @@ subdirs-y += vboot subdirs-y += tpm +subdirs-y += intel/stm + diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig new file mode 100644 index 0000000..e8eea02 --- /dev/null +++ b/src/security/intel/stm/Kconfig @@ -0,0 +1,17 @@ + +menu "SMI Transfer Monitor (STM)" + +config STM + bool "Enable STM" + default y + depends on (PLATFORM_USES_FSP2_0||PLATFORM_USES_FSP1_1||PLATFORM_USES_FSP1_0) + +if STM + +config MSEG_SIZE + hex "mseg size" + default 0x400000 + +endif #STM + +endmenu diff --git a/src/security/intel/stm/Makefile.inc b/src/security/intel/stm/Makefile.inc new file mode 100644 index 0000000..24d7bac --- /dev/null +++ b/src/security/intel/stm/Makefile.inc @@ -0,0 +1,16 @@ + +# put the stm where is can be found + +cbfs-files-y += stm.bin +stm.bin-file = stm.bin +stm.bin-type = raw + +ramstage-y += SmmStm.c +ramstage-y += StmPlatformSmm.c +ramstage-y += StmPlatformResource.c + +smm-y += StmPlatformResource.c +smm-y += SmmStm.c +smm-y += StmPlatformSmm.c + + diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c new file mode 100644 index 0000000..677d514 --- /dev/null +++ b/src/security/intel/stm/SmmStm.c @@ -0,0 +1,894 @@ +/** @file + + SMM STM support + + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <security/intel/stm/SmmStm.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/cr.h> +#include <string.h> +#include <cpu/x86/mp.h> +#include <console/console.h> + +#define TXT_EVTYPE_BASE 0x400 +#define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14) + +#define RDWR_ACCS 3 +#define FULL_ACCS 7 + +#define SIZE_4KB 0x00001000 +#define SIZE_4MB 0x00400000 + +#define IA32_PG_P (1<<0) +#define IA32_PG_RW (1<<1) +#define IA32_PG_PS (1<<7) + +#define STM_PAGE_SHIFT 12 +#define STM_PAGE_MASK 0xFFF +#define STM_SIZE_TO_PAGES(a) (((a) >> STM_PAGE_SHIFT) + (((a) & STM_PAGE_MASK) ? 1 : 0)) +#define STM_PAGES_TO_SIZE(a) ((a) << STM_PAGE_SHIFT) + +#define STM_ACCESS_DENIED 15 +#define STM_UNSUPPORTED 3 + +#define STM_BUFFER_TOO_SMALL 1 + +#define STM_SM_MONITOR_STATE_ENABLED 1 + +#define RESOURCEHEAPSIZE 4096 + +uint32_t GetVmcsSize(void); +void StmGen4GPageTableIa32(uint32_t PageTableBase); +void StmGen4GPageTableX64(uint32_t PageTableBase); +bool StmCheckStmImage(void * StmImage, uint32_t StmImageSize); +void StmLoadStmImage(void * StmImage, UINTN StmImageSize); + +bool HandleSingleResource(STM_RSC *Resource, STM_RSC *Record); +void AddSingleResource(STM_RSC *Resource); +void AddResource(STM_RSC *ResourceList, uint32_t NumEntries); +bool ValidateResource(STM_RSC *ResourceList, uint32_t NumEntries); +UINTN GetResourceSize(STM_RSC *ResourceList, uint32_t NumEntries); + +typedef struct { + + uint64_t VmcsRevisionID:31; + uint64_t AlwaysZero:1; + uint64_t VmcsSize:13; + uint64_t Reserved1:3; + uint64_t VmxonAddWidth:1; + uint64_t StmSupported:1; + uint64_t VmcsMemoryType:4; + uint64_t InOutReporting:1; + uint64_t MayClearDefaults:1; + uint64_t Reserved2:8; +} VMX_BASIC_MSR_BITS; + +typedef union { + VMX_BASIC_MSR_BITS bits; + uint64_t uint64; + msr_t msr; +} VMX_BASIC_MSR; + +typedef struct { + uint64_t valid:1; + uint64_t reserved1:1; + uint64_t VmxOffBlockSmi:1; + uint64_t reserved2:9; + uint64_t MsegAddress:20; + uint64_t reserved3:32; +} SMM_MONITOR_CTL_MSR_BITS; + +extern struct mp_state { + struct mp_ops ops; + int cpu_count; + uintptr_t perm_smbase; + size_t perm_smsize; + size_t smm_save_state_size; + int do_smm; +} mp_state; + +typedef union { + SMM_MONITOR_CTL_MSR_BITS bits; + uint64_t uint64; + msr_t msr; +} SMM_MONITOR_CTL_MSR; + +// +// Template of STM_RSC_END structure for copying. +// + +STM_RSC_END mRscEndNode = { + {END_OF_RESOURCES, sizeof(STM_RSC_END)}, +}; + +uint8_t *mStmResourcesPtr = NULL; +UINTN mStmResourceTotalSize = 0x0; +UINTN mStmResourceSizeUsed = 0x0; +UINTN mStmResourceSizeAvailable = 0x0; + +uint8_t StmResourceHeap[RESOURCEHEAPSIZE]; + +uint32_t mStmState = 0; + +/** + + Handle single Resource to see if it can be merged into Record. + + @param Resource A pointer to resource node to be added + @param Record A pointer to record node to be merged + + @retval true resource handled + @retval false resource is not handled + +**/ + +bool +HandleSingleResource( + STM_RSC *Resource, + STM_RSC *Record + ) +{ + uint64_t ResourceLo; + uint64_t ResourceHi; + uint64_t RecordLo; + uint64_t RecordHi; + + ResourceLo = 0; + ResourceHi = 0; + RecordLo = 0; + RecordHi = 0; + + // + // Calling code is responsible for making sure that + // Resource->Header.RscType == (*Record)->Header.RscType + // thus we use just one of them as switch variable. + // + + switch (Resource->Header.RscType) { + case MEM_RANGE: + case MMIO_RANGE: + ResourceLo = Resource->Mem.Base; + ResourceHi = Resource->Mem.Base + Resource->Mem.Length; + RecordLo = Record->Mem.Base; + RecordHi = Record->Mem.Base + Record->Mem.Length; + if (Resource->Mem.RWXAttributes != Record->Mem.RWXAttributes) { + if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) { + Record->Mem.RWXAttributes = Resource->Mem.RWXAttributes | Record->Mem.RWXAttributes; + return true; + } else { + return false; + } + } + break; + case IO_RANGE: + case TRAPPED_IO_RANGE: + ResourceLo = (uint64_t) Resource->Io.Base; + ResourceHi = (uint64_t) Resource->Io.Base + (uint64_t) Resource->Io.Length; + RecordLo = (uint64_t) Record->Io.Base; + RecordHi = (uint64_t) Record->Io.Base + (uint64_t) Record->Io.Length; + break; + case PCI_CFG_RANGE: + if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) || + (Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex)) { + return false; + } + if (memcmp (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof(STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) { + return false; + } + ResourceLo = (uint64_t) Resource->PciCfg.Base; + ResourceHi = (uint64_t) Resource->PciCfg.Base + (uint64_t) Resource->PciCfg.Length; + RecordLo = (uint64_t) Record->PciCfg.Base; + RecordHi = (uint64_t) Record->PciCfg.Base + (uint64_t) Record->PciCfg.Length; + if (Resource->PciCfg.RWAttributes != Record->PciCfg.RWAttributes) { + if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) { + Record->PciCfg.RWAttributes = Resource->PciCfg.RWAttributes | Record->PciCfg.RWAttributes; + return true; + } else { + return false; + } + } + break; + case MACHINE_SPECIFIC_REG: + // + // Special case - merge MSR masks in place. + // + if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) { + return false; + } + Record->Msr.ReadMask |= Resource->Msr.ReadMask; + Record->Msr.WriteMask |= Resource->Msr.WriteMask; + return true; + default: + return false; + } + // + // If resources are disjoint + // + if ((ResourceHi < RecordLo) || (ResourceLo > RecordHi)) { + return false; + } + + // + // If resource is consumed by record. + // + if ((ResourceLo >= RecordLo) && (ResourceHi <= RecordHi)) { + return true; + } + // + // Resources are overlapping. + // Resource and record are merged. + // + ResourceLo = (ResourceLo < RecordLo) ? ResourceLo : RecordLo; + ResourceHi = (ResourceHi > RecordHi) ? ResourceHi : RecordHi; + + switch (Resource->Header.RscType) { + case MEM_RANGE: + case MMIO_RANGE: + Record->Mem.Base = ResourceLo; + Record->Mem.Length = ResourceHi - ResourceLo; + break; + case IO_RANGE: + case TRAPPED_IO_RANGE: + Record->Io.Base = (uint64_t) ResourceLo; + Record->Io.Length = (uint64_t) (ResourceHi - ResourceLo); + break; + case PCI_CFG_RANGE: + Record->PciCfg.Base = (uint64_t) ResourceLo; + Record->PciCfg.Length = (uint64_t) (ResourceHi - ResourceLo); + break; + default: + return false; + } + + return true; +} + +/** + + Add resource node. + + @param Resource A pointer to resource node to be added + +**/ +void AddSingleResource(STM_RSC *Resource) +{ + STM_RSC *Record; + + Record = (STM_RSC *)mStmResourcesPtr; + + while (true) { + if (Record->Header.RscType == END_OF_RESOURCES) { + break; + } + // + // Go to next record if resource and record types don't match. + // + if (Resource->Header.RscType != Record->Header.RscType) { + Record = (STM_RSC *)((void *)Record + Record->Header.Length); + continue; + } + // + // Record is handled inside of procedure - don't adjust. + // + if (HandleSingleResource (Resource, Record)) { + return ; + } + Record = (STM_RSC *)((void *)Record + Record->Header.Length); + } + + // + // Add resource to the end of area. + // + memcpy ( + mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode), + Resource, + Resource->Header.Length + ); + memcpy ( + mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode) + Resource->Header.Length, + &mRscEndNode, + sizeof(mRscEndNode) + ); + mStmResourceSizeUsed += Resource->Header.Length; + mStmResourceSizeAvailable = mStmResourceTotalSize - mStmResourceSizeUsed; + + return ; +} + +/** + + Add resource list. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + +**/ +void AddResource(STM_RSC *ResourceList, uint32_t NumEntries) +{ + uint32_t Count; + UINTN Index; + STM_RSC *Resource; + + if (NumEntries == 0) { + Count = 0xFFFFFFFF; + } else { + Count = NumEntries; + } + + Resource = ResourceList; + + for (Index = 0; Index < Count; Index++) { + if (Resource->Header.RscType == END_OF_RESOURCES) { + return ; + } + AddSingleResource (Resource); + Resource = (STM_RSC *)((void *)Resource + Resource->Header.Length); + } + return ; +} + +/** + + Validate resource list. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval true resource valid + @retval false resource invalid + +**/ +bool +ValidateResource ( + STM_RSC *ResourceList, + uint32_t NumEntries + ) +{ + uint32_t Count; + UINTN Index; + STM_RSC *Resource; + UINTN SubIndex; + + // + // If NumEntries == 0 make it very big. Scan will be terminated by + // END_OF_RESOURCES. + // + if (NumEntries == 0) { + Count = 0xFFFFFFFF; + } else { + Count = NumEntries; + } + + // + // Start from beginning of resource list. + // + Resource = ResourceList; + + for (Index = 0; Index < Count; Index++) { + printk(BIOS_DEBUG, "ValidateResource (%llu) - RscType(%x)\n", Index, Resource->Header.RscType); + // + // Validate resource. + // + switch (Resource->Header.RscType) { + case END_OF_RESOURCES: + if (Resource->Header.Length != sizeof (STM_RSC_END)) { + return false; + } + // + // If we are passed actual number of resources to add, + // END_OF_RESOURCES structure between them is considered an + // error. If NumEntries == 0 END_OF_RESOURCES is a termination. + // + if (NumEntries != 0) { + return false; + } else { + // + // If NumEntries == 0 and list reached end - return success. + // + return true; + } + break; + + case MEM_RANGE: + case MMIO_RANGE: + if (Resource->Header.Length != sizeof (STM_RSC_MEM_DESC)) { + return false; + } + + if (Resource->Mem.RWXAttributes > FULL_ACCS) { + return false; + } + break; + + case IO_RANGE: + case TRAPPED_IO_RANGE: + if (Resource->Header.Length != sizeof (STM_RSC_IO_DESC)) { + return false; + } + + if ((Resource->Io.Base + Resource->Io.Length) > 0xFFFF) { + return false; + } + break; + + case PCI_CFG_RANGE: + printk(BIOS_DEBUG, "ValidateResource - PCI (0x%02x, 0x%08x, 0x%02x, 0x%02x)\n", Resource->PciCfg.OriginatingBusNumber, Resource->PciCfg.LastNodeIndex, Resource->PciCfg.PciDevicePath[0].PciDevice, Resource->PciCfg.PciDevicePath[0].PciFunction); + if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof(STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) { + return false; + } + for (SubIndex = 0; SubIndex <= Resource->PciCfg.LastNodeIndex; SubIndex++) { + if ((Resource->PciCfg.PciDevicePath[SubIndex].PciDevice > 0x1F) || (Resource->PciCfg.PciDevicePath[SubIndex].PciFunction > 7)) { + return false; + } + } + if ((Resource->PciCfg.Base + Resource->PciCfg.Length) > 0x1000) { + return false; + } + break; + + case MACHINE_SPECIFIC_REG: + if (Resource->Header.Length != sizeof (STM_RSC_MSR_DESC)) { + return false; + } + break; + + default : + printk(BIOS_DEBUG, "ValidateResource - Unknown RscType(%x)\n", Resource->Header.RscType); + return false; + } + Resource = (STM_RSC *)((void *)Resource + Resource->Header.Length); + } + return true; +} + +/** + + Get resource list. + EndResource is excluded. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval true resource valid + @retval false resource invalid + +**/ +UINTN +GetResourceSize ( + STM_RSC *ResourceList, + uint32_t NumEntries + ) +{ + uint32_t Count; + UINTN Index; + STM_RSC *Resource; + + Resource = ResourceList; + + // + // If NumEntries == 0 make it very big. Scan will be terminated by + // END_OF_RESOURCES. + // + if (NumEntries == 0) { + Count = 0xFFFFFFFF; + } else { + Count = NumEntries; + } + + // + // Start from beginning of resource list. + // + Resource = ResourceList; + + for (Index = 0; Index < Count; Index++) { + if (Resource->Header.RscType == END_OF_RESOURCES) { + break; + } + Resource = (STM_RSC *)((void *)Resource + Resource->Header.Length); + } + return (UINTN)((uint32_t)Resource - (uint32_t) ResourceList); +} + +/** + + Add resources in list to database. Allocate new memory areas as needed. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval EFI_SUCCESS If resources are added + @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer + @retval EFI_OUT_OF_RESOURCES If nested procedure returned it and we cannot allocate more areas. + +**/ +int +AddPiResource ( + STM_RSC *ResourceList, + uint32_t NumEntries + ) +{ + //int Status; + UINTN ResourceSize; + //void * NewResource; + //UINTN NewResourceSize; + + printk (BIOS_DEBUG, "AddPiResource - Enter\n"); + + if (!ValidateResource (ResourceList, NumEntries)) { + return -1; //EFI_INVALID_PARAMETER; + } + + ResourceSize = GetResourceSize (ResourceList, NumEntries); + printk (BIOS_DEBUG, "ResourceSize - 0x%08llx\n", ResourceSize); + if (ResourceSize == 0) { + return -1;//EFI_INVALID_PARAMETER; + } + + if (mStmResourcesPtr == NULL) { + // + // Copy EndResource for intialization + // + //mStmResourcesPtr = (uint8_t *)(UINTN)NewResource; + //mStmResourceTotalSize = NewResourceSize; + + mStmResourcesPtr = StmResourceHeap; + mStmResourceTotalSize = RESOURCEHEAPSIZE; + memset(mStmResourcesPtr, 0, RESOURCEHEAPSIZE); + + memcpy (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode)); + mStmResourceSizeUsed = sizeof(mRscEndNode); + mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode); + + // + // Let SmmCore change resource ptr + // + //NotifyStmResourceChange (mStmResourcesPtr); + } else if (mStmResourceSizeAvailable < ResourceSize) { + // + // Need enlarge + // + printk(BIOS_DEBUG, "ERROR - not enough soace for SMM resource list\n"); + return -1; + } + + // + // Check duplication + // + AddResource (ResourceList, NumEntries); + + return 0;//EFI_SUCCESS; +} + +/** + + Delete resources in list to database. + + @param ResourceList A pointer to resource list to be deleted + NULL means delete all resources. + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval EFI_SUCCESS If resources are deleted + @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer + +**/ +int32_t +DeletePiResource ( + STM_RSC *ResourceList, + uint32_t NumEntries + ) +{ + if (ResourceList != NULL) { + // TBD + //ASSERT (false); + return -1;//EFI_UNSUPPORTED; + } + // + // Delete all + // + memcpy (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode)); + mStmResourceSizeUsed = sizeof(mRscEndNode); + mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode); + return 0;//EFI_SUCCESS; +} + +/** + + Get BIOS resources. + + @param ResourceList A pointer to resource list to be filled + @param ResourceSize On input it means size of resource list input. + On output it means size of resource list filled, + or the size of resource list to be filled if size of too small. + + @retval EFI_SUCCESS If resources are returned. + @retval EFI_BUFFER_TOO_SMALL If resource list buffer is too small to hold the whole resources. + +**/ +int32_t +GetPiResource ( + STM_RSC *ResourceList, + uint32_t *ResourceSize + ) +{ + if (*ResourceSize < mStmResourceSizeUsed) { + *ResourceSize = (uint32_t)mStmResourceSizeUsed; + return -1;//EFI_BUFFER_TOO_SMALL; + } + + memcpy (ResourceList, mStmResourcesPtr, mStmResourceSizeUsed); + *ResourceSize = (uint32_t)mStmResourceSizeUsed; + return 0;//EFI_SUCCESS; +} + +/** + Get 4K page aligned VMCS size. + @return 4K page aligned VMCS size + +**/ +uint32_t +GetVmcsSize ( + void + ) +{ + uint32_t ThisVmcsSize; + VMX_BASIC_MSR MsrData64; + int StmSupport; + + MsrData64.msr = rdmsr (IA32_VMX_BASIC_MSR_INDEX); + + ThisVmcsSize = MsrData64.bits.VmcsSize; + StmSupport = MsrData64.bits.StmSupported; + printk(BIOS_DEBUG, "GetVmcsSize: Size %d StmSupport %d\n", ThisVmcsSize, StmSupport); + + // + // VMCS require 0x1000 alignment + // + ThisVmcsSize = STM_PAGES_TO_SIZE (STM_SIZE_TO_PAGES (ThisVmcsSize)); + + return ThisVmcsSize; +} + +/** + + Create 4G page table for STM. + 4M Non-PAE page table in IA32 version. + + @param PageTableBase The page table base in MSEG + +**/ +void +StmGen4GPageTableIa32 ( + uint32_t PageTableBase + ) +{ + UINTN Index; + uint32_t *Pte; + uint32_t Address; + + Pte = (uint32_t*)(uint32_t)PageTableBase; + + Address = 0; + for (Index = 0; Index < SIZE_4KB / sizeof (*Pte); Index++) { + *Pte = Address | IA32_PG_PS | IA32_PG_RW | IA32_PG_P; + Pte++; + Address += SIZE_4MB; + } + + return ; +} + +/** + + Create 4G page table for STM. + 2M PAE page table in X64 version. + + @param PageTableBase The page table base in MSEG + +**/ +void +StmGen4GPageTableX64 ( + uint32_t PageTableBase + ) +{ + UINTN Index; + UINTN SubIndex; + uint64_t *Pde; + uint64_t *Pte; + uint64_t *Pml4; + + Pml4 = (uint64_t*)(uint32_t) PageTableBase; + PageTableBase += SIZE_4KB; + *Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P; + + Pde = (uint64_t*)(uint32_t)PageTableBase; + PageTableBase += SIZE_4KB; + Pte = (uint64_t *)(uint32_t)PageTableBase; + + for (Index = 0; Index < 4; Index++) { + *Pde = PageTableBase | IA32_PG_RW | IA32_PG_P; + Pde++; + PageTableBase += SIZE_4KB; + + for (SubIndex = 0; SubIndex < SIZE_4KB / sizeof (*Pte); SubIndex++) { + *Pte = (((Index << 9) + SubIndex) << 21) | IA32_PG_PS | IA32_PG_RW | IA32_PG_P; + Pte++; + } + } + + return ; +} + +/** + + Check STM image size. + + @param StmImage STM image + @param StmImageSize STM image size + + @retval true check pass + @retval false check fail +**/ + +bool StmCheckStmImage ( + void * StmImage, + uint32_t StmImageSize + ) +{ + UINTN MinMsegSize; + STM_HEADER *StmHeader; + + StmHeader = (STM_HEADER *)StmImage; + + // + // Get Minimal required Mseg size + // + MinMsegSize = (STM_PAGES_TO_SIZE (STM_SIZE_TO_PAGES (StmHeader->SwStmHdr.StaticImageSize)) + + StmHeader->SwStmHdr.AdditionalDynamicMemorySize + + (StmHeader->SwStmHdr.PerProcDynamicMemorySize + GetVmcsSize () * 2) * mp_state.cpu_count); + if (MinMsegSize < StmImageSize) { + MinMsegSize = StmImageSize; + } + + if (StmHeader->HwStmHdr.Cr3Offset >= StmHeader->SwStmHdr.StaticImageSize) { + // + // We will create page table, just in case that SINIT does not create it. + // + if (MinMsegSize < StmHeader->HwStmHdr.Cr3Offset + STM_PAGES_TO_SIZE(6)) { + MinMsegSize = StmHeader->HwStmHdr.Cr3Offset + STM_PAGES_TO_SIZE(6); + } + } + + // + // Check if it exceeds MSEG size + // + if (MinMsegSize > CONFIG_MSEG_SIZE) { + return false; + } + + return true; + +} + + +/** + + Load STM image to MSEG. + + @param StmImage STM image + @param StmImageSize STM image size + +**/ +void +StmLoadStmImage ( + void * StmImage, + UINTN StmImageSize + ) +{ + uint32_t MsegBase; + STM_HEADER *StmHeader; + SMM_MONITOR_CTL_MSR SmmMonitorMsr; + + StmHeader = (STM_HEADER *)(uint32_t)StmImage; + SmmMonitorMsr.msr = rdmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX); + MsegBase = SmmMonitorMsr.bits.MsegAddress << 12; + + //ZeroMem ((void *)(uint32_t)MsegBase, (uint32_t)PcdGet32 (PcdCpuMsegSize)); + + memset((void *) MsegBase, 0, CONFIG_MSEG_SIZE); + //memcpy ((void *)(uint32_t)MsegBase, (void *)(uint32_t)StmImage, StmImageSize); + memcpy((void *) MsegBase, (void *) StmImage, (size_t) StmImageSize); + + + if (sizeof(UINTN) == sizeof(uint64_t)) { + StmGen4GPageTableX64 ((UINTN)MsegBase + StmHeader->HwStmHdr.Cr3Offset); + } else { + StmGen4GPageTableIa32 ((UINTN)MsegBase + StmHeader->HwStmHdr.Cr3Offset); + } + + // BUGBUG: SNB can not write 0x9B twice +// WriteCpuMsegInfo (); +} + +/** + + Load STM image to MSEG. + + @param StmImage STM image + @param StmImageSize STM image size + + @retval EFI_SUCCESS Load STM to MSEG successfully + @retval EFI_ALREADY_STARTED STM image is already loaded to MSEG + @retval EFI_BUFFER_TOO_SMALL MSEG is smaller than minimal requirement of STM image + @retval EFI_UNSUPPORTED MSEG is not enabled + +**/ +int LoadMonitor ( + void * StmImage, + uint32_t StmImageSize + ) +{ + SMM_MONITOR_CTL_MSR SmmMonCtlMsr; + + SmmMonCtlMsr.msr = (msr_t) rdmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX); + + if (SmmMonCtlMsr.bits.MsegAddress == 0) { + return STM_UNSUPPORTED; + } + if (SmmMonCtlMsr.bits.valid != 0) { + // BUGBUG: SNB can not write 0x9B twice +// return EFI_ALREADY_STARTED; + } + + if (!StmCheckStmImage (StmImage, StmImageSize)) { + return STM_BUFFER_TOO_SMALL; + } + +#ifdef TPMSUPPORT + // Record STM_HASH to PCR 0, just in case it is NOT TXT launch, we still need provide the evidence. + TpmMeasureAndLogData( + 0, // PcrIndex + TXT_EVTYPE_STM_HASH, // EventType + NULL, // EventLog + 0, // LogLen + (void *)StmImage, // HashData + StmImageSize // HashDataLen + ); +#endif + StmLoadStmImage (StmImage, StmImageSize); + + mStmState |= STM_SM_MONITOR_STATE_ENABLED; + + return STM_SUCCESS; +} + +/** + This function return BIOS STM resource. + Produced by SmmStm. + Comsumed by SmmMpService when Init. + + @return BIOS STM resource +**/ +void * +GetStmResource( + void + ) +{ + return mStmResourcesPtr; +} + diff --git a/src/security/intel/stm/SmmStm.h b/src/security/intel/stm/SmmStm.h new file mode 100644 index 0000000..4442a63 --- /dev/null +++ b/src/security/intel/stm/SmmStm.h @@ -0,0 +1,122 @@ +/** @file + SMM STM support + + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made + available under the terms and conditions of the BSD License which + accompanies this distribution. The full text of the license may + be found at http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED + +**/ + +#ifndef _SMM_STM_H_ +#define _SMM_STM_H_ + +#include "StmApi.h" + +#define IA32_VMX_BASIC_MSR_INDEX 0x480 +#define IA32_VMX_MISC_MSR_INDEX 0x485 +#define IA32_SMM_MONITOR_CTL_MSR_INDEX 0x9B +#define IA32_SMM_MONITOR_VALID (1<<0) + +/** + + Load STM image to MSEG. + + @param StmImage STM image + @param StmImageSize STM image size + + @retval SUCCESS Load STM to MSEG successfully + @retval BUFFER_TOO_SMALL MSEG is smaller than minimal size of STM image + +**/ +int LoadMonitor( + void *StmImage, + uint32_t StmImageSize + ); + +/** + + Add resources in list to database. Allocate new memory areas as needed. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval SUCCESS If resources are added + @retval INVALID_PARAMETER If nested procedure detected resource failer + @retval OUT_OF_RESOURCES If nested procedure returned it and we cannot allocate more areas. + +**/ +int AddPiResource( + STM_RSC *ResourceList, + uint32_t NumEntries + ); + +/** + + Delete resources in list to database. + + @param ResourceList A pointer to resource list to be deleted + NULL means delete all resources. + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval SUCCESS If resources are deleted + @retval NVALID_PARAMETER If nested procedure detected resource failer + +**/ +int DeletePiResource( + STM_RSC *ResourceList, + uint32_t NumEntries + ); + +/** + + Get BIOS resources. + + @param ResourceList A pointer to resource list to be filled + @param ResourceSize On input it means size of resource list input. + On output it means size of resource list filled, + or the size of resource list to be filled if + size of too small. + + @retval SUCCESS If resources are returned. + @retval BUFFER_TOO_SMALL If resource list buffer is too small to + hold the whole resources. + +**/ +int GetPiResource( + STM_RSC *ResourceList, + uint32_t *ResourceSize + ); + +/** + This function notify STM resource change. + + @param StmResource BIOS STM resource + +**/ +void +NotifyStmResourceChange( + void *StmResource + ); + +/** + This function return BIOS STM resource. + + @return BIOS STM resource + +**/ +void * +GetStmResource( + void + ); + +void SetupSmmDescriptor(void *smbase, int32_t state_size, int32_t apic_id, + int32_t entry32_off); + +#endif diff --git a/src/security/intel/stm/StmApi.h b/src/security/intel/stm/StmApi.h new file mode 100644 index 0000000..2328b32 --- /dev/null +++ b/src/security/intel/stm/StmApi.h @@ -0,0 +1,753 @@ +/** @file + STM API definition + + Copyright (c) 2015, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _STM_API_H_ +#define _STM_API_H_ + +#include <stdint.h> + +// definition in STM spec + +#define STM_SPEC_VERSION_MAJOR 1 +#define STM_SPEC_VERSION_MINOR 0 + +typedef uint64_t UINTN; + +#pragma pack (push, 1) + +#define STM_HARDWARE_FIELD_FILL_TO_2K (2048 - sizeof(uint32_t) * 8) +typedef struct { + uint32_t StmHeaderRevision; + uint32_t MonitorFeatures; + uint32_t GdtrLimit; + uint32_t GdtrBaseOffset; + uint32_t CsSelector; + uint32_t EipOffset; + uint32_t EspOffset; + uint32_t Cr3Offset; + uint8_t Reserved[STM_HARDWARE_FIELD_FILL_TO_2K]; +} HARDWARE_STM_HEADER; + +#define STM_FEATURES_IA32E 0x1 + +typedef struct { + uint32_t Intel64ModeSupported :1; // bitfield + uint32_t EptSupported :1; // bitfield + uint32_t Reserved :30; // must be 0 +} STM_FEAT; + +typedef struct { + uint8_t StmSpecVerMajor; + uint8_t StmSpecVerMinor; + uint16_t Reserved; // must be zero + uint32_t StaticImageSize; + uint32_t PerProcDynamicMemorySize; + uint32_t AdditionalDynamicMemorySize; + STM_FEAT StmFeatures; + uint32_t NumberOfRevIDs; + uint32_t StmSmmRevID[1]; + // + // The total STM_HEADER should be 4K. + // +} SOFTWARE_STM_HEADER; + +typedef struct { + HARDWARE_STM_HEADER HwStmHdr; + SOFTWARE_STM_HEADER SwStmHdr; +} STM_HEADER; + +#define SHA1 1 +#define SHA256 2 +typedef struct { + uint64_t BiosComponentBase; + uint32_t ImageSize; + uint32_t HashAlgorithm; // SHA1 or SHA256 + uint8_t Hash[32]; +} TXT_BIOS_COMPONENT_STATUS; + +#define PAGE_SIZE 4096 +typedef struct { + uint32_t ImageSize; + uint32_t Reserved; + uint64_t ImagePageBase[1]; //[NumberOfPages]; +} TXT_BIOS_COMPONENT_UPDATE; + +// If (ImageSizeInBytes % PAGE_SIZE == 0) { +// NumberOfPages = ImageSizeInBytes / PAGE_SIZE +// } else { +// NumberOfPages = ImageSizeInBytes / PAGE_SIZE + 1 +// } + + +typedef struct { + uint64_t SpeRip; + uint64_t SpeRsp; + uint16_t SpeSs; + uint16_t PageViolationException:1; + uint16_t MsrViolationException:1; + uint16_t RegisterViolationException:1; + uint16_t IoViolationException:1; + uint16_t PciViolationException:1; + uint16_t Reserved1:11; + uint32_t Reserved2; +} STM_PROTECTION_EXCEPTION_HANDLER; + +typedef struct { + uint8_t ExecutionDisableOutsideSmrr:1; + uint8_t Intel64Mode:1; + uint8_t Cr4Pae : 1; + uint8_t Cr4Pse : 1; + uint8_t Reserved1 : 4; +} STM_SMM_ENTRY_STATE; + +typedef struct { + uint8_t SmramToVmcsRestoreRequired : 1; // BIOS restore hint + uint8_t ReinitializeVmcsRequired : 1; // BIOS request + uint8_t Reserved2 : 6; +} STM_SMM_RESUME_STATE; + +typedef struct { + uint8_t DomainType : 4; // STM input to BIOS on each SM + uint8_t XStatePolicy : 2; // STM input to BIOS on each SMI + uint8_t EptEnabled : 1; + uint8_t Reserved3 : 1; +} STM_SMM_STATE; + +typedef struct { + uint64_t Signature; + uint16_t Size; + uint8_t SmmDescriptorVerMajor; + uint8_t SmmDescriptorVerMinor; + uint32_t LocalApicId; + STM_SMM_ENTRY_STATE SmmEntryState; + STM_SMM_RESUME_STATE SmmResumeState; + STM_SMM_STATE StmSmmState; + uint8_t Reserved4; + uint16_t SmmCs; + uint16_t SmmDs; + uint16_t SmmSs; + uint16_t SmmOtherSegment; + uint16_t SmmTr; + uint16_t Reserved5; + uint64_t SmmCr3; + uint64_t SmmStmSetupRip; + uint64_t SmmStmTeardownRip; + uint64_t SmmSmiHandlerRip; + uint64_t SmmSmiHandlerRsp; + uint64_t SmmGdtPtr; + uint32_t SmmGdtSize; + uint32_t RequiredStmSmmRevId; + STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler; + uint64_t Reserved6; + uint64_t BiosHwResourceRequirementsPtr; + // extend area + uint64_t AcpiRsdp; + uint8_t PhysicalAddressBits; +} TXT_PROCESSOR_SMM_DESCRIPTOR; + +#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE "TXTPSSIG" +#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR 1 +#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0 + +#define SMM_PSD_OFFSET 0xfb00 + +typedef enum { + TxtSmmPageViolation = 1, + TxtSmmMsrViolation, + TxtSmmRegisterViolation, + TxtSmmIoViolation, + TxtSmmPciViolation +} TXT_SMM_PROTECTION_EXCEPTION_TYPE; + +typedef struct { + uint32_t Rdi; + uint32_t Rsi; + uint32_t Rbp; + uint32_t Rdx; + uint32_t Rcx; + uint32_t Rbx; + uint32_t Rax; + uint32_t Cr3; + uint32_t Cr2; + uint32_t Cr0; + uint32_t VmcsExitInstructionInfo; + uint32_t VmcsExitInstructionLength; + uint64_t VmcsExitQualification; + uint32_t ErrorCode; // TXT_SMM_PROTECTION_EXCEPTION_TYPE + uint32_t Rip; + uint32_t Cs; + uint32_t Rflags; + uint32_t Rsp; + uint32_t Ss; +} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32; + +typedef struct { + uint64_t R15; + uint64_t R14; + uint64_t R13; + uint64_t R12; + uint64_t R11; + uint64_t R10; + uint64_t R9; + uint64_t R8; + uint64_t Rdi; + uint64_t Rsi; + uint64_t Rbp; + uint64_t Rdx; + uint64_t Rcx; + uint64_t Rbx; + uint64_t Rax; + uint64_t Cr8; + uint64_t Cr3; + uint64_t Cr2; + uint64_t Cr0; + uint64_t VmcsExitInstructionInfo; + uint64_t VmcsExitInstructionLength; + uint64_t VmcsExitQualification; + uint64_t ErrorCode; // TXT_SMM_PROTECTION_EXCEPTION_TYPE + uint64_t Rip; + uint64_t Cs; + uint64_t Rflags; + uint64_t Rsp; + uint64_t Ss; +} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64; + +typedef union { + STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame; + STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame; +} STM_PROTECTION_EXCEPTION_STACK_FRAME; + +#define STM_SMM_REV_ID 0x80010100 + +typedef struct _STM_SMM_CPU_STATE { + uint8_t Reserved1[0x1d0]; // fc00h + uint32_t GdtBaseHiDword; // fdd0h : NO + uint32_t LdtBaseHiDword; // fdd4h : NO + uint32_t IdtBaseHiDword; // fdd8h : NO + uint8_t Reserved2[0x4]; // fddch + uint64_t IoRdi; // fde0h : NO + // - restricted + uint64_t IoEip; // fde8h : YES + uint64_t IoRcx; // fdf0h : NO + // - restricted + uint64_t IoRsi; // fdf8h : NO + // - restricted + uint8_t Reserved3[0x40]; // fe00h + uint32_t Cr4; // fe40h : NO + uint8_t Reserved4[0x48]; // fe44h + uint32_t GdtBaseLoDword; // fe8ch : NO + uint32_t GdtLimit; // fe90h : NO + // - RESTRICTED + uint32_t IdtBaseLoDword; // fe94h : NO + uint32_t IdtLimit; // fe98h : NO + // - RESTRICTED + uint32_t LdtBaseLoDword; // fe9ch : NO + uint32_t LdtLimit; // fea0h : NO + // - RESTRICTED + uint32_t LdtInfo; // fea4h : NO + // - RESTRICTED + uint8_t Reserved5[0x30]; // fea8h + uint64_t Eptp; // fed8h : NO + uint32_t EnabledEPT; // fee0h : NO + uint8_t Reserved6[0x14]; // fee4h + uint32_t Smbase; // fef8h : YES + // - NO for STM + uint32_t SMMRevId; // fefch : NO + uint16_t IORestart; // ff00h : YES + uint16_t AutoHALTRestart; // ff02h : YES + uint8_t Reserved7[0x18]; // ff04h + uint64_t R15; // ff1ch : YES + uint64_t R14; // ff24h : YES + uint64_t R13; // ff2ch : YES + uint64_t R12; // ff34h : YES + uint64_t R11; // ff3ch : YES + uint64_t R10; // ff44h : YES + uint64_t R9; // ff4ch : YES + uint64_t R8; // ff54h : YES + uint64_t Rax; // ff5ch : YES + uint64_t Rcx; // ff64h : YES + uint64_t Rdx; // ff6ch : YES + uint64_t Rbx; // ff74h : YES + uint64_t Rsp; // ff7ch : YES + uint64_t Rbp; // ff84h : YES + uint64_t Rsi; // ff8ch : YES + uint64_t Rdi; // ff94h : YES + uint64_t IOMemAddr; // ff9ch : NO + uint32_t IOMisc; // ffa4h : NO + uint32_t Es; // ffa8h : NO + uint32_t Cs; // ffach : NO + uint32_t Ss; // ffb0h : NO + uint32_t Ds; // ffb4h : NO + uint32_t Fs; // ffb8h : NO + uint32_t Gs; // ffbch : NO + uint32_t Ldtr; // ffc0h : NO + uint32_t Tr; // ffc4h : NO + uint64_t Dr7; // ffc8h : NO + uint64_t Dr6; // ffd0h : NO + uint64_t Rip; // ffd8h : YES + uint64_t Ia32Efer; // ffe0h : YES + // - NO for STM + uint64_t Rflags; // ffe8h : YES + uint64_t Cr3; // fff0h : NO + uint64_t Cr0; // fff8h : NO +} STM_SMM_CPU_STATE; + +// +// STM Mapping +// + +typedef struct { + uint64_t PhysicalAddress; + uint64_t VirtualAddress; + uint32_t PageCount; + uint32_t PatCacheType; +} STM_MAP_ADDRESS_RANGE_DESCRIPTOR; +#define ST_UC 0x00 +#define WC 0x01 +#define WT 0x04 +#define WP 0x05 +#define WB 0x06 +#define UC 0x07 +#define FOLLOW_MTRR 0xFFFFFFFF + +typedef struct { + uint64_t VirtualAddress; + uint32_t Length; +} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR; + +typedef struct { + uint64_t InterruptedGuestVirtualAddress; + uint32_t Length; + uint64_t InterruptedCr3; + uint64_t InterruptedEptp; + uint32_t MapToSmmGuest:2; + uint32_t InterruptedCr4Pae:1; + uint32_t InterruptedCr4Pse:1; + uint32_t InterruptedIa32eMode:1; + uint32_t Reserved1:27; + uint32_t Reserved2; + uint64_t PhysicalAddress; + uint64_t SmmGuestVirtualAddress; +} STM_ADDRESS_LOOKUP_DESCRIPTOR; +#define DO_NOT_MAP 0 +#define ONE_TO_ONE 1 +#define VIRTUAL_ADDRESS_SPECIFIED 3 + +// +// STM_RESOURCE_LIST +// +#define END_OF_RESOURCES 0 +#define MEM_RANGE 1 +#define IO_RANGE 2 +#define MMIO_RANGE 3 +#define MACHINE_SPECIFIC_REG 4 +#define PCI_CFG_RANGE 5 +#define TRAPPED_IO_RANGE 6 +#define ALL_RESOURCES 7 +#define REGISTER_VIOLATION 8 +#define MAX_DESC_TYPE 8 + +typedef struct { + uint32_t RscType; + uint16_t Length; + uint16_t ReturnStatus:1; + uint16_t Reserved:14; + uint16_t IgnoreResource:1; +} STM_RSC_DESC_HEADER; + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint64_t ResourceListContinuation; +} STM_RSC_END; + +// byte granular Memory range support +#define STM_RSC_BGM 0x4 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint64_t Base; + uint64_t Length; + uint32_t RWXAttributes:3; + uint32_t Reserved:29; + uint32_t Reserved_2; +} STM_RSC_MEM_DESC; +#define STM_RSC_MEM_R 0x1 +#define STM_RSC_MEM_W 0x2 +#define STM_RSC_MEM_X 0x4 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint16_t Base; + uint16_t Length; + uint32_t Reserved; +} STM_RSC_IO_DESC; + +// byte granular MMIO range support +#define STM_RSC_BGI 0x2 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint64_t Base; + uint64_t Length; + uint32_t RWXAttributes:3; + uint32_t Reserved:29; + uint32_t Reserved_2; +} STM_RSC_MMIO_DESC; +#define STM_RSC_MMIO_R 0x1 +#define STM_RSC_MMIO_W 0x2 +#define STM_RSC_MMIO_X 0x4 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint32_t MsrIndex; + uint32_t KernelModeProcessing:1; + uint32_t Reserved:31; + uint64_t ReadMask; + uint64_t WriteMask; +} STM_RSC_MSR_DESC; + +// bit granular MSR resource support +#define STM_RSC_MSR 0x8 + +typedef struct { + uint8_t Type; // must be 1, indicating Hardware Device Path + uint8_t Subtype; // must be 1, indicating PCI + uint16_t Length; // sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6 + uint8_t PciFunction; + uint8_t PciDevice; +} STM_PCI_DEVICE_PATH_NODE; +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint16_t RWAttributes:2; + uint16_t Reserved:14; + uint16_t Base; + uint16_t Length; + uint8_t OriginatingBusNumber; + uint8_t LastNodeIndex; + STM_PCI_DEVICE_PATH_NODE PciDevicePath[1]; +//STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1]; +} STM_RSC_PCI_CFG_DESC; + +#define STM_RSC_PCI_CFG_R 0x1 +#define STM_RSC_PCI_CFG_W 0x2 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint16_t Base; + uint16_t Length; + uint16_t In:1; + uint16_t Out:1; + uint16_t Api:1; + uint16_t Reserved1:13; + uint16_t Reserved2; +} STM_RSC_TRAPPED_IO_DESC; + +typedef struct { + STM_RSC_DESC_HEADER Hdr; +} STM_RSC_ALL_RESOURCES_DESC; + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint32_t RegisterType; + uint32_t Reserved; + uint64_t ReadMask; + uint64_t WriteMask; +} STM_REGISTER_VIOLATION_DESC; + +typedef enum { + StmRegisterCr0, + StmRegisterCr2, + StmRegisterCr3, + StmRegisterCr4, + StmRegisterCr8, + StmRegisterMax, +} STM_REGISTER_VIOLATION_TYPE; + +typedef union { + STM_RSC_DESC_HEADER Header; + STM_RSC_END End; + STM_RSC_MEM_DESC Mem; + STM_RSC_IO_DESC Io; + STM_RSC_MMIO_DESC Mmio; + STM_RSC_MSR_DESC Msr; + STM_RSC_PCI_CFG_DESC PciCfg; + STM_RSC_TRAPPED_IO_DESC TrappedIo; + STM_RSC_ALL_RESOURCES_DESC All; + STM_REGISTER_VIOLATION_DESC RegisterViolation; +} STM_RSC; + +// +// VMCS database +// +#define STM_VMCS_DATABASE_REQUEST_ADD 1 +#define STM_VMCS_DATABASE_REQUEST_REMOVE 0 + +// Values for DomainType +// Intepreter of DomainType +#define DOMAIN_DISALLOWED_IO_OUT (1u << 0) +#define DOMAIN_DISALLOWED_IO_IN (1u << 1) +#define DOMAIN_INTEGRITY (1u << 2) +#define DOMAIN_CONFIDENTIALITY (1u << 3) + +#define DOMAIN_UNPROTECTED 0x00 +#define DOMAIN_INTEGRITY_PROT_OUT_IN (DOMAIN_INTEGRITY) +//#define DOMAIN_INTEGRITY_PROT_OUT (DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_IN) +#define DOMAIN_FULLY_PROT_OUT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY) +//#define DOMAIN_FULLY_PROT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_OUT) +//#define DOMAIN_FULLY_PROT_OUT (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_IN) +#define DOMAIN_FULLY_PROT (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_IN | DOMAIN_DISALLOWED_IO_OUT) + +// Values for XStatePolicy +#define XSTATE_READWRITE 0x00 +#define XSTATE_READONLY 0x01 +#define XSTATE_SCRUB 0x03 + +typedef struct { + uint64_t VmcsPhysPointer; // bits 11:0 are reserved and must be 0 + uint32_t DomainType :4; + uint32_t XStatePolicy :2; + uint32_t DegradationPolicy :4; + uint32_t Reserved1 :22; // Must be 0 + uint32_t AddOrRemove; +} STM_VMCS_DATABASE_REQUEST; + +// +// Event log +// +#define NEW_LOG 1 +#define CONFIGURE_LOG 2 +#define START_LOG 3 +#define STOP_LOG 4 +#define CLEAR_LOG 5 +#define DELETE_LOG 6 +typedef enum { + EvtLogStarted, + EvtLogStopped, + EvtLogInvalidParameterDetected, + EvtHandledProtectionException, + // unhandled protection exceptions result in reset & cannot be logged + EvtBiosAccessToUnclaimedResource, + EvtMleResourceProtectionGranted, + EvtMleResourceProtectionDenied, + EvtMleResourceUnprotect, + EvtMleResourceUnprotectError, + EvtMleDomainTypeDegraded, + // add more here + EvtMleMax, + // Not used + EvtInvalid = 0xFFFFFFFF, +} EVENT_TYPE; + +//#define STM_EVENT_LOG_PAGE_COUNT_MAX 62 + +typedef struct { + uint32_t PageCount; + uint64_t Pages[1]; // number of elements is PageCount +} STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA_LOG_BUFFER; + +typedef union { + STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA_LOG_BUFFER LogBuffer; + uint32_t EventEnableBitmap; // bitmap of EVENT_TYPE +} STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA; + +typedef struct { + uint32_t SubFunctionIndex; + STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA Data; +} STM_EVENT_LOG_MANAGEMENT_REQUEST; + +// +// VMCALL API Numbers +// + +// API number convention: BIOS facing VMCALL interfaces have bit 16 clear +#define STM_API_MAP_ADDRESS_RANGE 0x00000001 +#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002 +#define STM_API_ADDRESS_LOOKUP 0x00000003 +#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004 + +// API number convention: MLE facing VMCALL interfaces have bit 16 set +// +// The STM configuration lifecycle is as follows: +// 1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked). +// 2. MLE invokes InitializeProtectionVMCALL() to prepare STM for setup of +// initial protection profile. This is done on a single CPU and has global +// effect. +// 3. MLE invokes ProtectResourceVMCALL() to define the initial protection +// profile. The protection profile is global across all CPUs. +// 4. MLE invokes StartStmVMCALL() to enable the STM to begin receiving SMI +// events. This must be done on every logical CPU. +// 5. MLE may invoke ProtectResourceVMCALL() or UnProtectResourceVMCALL() +// during runtime as many times as necessary. +// 6. MLE invokes StopStmVMCALL() to disable the STM. SMI is again masked +// following StopStmVMCALL(). +// +#define STM_API_START 0x00010001 +#define STM_API_STOP 0x00010002 +#define STM_API_PROTECT_RESOURCE 0x00010003 +#define STM_API_UNPROTECT_RESOURCE 0x00010004 +#define STM_API_GET_BIOS_RESOURCES 0x00010005 +#define STM_API_MANAGE_VMCS_DATABASE 0x00010006 +#define STM_API_INITIALIZE_PROTECTION 0x00010007 +#define STM_API_MANAGE_EVENT_LOG 0x00010008 + +// +// Return codes +// +typedef uint32_t STM_STATUS; + +#define STM_SUCCESS 0x00000000 +#define SMM_SUCCESS 0x00000000 +// all error codes have bit 31 set +// STM errors have bit 16 set +#define ERROR_STM_SECURITY_VIOLATION 0x80010001 +#define ERROR_STM_CACHE_TYPE_NOT_SUPPORTED 0x80010002 +#define ERROR_STM_PAGE_NOT_FOUND 0x80010003 +#define ERROR_STM_BAD_CR3 0x80010004 +#define ERROR_STM_PHYSICAL_OVER_4G 0x80010005 +#define ERROR_STM_VIRTUAL_SPACE_TOO_SMALL 0x80010006 +#define ERROR_STM_UNPROTECTABLE_RESOURCE 0x80010007 +#define ERROR_STM_ALREADY_STARTED 0x80010008 +#define ERROR_STM_WITHOUT_SMX_UNSUPPORTED 0x80010009 +#define ERROR_STM_STOPPED 0x8001000A +#define ERROR_STM_BUFFER_TOO_SMALL 0x8001000B +#define ERROR_STM_INVALID_VMCS_DATABASE 0x8001000C +#define ERROR_STM_MALFORMED_RESOURCE_LIST 0x8001000D +#define ERROR_STM_INVALID_PAGECOUNT 0x8001000E +#define ERROR_STM_LOG_ALLOCATED 0x8001000F +#define ERROR_STM_LOG_NOT_ALLOCATED 0x80010010 +#define ERROR_STM_LOG_NOT_STOPPED 0x80010011 +#define ERROR_STM_LOG_NOT_STARTED 0x80010012 +#define ERROR_STM_RESERVED_BIT_SET 0x80010013 +#define ERROR_STM_NO_EVENTS_ENABLED 0x80010014 +#define ERROR_STM_OUT_OF_RESOURCES 0x80010015 +#define ERROR_STM_FUNCTION_NOT_SUPPORTED 0x80010016 +#define ERROR_STM_UNPROTECTABLE 0x80010017 +#define ERROR_STM_UNSUPPORTED_MSR_BIT 0x80010018 +#define ERROR_STM_UNSPECIFIED 0x8001FFFF + +// SMM errors have bit 17 set +#define ERROR_SMM_BAD_BUFFER 0x80020001 +#define ERROR_SMM_INVALID_RSC 0x80020004 +#define ERROR_SMM_INVALID_BUFFER_SIZE 0x80020005 +#define ERROR_SMM_BUFFER_TOO_SHORT 0x80020006 +#define ERROR_SMM_INVALID_LIST 0x80020007 +#define ERROR_SMM_OUT_OF_MEMORY 0x80020008 +#define ERROR_SMM_AFTER_INIT 0x80020009 +#define ERROR_SMM_UNSPECIFIED 0x8002FFFF + +// Errors that apply to both have bits 15, 16, and 17 set +#define ERROR_INVALID_API 0x80038001 +#define ERROR_INVALID_PARAMETER 0x80038002 + +// +// STM TXT.ERRORCODE codes +// +#define STM_CRASH_PROTECTION_EXCEPTION 0xC000F001 +#define STM_CRASH_PROTECTION_EXCEPTION_FAILURE 0xC000F002 +#define STM_CRASH_DOMAIN_DEGRADATION_FAILURE 0xC000F003 +#define STM_CRASH_BIOS_PANIC 0xC000E000 + +typedef struct { + uint32_t EventSerialNumber; + uint16_t Type; + uint16_t Lock :1; + uint16_t Valid :1; + uint16_t ReadByMle :1; + uint16_t Wrapped :1; + uint16_t Reserved :12; +} LOG_ENTRY_HEADER; + +typedef struct { + uint32_t Reserved; +} ENTRY_EVT_LOG_STARTED; + +typedef struct { + uint32_t Reserved; +} ENTRY_EVT_LOG_STOPPED; + +typedef struct { + uint32_t VmcallApiNumber; +} ENTRY_EVT_LOG_INVALID_PARAM; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_PROT_GRANTED; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_PROT_DENIED; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_UNPROT; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_UNPROT_ERROR; + +typedef struct { + uint64_t VmcsPhysPointer; + uint8_t ExpectedDomainType; + uint8_t DegradedDomainType; +} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED; + +typedef union { + ENTRY_EVT_LOG_STARTED Started; + ENTRY_EVT_LOG_STOPPED Stopped; + ENTRY_EVT_LOG_INVALID_PARAM InvalidParam; + ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException; + ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc; + ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted; + ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied; + ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot; + ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError; + ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded; +} LOG_ENTRY_DATA; + +typedef struct { + LOG_ENTRY_HEADER Hdr; + LOG_ENTRY_DATA Data; +} STM_LOG_ENTRY; + +#define STM_LOG_ENTRY_SIZE 256 + +// +// +// +#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF 0x1 + +// +// TXT debug +// +#define SW_SMI_STM_ADD_RUNTIME_RESOURCES_SUB_FUNC 0 +#define SW_SMI_STM_READ_BIOS_RESOURCES_SUB_FUNC 1 +#define SW_SMI_STM_REPLACE_BIOS_RESOURCES_SUB_FUNC 2 + +typedef struct { + uint32_t BufferSize; + uint32_t Reserved; + //uint8_t Data[]; +} TXT_BIOS_DEBUG; + +#pragma pack (pop) + +#endif diff --git a/src/security/intel/stm/StmPlatformResource.c b/src/security/intel/stm/StmPlatformResource.c new file mode 100644 index 0000000..ad8a69b --- /dev/null +++ b/src/security/intel/stm/StmPlatformResource.c @@ -0,0 +1,259 @@ +/** @file + STM platform SMM resource + + Copyright (c) 2015, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made + available under the terms and conditions of the BSD License which + accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <stdint.h> +#include <security/intel/stm/StmApi.h> +#include <security/intel/stm/SmmStm.h> +#include <security/intel/stm/StmPlatformResource.h> + +#include <southbridge/intel/common/pmutil.h> +#include <cpu/x86/msr.h> + +#define RDWR_ACCS 3 +#define FULL_ACCS 7 + +uint32_t mMaxBus; +uint32_t mTsegBase; +uint32_t mTsegSize; +uint16_t mPmBase; + +typedef union { + uint64_t uint64; + msr_t msr; +} msr64_t; + +//uint64_t PciRead64 (UINTN Address); +void ResourceInit(void); +void FixupPciexResource(void); +void AddSimpleResources(void); +void AddMsrResources(void); + +// +// Fixed memory ranges +// + +// +// TSEG memory! +// +STM_RSC_MEM_DESC RscTsegMemory = { + {MEM_RANGE, sizeof (STM_RSC_MEM_DESC)}, + 0, + 0, + FULL_ACCS +}; +// +// Flash part +// +STM_RSC_MEM_DESC RscSpiMemory = { + {MEM_RANGE, sizeof (STM_RSC_MEM_DESC)}, + 0xFE000000, + 0x01000000, + FULL_ACCS +}; +// +// ACPI +// +STM_RSC_IO_DESC RscPmIo = { + {IO_RANGE, sizeof (STM_RSC_IO_DESC)}, + 0, + 128 +}; + +// +// PCIE MMIO +// +STM_RSC_MMIO_DESC RscPcieMmio = { + {MMIO_RANGE, sizeof (STM_RSC_MMIO_DESC)}, + 0, + 0, // Length + RDWR_ACCS +}; +// +// Local APIC +// +STM_RSC_MMIO_DESC RscApicMmio = { + {MMIO_RANGE, sizeof (STM_RSC_MMIO_DESC)}, + 0, + 0x400, + RDWR_ACCS +}; +// +// Software SMI +// +STM_RSC_TRAPPED_IO_DESC RscSwSmiTrapIo = { + {TRAPPED_IO_RANGE, sizeof (STM_RSC_TRAPPED_IO_DESC)}, + 0xB2, + 2 +}; +// +// End of list +// +STM_RSC_END RscListEnd = { + {END_OF_RESOURCES, sizeof (STM_RSC_END)}, + 0 +}; + +// +// Common PCI devices +// +// +// LPC bridge +// +STM_RSC_PCI_CFG_DESC RscLpcBridgePci = { + {PCI_CFG_RANGE, sizeof (STM_RSC_PCI_CFG_DESC)}, + RDWR_ACCS, 0, + 0, + 0x1000, + 0, + 0, + { + {1, 1, sizeof(STM_PCI_DEVICE_PATH_NODE), LPC_FUNCTION, LPC_DEVICE}, + }, +}; + +// +// Template for MSR resources. +// +STM_RSC_MSR_DESC RscMsrTpl = { + {MACHINE_SPECIFIC_REG, sizeof (STM_RSC_MSR_DESC)}, +}; + +// +// MSR indices to register +// +typedef struct { + uint32_t MsrIndex; + uint64_t ReadMask; + uint64_t WriteMask; +} MSR_TABLE_ENTRY; + +MSR_TABLE_ENTRY MsrTable[] = { + // Index Read Write // MASK64 means need access, MASK0 means no need access. + {SMRR_PHYSBASE_MSR, MASK64, MASK0}, + {SMRR_PHYSMASK_MSR, MASK64, MASK0}, +}; + +/** + + BIOS resources initialization. + +**/ +void ResourceInit(void) +{ + mMaxBus = 255; + + msr_t MsrRead; + + mPmBase = get_pmbase(); + + //mTsegBase = (uint32_t)rdmsr(SMRR_PHYSBASE_MSR) & 0xFFFFF000; + + MsrRead = rdmsr(SMRR_PHYSBASE_MSR); + mTsegBase = MsrRead.lo & 0xFFFFF000; + + //mTsegSize = (uint32_t)(~((uint32_t)rdmsr(SMRR_PHYSMASK_MSR) & 0xFFFFF000) + 1); + + MsrRead = rdmsr(SMRR_PHYSMASK_MSR); + mTsegSize = (~(MsrRead.lo & 0xFFFFF000) + 1); +} + +/** + + Fix up PCIE resource. + +**/ +void FixupPciexResource(void) +{ + // bug, bug, need to fix for coreboot + // + // Find max bus number and PCIEX length + // + //RscPcieMmio.Length = 0x10000000; // 256 MB + //RscPcieMmio.Base = PcdGet64 (PcdPciExpressBaseAddress); +} + +/** + + Add basic resources to BIOS resource database. + +**/ +void +AddSimpleResources(void) +{ + int Status; + msr64_t ReadMsr; + + // + // Fix-up values + // + RscTsegMemory.Base = mTsegBase; + RscTsegMemory.Length = mTsegSize; + + RscPmIo.Base = (uint16_t) mPmBase; + + // + // Local APIC. We assume that all thteads are programmed identically + // despite that it is possible to have individual APIC address for + // each of the threads. If this is the case this programming should + // be corrected. + // + //RscApicMmio.Base = AsmReadMsr64 (IA32_APIC_BASE_MSR_INDEX) & 0xFFFFFF000ull; + + ReadMsr.msr = rdmsr(IA32_APIC_BASE_MSR_INDEX); + RscApicMmio.Base = ReadMsr.uint64 & 0xFFFFFF000ull; + + // + // PCIEX BAR + // + FixupPciexResource (); + + Status = AddPiResource((void *) &RscTsegMemory, 0); + //ASSERT_EFI_ERROR (Status); + Status = AddPiResource((void *) &RscLpcBridgePci, 1); + //ASSERT_EFI_ERROR (Status); +} + +/** + + Add MSR resources to BIOS resource database. + +**/ +void AddMsrResources(void) +{ + uint32_t Status; + uint32_t Index; + + for (Index = 0; Index < sizeof(MsrTable)/sizeof(MsrTable[0]); Index ++) { + + RscMsrTpl.MsrIndex = (uint32_t) MsrTable[Index].MsrIndex; + RscMsrTpl.ReadMask = (uint64_t) MsrTable[Index].ReadMask; + RscMsrTpl.WriteMask = (uint64_t) MsrTable[Index].WriteMask; + + Status = AddPiResource ((void *) &RscMsrTpl, 1); + } +} + +/** + + Add resources to BIOS resource database. + +**/ +void AddResourcesCmd(void) +{ + ResourceInit(); + + AddSimpleResources(); + + AddMsrResources(); +} diff --git a/src/security/intel/stm/StmPlatformResource.h b/src/security/intel/stm/StmPlatformResource.h new file mode 100644 index 0000000..e31e74b --- /dev/null +++ b/src/security/intel/stm/StmPlatformResource.h @@ -0,0 +1,43 @@ +/** @file + STM platform SMM resource + + Copyright (c) 2015, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _STM_PLATFORM_RESOURCE_H_ +#define _STM_PLATFORM_RESOURCE_H_ + +#define MASK0 0 +#define MASK64 0xFFFFFFFFFFFFFFFFull + +// +// LPC +// +#define LPC_BUS 0 +#define LPC_DEVICE 31 +#define LPC_FUNCTION 0 +#define R_ACPI_PM_BASE 0x40 +#define ACPI_PM_BASE_MASK 0xFFF8 + +// +// MSRs +// +#define IA32_APIC_BASE_MSR_INDEX 0x1B +#define SMRR_PHYSBASE_MSR 0x1F2 +#define SMRR_PHYSMASK_MSR 0x1F3 + +/** + + Add resources to BIOS resource database. + +**/ +void AddResourcesCmd(void); +#endif diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c new file mode 100644 index 0000000..bd9cea5 --- /dev/null +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -0,0 +1,128 @@ +/** @file + STM platform SMM API + + Copyright (c) 2015, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made + available under the terms and conditions of the BSD License which + accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <security/intel/stm/StmApi.h> +#include <security/intel/stm/SmmStm.h> +#include <cpu/x86/smm.h> + +#include <stddef.h> +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <stdint.h> + +int LoadStmImage(uint32_t mseg); + +extern bool StmCheckStmImage(void *StmImage, uint32_t StmImageSize); +extern void StmGen4GPageTableIa32(uint32_t PageTableBase); +extern void StmGen4GPageTableX64(uint32_t PageTableBase); + +/** + Load STM image. + + @retval EFI_SUCCESS STM is loaded to MSEG + @retval EFI_BUFFER_TOO_SMALL MSEG is too small + @retval EFI_UNSUPPORTED MSEG is not enabled +**/ +int LoadStmImage(uint32_t mseg) +{ + int Status; + void *MsegBase; + uint32_t StmBufferSize; + uint32_t StmImageSize; + bool StmStatus; + + STM_HEADER *StmHeader; + + // + // Extract STM image from FV + // + MsegBase = (void *) mseg; + StmBufferSize = CONFIG_MSEG_SIZE; + StmImageSize = 0; + + memset((void *) MsegBase, 0, CONFIG_MSEG_SIZE); // clear the mseg + + StmImageSize = cbfs_boot_load_file("stm.bin", MsegBase, StmBufferSize, CBFS_TYPE_RAW); + printk(BIOS_DEBUG, "STM loaded into mseg: 0x%08x size: %u \n", (uint32_t) MsegBase, StmImageSize); /* status is number of bytes loaded */ + + StmStatus = StmCheckStmImage(MsegBase, StmImageSize); + + StmHeader = MsegBase; + + StmGen4GPageTableX64 ((uint32_t)MsegBase + StmHeader->HwStmHdr.Cr3Offset); + + // Debug stuff + + printk(BIOS_DEBUG, "STM Header - Revision: 0x%08x Features: 0x%08x ... Cr3Offset: 0x%08x\n", + StmHeader->HwStmHdr.StmHeaderRevision, + StmHeader->HwStmHdr.MonitorFeatures, + StmHeader->HwStmHdr.Cr3Offset); + printk(BIOS_DEBUG, "STM Header - StaticImageSize: %d Cr3Location: 0x%08x \n", + StmHeader->SwStmHdr.StaticImageSize, + ((uint32_t) MsegBase + StmHeader->HwStmHdr.Cr3Offset)); + + Status = 0; // always return good for now + + return Status; +} + +struct descriptor +{ + uint16_t limit; + uintptr_t base; +} __attribute__((packed)); + + +void ReadGdtr( struct descriptor *gdtr); + +void ReadGdtr( struct descriptor *gdtr) +{ + __asm__ __volatile__ ( + "sgdt %0" + : "=m" (*gdtr) + ); +} + +void SetupSmmDescriptor(void *smbase, int32_t state_size, int32_t apic_id, int32_t entry32_off) +{ + struct descriptor Gdtr; + + TXT_PROCESSOR_SMM_DESCRIPTOR * Psd; + + Psd = smbase + SMM_PSD_OFFSET - (apic_id * state_size); + + printk(BIOS_DEBUG, "Setting up Smm Descriptor - Smbase: %p Psd: %p\n", smbase, Psd); + + memset(Psd, 0, sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR)); + + memcpy(&Psd->Signature, TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE, 8); + Psd->SmmDescriptorVerMajor = TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR; + Psd->SmmDescriptorVerMinor = TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR; + Psd->SmmSmiHandlerRip = (uint64_t)((uint32_t)smbase + SMM_ENTRY_OFFSET + entry32_off); + Psd->LocalApicId = apic_id; + Psd->Size = sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); + Psd->AcpiRsdp = 0; + Psd->BiosHwResourceRequirementsPtr = (uint64_t)((uint32_t)GetStmResource()); + Psd->SmmCs = 0x8; + Psd->SmmDs = 0x10; + Psd->SmmSs = 0x10; + Psd->SmmOtherSegment = 0x10; + Psd->SmmTr = 0x18; + + ReadGdtr(&Gdtr); + + Psd->SmmGdtPtr = Gdtr.base; + Psd->SmmGdtSize = Gdtr.limit + 1; // the stm will subtract, so need to compensate +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec Gerrit-Change-Number: 33234 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

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Change in coreboot[master]: Add configurable ramstage support for minimal PCI scanning
by ron minnich (Code Review) 08 Feb '20

08 Feb '20

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36221 ) Change subject: Add configurable ramstage support for minimal PCI scanning ...................................................................... Add configurable ramstage support for minimal PCI scanning This CL has changes that allow us to enable a configurable ramstage, and one change that allows us to minimize PCI scanning. Minimal scanning is a frequently requested feature. To enable it, we add two new variables to src/Kconfig CONFIGURABLE_RAMSTAGE is the overall variable controlling other options for minimizing the ramstage. MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal PCI scanning. Some devices must be scanned in all cases, such as 0:0.0. To indicate which devices we must scan, we add a new mandatory keyword to sconfig It is used in place of on, off, or hidden, and indicates a device is enabled and mandatory. Mandatory devices are always scanned. When MINIMAL_PCI_SCANNING is enabled, ONLY mandatory devices are scanned. We further add support in src/device/pci_device.c to manage both MINIMAL_PCI_SCANNING and mandatory devices. Finally, to show how this works in practice, we add mandatory keywords to 3 devices on the qemu-q35. This is tested and working on the qemu-q35 target. Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- M src/Kconfig M src/device/pci_device.c M src/include/device/device.h M src/mainboard/emulation/qemu-q35/devicetree.cb M util/sconfig/lex.yy.c_shipped M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.l M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.tab.h_shipped M util/sconfig/sconfig.y 11 files changed, 394 insertions(+), 354 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/36221/1 diff --git a/src/Kconfig b/src/Kconfig index 4c71f28..8fd3d78 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -335,6 +335,21 @@ Skip PCI enumeration logic and only allocate BAR for fixed devices (bootable devices, TPM over GSPI). +config CONFIGURABLE_RAMSTAGE + bool "Enable a configurable ramstage." + default y if ARCH_X86 + help + A configurable ramstage allows you to select which parts of the ramstage + to run. Currently, we can only select a minimal PCI scanning step. + The minimal PCI scanning will only check those parts that are enabled + in the devicetree.cb. By convention none of those devices should be bridges. + +config MINIMAL_PCI_SCANNING + bool "Enable minimal PCI scanning" + depends on CONFIGURABLE_RAMSTAGE + help + If this option is enabled, coreboot will scan only devices + marked as mandatory in devicetree.cb endmenu menu "Mainboard" diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 191c846..4cd0401 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1187,6 +1187,20 @@ * non-existence and single function devices. */ for (devfn = min_devfn; devfn <= max_devfn; devfn++) { + /* When we are not configuring anything, we don't look through + * bridges. Hence, only devices on bus 0 matter. Since we don't + * look through bridges, we don't need to worry about getting here + * for any bus that is non-zero. */ + if (!CONFIG(MINIMAL_PCI_SCANNING)) { + dev = dev_find_slot(0, devfn); + if (!dev) { + printk(BIOS_WARNING, "%#x is NOT static, skipping it\n", devfn); + continue; + } + if (!dev->mandatory) + continue; + } + /* First thing setup the device structure. */ dev = pci_scan_get_dev(bus, devfn); diff --git a/src/include/device/device.h b/src/include/device/device.h index 405d816e..db36ed3 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -129,6 +129,7 @@ unsigned int on_mainboard : 1; unsigned int disable_pcie_aspm : 1; unsigned int hidden : 1; /* set if we should hide from UI */ + unsigned int mandatory : 1; /* set if this device is used even in minimum PCI cases */ u8 command; /* Base registers for this device. I/O, MEM and Expansion ROM */ diff --git a/src/mainboard/emulation/qemu-q35/devicetree.cb b/src/mainboard/emulation/qemu-q35/devicetree.cb index 671a2d6..fb42e8a 100644 --- a/src/mainboard/emulation/qemu-q35/devicetree.cb +++ b/src/mainboard/emulation/qemu-q35/devicetree.cb @@ -5,10 +5,10 @@ end end device domain 0 on - device pci 0.0 on end # northbridge (q35) + device pci 0.0 mandatory end # northbridge (q35) chip southbridge/intel/i82801ix # present unconditionally - device pci 1f.0 on end # LPC + device pci 1f.0 mandatory end # LPC device pci 1f.2 on end # SATA device pci 1f.3 on end # SMBus @@ -19,7 +19,7 @@ device pci 1a.2 on end # UHCI #6 device pci 1a.7 on end # EHCI #2 device pci 1b.0 on end # HD Audio - device pci 1c.0 on end # PCIe Port #1 + device pci 1c.0 mandatory end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 device pci 1c.2 on end # PCIe Port #3 device pci 1c.3 on end # PCIe Port #4 diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index 14ffeff..c8cc44d 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -6,7 +6,7 @@ #define FLEX_SCANNER #define YY_FLEX_MAJOR_VERSION 2 #define YY_FLEX_MINOR_VERSION 6 -#define YY_FLEX_SUBMINOR_VERSION 1 +#define YY_FLEX_SUBMINOR_VERSION 4 #if YY_FLEX_SUBMINOR_VERSION > 0 #define FLEX_BETA #endif @@ -81,10 +81,16 @@ #define UINT32_MAX (4294967295U) #endif +#ifndef SIZE_MAX +#define SIZE_MAX (~(size_t)0) +#endif + #endif /* ! C99 */ #endif /* ! FLEXINT_H */ +/* begin standard C++ headers. */ + /* TODO: this is always defined, so inline it */ #define yyconst const @@ -97,32 +103,26 @@ /* Returned upon end-of-file. */ #define YY_NULL 0 -/* Promotes a possibly negative, possibly signed char to an unsigned - * integer for use as an array index. If the signed char is negative, - * we want to instead treat it as an 8-bit unsigned char, hence the - * double cast. +/* Promotes a possibly negative, possibly signed char to an + * integer in range [0..255] for use as an array index. */ -#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c) +#define YY_SC_TO_UI(c) ((YY_CHAR) (c)) /* Enter a start condition. This macro really ought to take a parameter, * but we do it the disgusting crufty way forced on us by the ()-less * definition of BEGIN. */ #define BEGIN (yy_start) = 1 + 2 * - /* Translate the current start state into a value that can be later handed * to BEGIN to return to the state. The YYSTATE alias is for lex * compatibility. */ #define YY_START (((yy_start) - 1) / 2) #define YYSTATE YY_START - /* Action number for EOF rule of a given start state. */ #define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1) - /* Special action meaning "start processing a new file". */ -#define YY_NEW_FILE yyrestart(yyin ) - +#define YY_NEW_FILE yyrestart( yyin ) #define YY_END_OF_BUFFER_CHAR 0 /* Size of default input buffer. */ @@ -159,7 +159,7 @@ #define EOB_ACT_CONTINUE_SCAN 0 #define EOB_ACT_END_OF_FILE 1 #define EOB_ACT_LAST_MATCH 2 - + #define YY_LESS_LINENO(n) #define YY_LINENO_REWIND_TO(ptr) @@ -168,7 +168,7 @@ do \ { \ /* Undo effects of setting up yytext. */ \ - yy_size_t yyless_macro_arg = (n); \ + int yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ *yy_cp = (yy_hold_char); \ YY_RESTORE_YY_MORE_OFFSET \ @@ -176,7 +176,6 @@ YY_DO_BEFORE_ACTION; /* set up yytext again */ \ } \ while ( 0 ) - #define unput(c) yyunput( c, (yytext_ptr) ) #ifndef YY_STRUCT_YY_BUFFER_STATE @@ -258,7 +257,6 @@ #define YY_CURRENT_BUFFER ( (yy_buffer_stack) \ ? (yy_buffer_stack)[(yy_buffer_stack_top)] \ : NULL) - /* Same as previous macro, but useful when we know that the buffer stack is not * NULL or when we need an lvalue. For internal use only. */ @@ -279,62 +277,56 @@ */ static int yy_did_buffer_switch_on_eof; -void yyrestart (FILE *input_file ); -void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer ); -YY_BUFFER_STATE yy_create_buffer (FILE *file,int size ); -void yy_delete_buffer (YY_BUFFER_STATE b ); -void yy_flush_buffer (YY_BUFFER_STATE b ); -void yypush_buffer_state (YY_BUFFER_STATE new_buffer ); -void yypop_buffer_state (void ); +void yyrestart ( FILE *input_file ); +void yy_switch_to_buffer ( YY_BUFFER_STATE new_buffer ); +YY_BUFFER_STATE yy_create_buffer ( FILE *file, int size ); +void yy_delete_buffer ( YY_BUFFER_STATE b ); +void yy_flush_buffer ( YY_BUFFER_STATE b ); +void yypush_buffer_state ( YY_BUFFER_STATE new_buffer ); +void yypop_buffer_state ( void ); -static void yyensure_buffer_stack (void ); -static void yy_load_buffer_state (void ); -static void yy_init_buffer (YY_BUFFER_STATE b,FILE *file ); +static void yyensure_buffer_stack ( void ); +static void yy_load_buffer_state ( void ); +static void yy_init_buffer ( YY_BUFFER_STATE b, FILE *file ); +#define YY_FLUSH_BUFFER yy_flush_buffer( YY_CURRENT_BUFFER ) -#define YY_FLUSH_BUFFER yy_flush_buffer(YY_CURRENT_BUFFER ) +YY_BUFFER_STATE yy_scan_buffer ( char *base, yy_size_t size ); +YY_BUFFER_STATE yy_scan_string ( const char *yy_str ); +YY_BUFFER_STATE yy_scan_bytes ( const char *bytes, int len ); -YY_BUFFER_STATE yy_scan_buffer (char *base,yy_size_t size ); -YY_BUFFER_STATE yy_scan_string (yyconst char *yy_str ); -YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,int len ); - -void *yyalloc (yy_size_t ); -void *yyrealloc (void *,yy_size_t ); -void yyfree (void * ); +void *yyalloc ( yy_size_t ); +void *yyrealloc ( void *, yy_size_t ); +void yyfree ( void * ); #define yy_new_buffer yy_create_buffer - #define yy_set_interactive(is_interactive) \ { \ if ( ! YY_CURRENT_BUFFER ){ \ yyensure_buffer_stack (); \ YY_CURRENT_BUFFER_LVALUE = \ - yy_create_buffer(yyin,YY_BUF_SIZE ); \ + yy_create_buffer( yyin, YY_BUF_SIZE ); \ } \ YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \ } - #define yy_set_bol(at_bol) \ { \ if ( ! YY_CURRENT_BUFFER ){\ yyensure_buffer_stack (); \ YY_CURRENT_BUFFER_LVALUE = \ - yy_create_buffer(yyin,YY_BUF_SIZE ); \ + yy_create_buffer( yyin, YY_BUF_SIZE ); \ } \ YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \ } - #define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol) /* Begin user sect3 */ - -typedef unsigned char YY_CHAR; +typedef flex_uint8_t YY_CHAR; FILE *yyin = NULL, *yyout = NULL; typedef int yy_state_type; extern int yylineno; - int yylineno = 1; extern char *yytext; @@ -343,10 +335,10 @@ #endif #define yytext_ptr yytext -static yy_state_type yy_get_previous_state (void ); -static yy_state_type yy_try_NUL_trans (yy_state_type current_state ); -static int yy_get_next_buffer (void ); -static void yynoreturn yy_fatal_error (yyconst char* msg ); +static yy_state_type yy_get_previous_state ( void ); +static yy_state_type yy_try_NUL_trans ( yy_state_type current_state ); +static int yy_get_next_buffer ( void ); +static void yynoreturn yy_fatal_error ( const char* msg ); /* Done after the current pattern has been matched and before the * corresponding action - sets up yytext. @@ -357,9 +349,8 @@ (yy_hold_char) = *yy_cp; \ *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; - -#define YY_NUM_RULES 38 -#define YY_END_OF_BUFFER 39 +#define YY_NUM_RULES 39 +#define YY_END_OF_BUFFER 40 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -367,28 +358,29 @@ flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static yyconst flex_int16_t yy_accept[160] = +static const flex_int16_t yy_accept[168] = { 0, - 0, 0, 39, 37, 1, 3, 37, 37, 37, 32, - 32, 30, 33, 37, 33, 33, 33, 37, 37, 37, - 37, 37, 37, 37, 37, 37, 37, 37, 1, 3, - 37, 0, 37, 37, 0, 2, 32, 33, 37, 37, - 37, 37, 33, 37, 37, 37, 37, 37, 37, 37, - 24, 37, 37, 37, 37, 7, 37, 37, 37, 37, - 37, 37, 37, 36, 36, 37, 0, 31, 37, 37, - 16, 37, 37, 23, 28, 37, 37, 13, 37, 37, - 22, 37, 37, 8, 10, 12, 37, 37, 20, 37, - 21, 37, 0, 34, 4, 37, 37, 37, 37, 37, + 0, 0, 40, 38, 1, 3, 38, 38, 38, 33, + 33, 31, 34, 38, 34, 34, 34, 38, 38, 38, + 38, 38, 38, 38, 38, 38, 38, 38, 1, 3, + 38, 0, 38, 38, 0, 2, 33, 34, 38, 38, + 38, 38, 34, 38, 38, 38, 38, 38, 38, 38, + 25, 38, 38, 38, 38, 38, 7, 38, 38, 38, + 38, 38, 38, 38, 37, 37, 38, 0, 32, 38, + 38, 17, 38, 38, 24, 29, 38, 38, 14, 38, + 38, 23, 38, 38, 38, 8, 11, 13, 38, 38, + 21, 38, 22, 38, 0, 35, 4, 38, 38, 38, - 37, 37, 37, 19, 37, 37, 37, 35, 35, 37, - 37, 37, 37, 37, 37, 37, 14, 37, 37, 37, - 37, 5, 17, 37, 9, 37, 11, 37, 37, 37, - 37, 18, 26, 37, 37, 37, 37, 37, 37, 6, - 37, 37, 37, 37, 37, 37, 37, 25, 37, 37, - 15, 37, 27, 37, 37, 37, 37, 29, 0 + 38, 38, 38, 38, 38, 38, 20, 38, 38, 38, + 36, 36, 38, 38, 38, 38, 38, 38, 38, 15, + 38, 38, 38, 38, 38, 5, 18, 38, 9, 38, + 12, 38, 38, 38, 38, 38, 19, 27, 38, 38, + 38, 38, 38, 38, 38, 38, 6, 38, 38, 38, + 38, 10, 38, 38, 38, 26, 38, 38, 16, 38, + 28, 38, 38, 38, 38, 30, 0 } ; -static yyconst YY_CHAR yy_ec[256] = +static const YY_CHAR yy_ec[256] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 3, 1, 1, 4, 1, 1, 1, 1, 1, 1, 1, @@ -420,7 +412,7 @@ 1, 1, 1, 1, 1 } ; -static yyconst YY_CHAR yy_meta[39] = +static const YY_CHAR yy_meta[39] = { 0, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, @@ -428,114 +420,118 @@ 1, 1, 1, 1, 1, 1, 1, 1 } ; -static yyconst flex_uint16_t yy_base[167] = +static const flex_int16_t yy_base[175] = { 0, - 0, 0, 227, 0, 224, 228, 222, 37, 41, 38, - 187, 0, 44, 209, 54, 78, 60, 201, 196, 45, - 203, 192, 42, 47, 197, 62, 184, 0, 214, 228, - 77, 210, 88, 69, 211, 228, 0, 87, 104, 198, - 187, 176, 93, 183, 178, 188, 179, 186, 186, 180, - 186, 171, 171, 175, 177, 0, 173, 167, 173, 177, - 169, 175, 174, 0, 228, 101, 186, 0, 179, 159, - 172, 162, 169, 0, 0, 164, 164, 0, 162, 152, - 0, 156, 151, 0, 0, 0, 154, 153, 0, 144, - 0, 171, 170, 0, 0, 155, 154, 147, 139, 149, + 0, 0, 235, 0, 232, 236, 230, 37, 41, 38, + 195, 0, 44, 217, 54, 78, 60, 209, 204, 45, + 211, 48, 42, 52, 206, 62, 193, 0, 223, 236, + 88, 219, 93, 79, 220, 236, 0, 93, 104, 207, + 196, 185, 96, 192, 187, 197, 188, 195, 195, 189, + 195, 180, 180, 181, 183, 185, 0, 181, 175, 181, + 185, 177, 183, 182, 0, 236, 115, 194, 0, 187, + 167, 180, 170, 177, 0, 0, 172, 172, 0, 170, + 160, 0, 164, 168, 158, 0, 0, 0, 161, 160, + 0, 151, 0, 178, 177, 0, 0, 162, 161, 154, - 137, 143, 148, 0, 133, 136, 126, 0, 228, 137, - 141, 133, 135, 131, 133, 138, 0, 122, 122, 121, - 118, 0, 0, 133, 0, 117, 134, 128, 132, 113, - 113, 0, 0, 120, 112, 110, 121, 94, 95, 0, - 94, 92, 97, 86, 85, 84, 76, 0, 71, 78, - 0, 67, 0, 61, 55, 32, 29, 0, 228, 40, - 129, 131, 133, 135, 137, 139 + 146, 156, 144, 150, 155, 156, 0, 139, 142, 132, + 0, 236, 143, 147, 139, 141, 137, 139, 144, 0, + 128, 127, 127, 126, 123, 0, 0, 138, 0, 122, + 139, 125, 132, 136, 117, 117, 0, 0, 124, 116, + 115, 113, 124, 97, 98, 91, 0, 102, 100, 98, + 83, 0, 80, 83, 74, 0, 60, 63, 0, 63, + 0, 56, 51, 33, 29, 0, 236, 40, 132, 134, + 136, 138, 140, 142 } ; -static yyconst flex_int16_t yy_def[167] = +static const flex_int16_t yy_def[175] = { 0, - 159, 1, 159, 160, 159, 159, 160, 161, 162, 160, - 10, 160, 10, 160, 10, 10, 10, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 159, 159, - 161, 163, 164, 162, 165, 159, 10, 10, 10, 160, - 160, 160, 10, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 159, 164, 166, 39, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 159, 160, 160, 160, 160, 160, 160, 160, + 167, 1, 167, 168, 167, 167, 168, 169, 170, 168, + 10, 168, 10, 168, 10, 10, 10, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 167, 167, + 169, 171, 172, 170, 173, 167, 10, 10, 10, 168, + 168, 168, 10, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 167, 172, 174, 39, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 167, 168, 168, 168, 168, 168, - 160, 160, 160, 160, 160, 160, 160, 160, 159, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 0, 159, - 159, 159, 159, 159, 159, 159 + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 167, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 0, 167, 167, 167, + 167, 167, 167, 167 } ; -static yyconst flex_uint16_t yy_nxt[267] = +static const flex_int16_t yy_nxt[275] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, 13, 13, 14, 4, 4, 4, 13, 13, 15, 16, 17, 13, 18, 19, 20, 21, 22, 4, 23, 24, 4, 25, 26, 4, 27, 4, 4, 4, 32, 32, - 28, 33, 35, 36, 37, 37, 37, 158, 38, 38, + 28, 33, 35, 36, 37, 37, 37, 166, 38, 38, 38, 38, 38, 49, 38, 38, 38, 38, 38, 38, - 38, 38, 38, 55, 157, 57, 38, 38, 38, 56, - 35, 36, 50, 51, 58, 156, 52, 41, 32, 32, - 155, 64, 154, 42, 38, 38, 38, 46, 60, 67, - 67, 61, 28, 38, 38, 38, 62, 153, 43, 38, + 38, 38, 38, 56, 54, 165, 38, 38, 38, 57, + 58, 164, 50, 51, 55, 163, 52, 41, 162, 59, + 35, 36, 161, 42, 38, 38, 38, 46, 61, 32, + 32, 62, 65, 160, 68, 68, 63, 28, 43, 38, - 38, 38, 67, 67, 152, 92, 44, 151, 150, 45, - 68, 68, 68, 149, 68, 68, 148, 147, 146, 145, - 68, 68, 68, 68, 68, 68, 144, 143, 72, 31, - 31, 34, 34, 32, 32, 66, 66, 35, 35, 67, - 67, 142, 141, 140, 139, 138, 137, 136, 135, 134, + 38, 38, 38, 38, 38, 159, 44, 158, 157, 45, + 69, 69, 69, 156, 69, 69, 68, 68, 155, 94, + 69, 69, 69, 69, 69, 69, 154, 153, 152, 151, + 150, 73, 31, 31, 34, 34, 32, 32, 67, 67, + 35, 35, 68, 68, 149, 148, 147, 146, 145, 144, + 143, 142, 141, 140, 139, 138, 137, 136, 135, 134, 133, 132, 131, 130, 129, 128, 127, 126, 125, 124, 123, 122, 121, 120, 119, 118, 117, 116, 115, 114, 113, 112, 111, 110, 109, 108, 107, 106, 105, 104, - 103, 102, 101, 100, 99, 98, 97, 96, 95, 94, - 93, 91, 90, 89, 88, 87, 86, 85, 84, 83, + 103, 102, 101, 100, 99, 98, 97, 96, 95, 93, - 82, 81, 80, 79, 78, 77, 76, 75, 74, 73, - 71, 70, 69, 36, 65, 29, 63, 59, 54, 53, - 48, 47, 40, 39, 30, 29, 159, 3, 159, 159, - 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, - 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, - 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, - 159, 159, 159, 159, 159, 159 + 92, 91, 90, 89, 88, 87, 86, 85, 84, 83, + 82, 81, 80, 79, 78, 77, 76, 75, 74, 72, + 71, 70, 36, 66, 29, 64, 60, 53, 48, 47, + 40, 39, 30, 29, 167, 3, 167, 167, 167, 167, + 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, + 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, + 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, + 167, 167, 167, 167 } ; -static yyconst flex_int16_t yy_chk[267] = +static const flex_int16_t yy_chk[275] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, - 160, 8, 9, 9, 10, 10, 10, 157, 10, 10, + 168, 8, 9, 9, 10, 10, 10, 165, 10, 10, 13, 13, 13, 20, 10, 10, 10, 10, 10, 10, - 15, 15, 15, 23, 156, 24, 17, 17, 17, 23, - 34, 34, 20, 20, 24, 155, 20, 15, 31, 31, - 154, 31, 152, 15, 16, 16, 16, 17, 26, 33, - 33, 26, 33, 38, 38, 38, 26, 150, 16, 43, + 15, 15, 15, 23, 22, 164, 17, 17, 17, 23, + 24, 163, 20, 20, 22, 162, 20, 15, 160, 24, + 34, 34, 158, 15, 16, 16, 16, 17, 26, 31, + 31, 26, 31, 157, 33, 33, 26, 33, 16, 38, - 43, 43, 66, 66, 149, 66, 16, 147, 146, 16, - 39, 39, 39, 145, 39, 39, 144, 143, 142, 141, - 39, 39, 39, 39, 39, 39, 139, 138, 43, 161, - 161, 162, 162, 163, 163, 164, 164, 165, 165, 166, - 166, 137, 136, 135, 134, 131, 130, 129, 128, 127, - 126, 124, 121, 120, 119, 118, 116, 115, 114, 113, - 112, 111, 110, 107, 106, 105, 103, 102, 101, 100, - 99, 98, 97, 96, 93, 92, 90, 88, 87, 83, - 82, 80, 79, 77, 76, 73, 72, 71, 70, 69, - 67, 63, 62, 61, 60, 59, 58, 57, 55, 54, + 38, 38, 43, 43, 43, 155, 16, 154, 153, 16, + 39, 39, 39, 151, 39, 39, 67, 67, 150, 67, + 39, 39, 39, 39, 39, 39, 149, 148, 146, 145, + 144, 43, 169, 169, 170, 170, 171, 171, 172, 172, + 173, 173, 174, 174, 143, 142, 141, 140, 139, 136, + 135, 134, 133, 132, 131, 130, 128, 125, 124, 123, + 122, 121, 119, 118, 117, 116, 115, 114, 113, 110, + 109, 108, 106, 105, 104, 103, 102, 101, 100, 99, + 98, 95, 94, 92, 90, 89, 85, 84, 83, 81, + 80, 78, 77, 74, 73, 72, 71, 70, 68, 64, - 53, 52, 51, 50, 49, 48, 47, 46, 45, 44, - 42, 41, 40, 35, 32, 29, 27, 25, 22, 21, - 19, 18, 14, 11, 7, 5, 3, 159, 159, 159, - 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, - 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, - 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, - 159, 159, 159, 159, 159, 159 + 63, 62, 61, 60, 59, 58, 56, 55, 54, 53, + 52, 51, 50, 49, 48, 47, 46, 45, 44, 42, + 41, 40, 35, 32, 29, 27, 25, 21, 19, 18, + 14, 11, 7, 5, 3, 167, 167, 167, 167, 167, + 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, + 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, + 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, + 167, 167, 167, 167 } ; static yy_state_type yy_last_accepting_state; @@ -586,36 +582,36 @@ #define YY_EXTRA_TYPE void * #endif -static int yy_init_globals (void ); +static int yy_init_globals ( void ); /* Accessor methods to globals. These are made visible to non-reentrant scanners for convenience. */ -int yylex_destroy (void ); +int yylex_destroy ( void ); -int yyget_debug (void ); +int yyget_debug ( void ); -void yyset_debug (int debug_flag ); +void yyset_debug ( int debug_flag ); -YY_EXTRA_TYPE yyget_extra (void ); +YY_EXTRA_TYPE yyget_extra ( void ); -void yyset_extra (YY_EXTRA_TYPE user_defined ); +void yyset_extra ( YY_EXTRA_TYPE user_defined ); -FILE *yyget_in (void ); +FILE *yyget_in ( void ); -void yyset_in (FILE * _in_str ); +void yyset_in ( FILE * _in_str ); -FILE *yyget_out (void ); +FILE *yyget_out ( void ); -void yyset_out (FILE * _out_str ); +void yyset_out ( FILE * _out_str ); - int yyget_leng (void ); + int yyget_leng ( void ); -char *yyget_text (void ); +char *yyget_text ( void ); -int yyget_lineno (void ); +int yyget_lineno ( void ); -void yyset_lineno (int _line_number ); +void yyset_lineno ( int _line_number ); /* Macros after this point can all be overridden by user definitions in * section 1. @@ -623,32 +619,31 @@ #ifndef YY_SKIP_YYWRAP #ifdef __cplusplus -extern "C" int yywrap (void ); +extern "C" int yywrap ( void ); #else -extern int yywrap (void ); +extern int yywrap ( void ); #endif #endif #ifndef YY_NO_UNPUT - static void yyunput (int c,char *buf_ptr ); + static void yyunput ( int c, char *buf_ptr ); #endif #ifndef yytext_ptr -static void yy_flex_strncpy (char *,yyconst char *,int ); +static void yy_flex_strncpy ( char *, const char *, int ); #endif #ifdef YY_NEED_STRLEN -static int yy_flex_strlen (yyconst char * ); +static int yy_flex_strlen ( const char * ); #endif #ifndef YY_NO_INPUT - #ifdef __cplusplus -static int yyinput (void ); +static int yyinput ( void ); #else -static int input (void ); +static int input ( void ); #endif #endif @@ -781,10 +776,10 @@ if ( ! YY_CURRENT_BUFFER ) { yyensure_buffer_stack (); YY_CURRENT_BUFFER_LVALUE = - yy_create_buffer(yyin,YY_BUF_SIZE ); + yy_create_buffer( yyin, YY_BUF_SIZE ); } - yy_load_buffer_state( ); + yy_load_buffer_state( ); } { @@ -814,13 +809,13 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 160 ) - yy_c = yy_meta[(unsigned int) yy_c]; + if ( yy_current_state >= 168 ) + yy_c = yy_meta[yy_c]; } - yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c]; + yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 228 ); + while ( yy_base[yy_current_state] != 236 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -880,95 +875,95 @@ YY_BREAK case 9: YY_RULE_SETUP -{yylval.number=3; return(HIDDEN);} +{yylval.number=3; return(STATUS);} YY_BREAK case 10: YY_RULE_SETUP -{yylval.number=PCI; return(BUS);} +{yylval.number=5; return(STATUS);} YY_BREAK case 11: YY_RULE_SETUP -{yylval.number=IOAPIC; return(BUS);} +{yylval.number=PCI; return(BUS);} YY_BREAK case 12: YY_RULE_SETUP -{yylval.number=PNP; return(BUS);} +{yylval.number=IOAPIC; return(BUS);} YY_BREAK case 13: YY_RULE_SETUP -{yylval.number=I2C; return(BUS);} +{yylval.number=PNP; return(BUS);} YY_BREAK case 14: YY_RULE_SETUP -{yylval.number=APIC; return(BUS);} +{yylval.number=I2C; return(BUS);} YY_BREAK case 15: YY_RULE_SETUP -{yylval.number=CPU_CLUSTER; return(BUS);} +{yylval.number=APIC; return(BUS);} YY_BREAK case 16: YY_RULE_SETUP -{yylval.number=CPU; return(BUS);} +{yylval.number=CPU_CLUSTER; return(BUS);} YY_BREAK case 17: YY_RULE_SETUP -{yylval.number=DOMAIN; return(BUS);} +{yylval.number=CPU; return(BUS);} YY_BREAK case 18: YY_RULE_SETUP -{yylval.number=GENERIC; return(BUS);} +{yylval.number=DOMAIN; return(BUS);} YY_BREAK case 19: YY_RULE_SETUP -{yylval.number=MMIO; return(BUS);} +{yylval.number=GENERIC; return(BUS);} YY_BREAK case 20: YY_RULE_SETUP -{yylval.number=SPI; return(BUS);} +{yylval.number=MMIO; return(BUS);} YY_BREAK case 21: YY_RULE_SETUP -{yylval.number=USB; return(BUS);} +{yylval.number=SPI; return(BUS);} YY_BREAK case 22: YY_RULE_SETUP -{yylval.number=IRQ; return(RESOURCE);} +{yylval.number=USB; return(BUS);} YY_BREAK case 23: YY_RULE_SETUP -{yylval.number=DRQ; return(RESOURCE);} +{yylval.number=IRQ; return(RESOURCE);} YY_BREAK case 24: YY_RULE_SETUP -{yylval.number=IO; return(RESOURCE);} +{yylval.number=DRQ; return(RESOURCE);} YY_BREAK case 25: YY_RULE_SETUP -{return(IOAPIC_IRQ);} +{yylval.number=IO; return(RESOURCE);} YY_BREAK case 26: YY_RULE_SETUP -{return(INHERIT);} +{return(IOAPIC_IRQ);} YY_BREAK case 27: YY_RULE_SETUP -{return(SUBSYSTEMID);} +{return(INHERIT);} YY_BREAK case 28: YY_RULE_SETUP -{return(END);} +{return(SUBSYSTEMID);} YY_BREAK case 29: YY_RULE_SETUP -{return(SLOT_DESC);} +{return(END);} YY_BREAK case 30: YY_RULE_SETUP -{return(EQUALS);} +{return(SLOT_DESC);} YY_BREAK case 31: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(EQUALS);} YY_BREAK case 32: YY_RULE_SETUP @@ -980,12 +975,11 @@ YY_BREAK case 34: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 35: -/* rule 35 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} YY_BREAK case 36: /* rule 36 can match eol */ @@ -993,10 +987,15 @@ {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 37: +/* rule 37 can match eol */ +YY_RULE_SETUP +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} + YY_BREAK +case 38: YY_RULE_SETUP {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} YY_BREAK -case 38: +case 39: YY_RULE_SETUP ECHO; YY_BREAK @@ -1077,7 +1076,7 @@ { (yy_did_buffer_switch_on_eof) = 0; - if ( yywrap( ) ) + if ( yywrap( ) ) { /* Note: because we've taken care in * yy_get_next_buffer() to have set up @@ -1144,7 +1143,7 @@ { char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; char *source = (yytext_ptr); - yy_size_t number_to_move, i; + int number_to_move, i; int ret_val; if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] ) @@ -1173,7 +1172,7 @@ /* Try to read more data. */ /* First move last chars to start of buffer. */ - number_to_move = (yy_size_t) ((yy_c_buf_p) - (yytext_ptr)) - 1; + number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr) - 1); for ( i = 0; i < number_to_move; ++i ) *(dest++) = *(source++); @@ -1209,7 +1208,8 @@ b->yy_ch_buf = (char *) /* Include room in for 2 EOB chars. */ - yyrealloc((void *) b->yy_ch_buf,(yy_size_t) (b->yy_buf_size + 2) ); + yyrealloc( (void *) b->yy_ch_buf, + (yy_size_t) (b->yy_buf_size + 2) ); } else /* Can't grow it, we don't own it. */ @@ -1241,7 +1241,7 @@ if ( number_to_move == YY_MORE_ADJ ) { ret_val = EOB_ACT_END_OF_FILE; - yyrestart(yyin ); + yyrestart( yyin ); } else @@ -1255,12 +1255,15 @@ else ret_val = EOB_ACT_CONTINUE_SCAN; - if ((int) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { + if (((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { /* Extend the array by 50%, plus the number we really need. */ int new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); - YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,(yy_size_t) new_size ); + YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc( + (void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf, (yy_size_t) new_size ); if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" ); + /* "- 2" to take care of EOB's */ + YY_CURRENT_BUFFER_LVALUE->yy_buf_size = (int) (new_size - 2); } (yy_n_chars) += number_to_move; @@ -1292,10 +1295,10 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 160 ) - yy_c = yy_meta[(unsigned int) yy_c]; + if ( yy_current_state >= 168 ) + yy_c = yy_meta[yy_c]; } - yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c]; + yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; } return yy_current_state; @@ -1320,11 +1323,11 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 160 ) - yy_c = yy_meta[(unsigned int) yy_c]; + if ( yy_current_state >= 168 ) + yy_c = yy_meta[yy_c]; } - yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c]; - yy_is_jam = (yy_current_state == 159); + yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; + yy_is_jam = (yy_current_state == 167); return yy_is_jam ? 0 : yy_current_state; } @@ -1394,7 +1397,7 @@ else { /* need more input */ - int offset = (yy_c_buf_p) - (yytext_ptr); + int offset = (int) ((yy_c_buf_p) - (yytext_ptr)); ++(yy_c_buf_p); switch ( yy_get_next_buffer( ) ) @@ -1411,13 +1414,13 @@ */ /* Reset buffer status. */ - yyrestart(yyin ); + yyrestart( yyin ); /*FALLTHROUGH*/ case EOB_ACT_END_OF_FILE: { - if ( yywrap( ) ) + if ( yywrap( ) ) return 0; if ( ! (yy_did_buffer_switch_on_eof) ) @@ -1455,11 +1458,11 @@ if ( ! YY_CURRENT_BUFFER ){ yyensure_buffer_stack (); YY_CURRENT_BUFFER_LVALUE = - yy_create_buffer(yyin,YY_BUF_SIZE ); + yy_create_buffer( yyin, YY_BUF_SIZE ); } - yy_init_buffer(YY_CURRENT_BUFFER,input_file ); - yy_load_buffer_state( ); + yy_init_buffer( YY_CURRENT_BUFFER, input_file ); + yy_load_buffer_state( ); } /** Switch to a different input buffer. @@ -1487,7 +1490,7 @@ } YY_CURRENT_BUFFER_LVALUE = new_buffer; - yy_load_buffer_state( ); + yy_load_buffer_state( ); /* We don't actually know whether we did this switch during * EOF (yywrap()) processing, but the only time this flag @@ -1515,7 +1518,7 @@ { YY_BUFFER_STATE b; - b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) ); + b = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) ); if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); @@ -1524,13 +1527,13 @@ /* yy_ch_buf has to be 2 characters longer than the size given because * we need to put in 2 end-of-buffer characters. */ - b->yy_ch_buf = (char *) yyalloc((yy_size_t) (b->yy_buf_size + 2) ); + b->yy_ch_buf = (char *) yyalloc( (yy_size_t) (b->yy_buf_size + 2) ); if ( ! b->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); b->yy_is_our_buffer = 1; - yy_init_buffer(b,file ); + yy_init_buffer( b, file ); return b; } @@ -1549,9 +1552,9 @@ YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0; if ( b->yy_is_our_buffer ) - yyfree((void *) b->yy_ch_buf ); + yyfree( (void *) b->yy_ch_buf ); - yyfree((void *) b ); + yyfree( (void *) b ); } /* Initializes or reinitializes a buffer. @@ -1563,7 +1566,7 @@ { int oerrno = errno; - yy_flush_buffer(b ); + yy_flush_buffer( b ); b->yy_input_file = file; b->yy_fill_buffer = 1; @@ -1606,7 +1609,7 @@ b->yy_buffer_status = YY_BUFFER_NEW; if ( b == YY_CURRENT_BUFFER ) - yy_load_buffer_state( ); + yy_load_buffer_state( ); } /** Pushes the new state onto the stack. The new state becomes @@ -1637,7 +1640,7 @@ YY_CURRENT_BUFFER_LVALUE = new_buffer; /* copied from yy_switch_to_buffer. */ - yy_load_buffer_state( ); + yy_load_buffer_state( ); (yy_did_buffer_switch_on_eof) = 1; } @@ -1656,7 +1659,7 @@ --(yy_buffer_stack_top); if (YY_CURRENT_BUFFER) { - yy_load_buffer_state( ); + yy_load_buffer_state( ); (yy_did_buffer_switch_on_eof) = 1; } } @@ -1666,7 +1669,7 @@ */ static void yyensure_buffer_stack (void) { - int num_to_alloc; + yy_size_t num_to_alloc; if (!(yy_buffer_stack)) { @@ -1723,7 +1726,7 @@ /* They forgot to leave room for the EOB's. */ return NULL; - b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) ); + b = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) ); if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" ); @@ -1737,7 +1740,7 @@ b->yy_fill_buffer = 0; b->yy_buffer_status = YY_BUFFER_NEW; - yy_switch_to_buffer(b ); + yy_switch_to_buffer( b ); return b; } @@ -1750,10 +1753,10 @@ * @note If you want to scan bytes that may contain NUL values, then use * yy_scan_bytes() instead. */ -YY_BUFFER_STATE yy_scan_string (yyconst char * yystr ) +YY_BUFFER_STATE yy_scan_string (const char * yystr ) { - return yy_scan_bytes(yystr,(int) strlen(yystr) ); + return yy_scan_bytes( yystr, (int) strlen(yystr) ); } /** Setup the input buffer state to scan the given bytes. The next call to yylex() will @@ -1763,7 +1766,7 @@ * * @return the newly allocated buffer state object. */ -YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, int _yybytes_len ) +YY_BUFFER_STATE yy_scan_bytes (const char * yybytes, int _yybytes_len ) { YY_BUFFER_STATE b; char *buf; @@ -1772,7 +1775,7 @@ /* Get memory for full buffer, including space for trailing EOB's. */ n = (yy_size_t) (_yybytes_len + 2); - buf = (char *) yyalloc(n ); + buf = (char *) yyalloc( n ); if ( ! buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" ); @@ -1781,7 +1784,7 @@ buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR; - b = yy_scan_buffer(buf,n ); + b = yy_scan_buffer( buf, n ); if ( ! b ) YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" ); @@ -1797,9 +1800,9 @@ #define YY_EXIT_FAILURE 2 #endif -static void yynoreturn yy_fatal_error (yyconst char* msg ) +static void yynoreturn yy_fatal_error (const char* msg ) { - (void) fprintf( stderr, "%s\n", msg ); + fprintf( stderr, "%s\n", msg ); exit( YY_EXIT_FAILURE ); } @@ -1810,7 +1813,7 @@ do \ { \ /* Undo effects of setting up yytext. */ \ - yy_size_t yyless_macro_arg = (n); \ + int yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ yytext[yyleng] = (yy_hold_char); \ (yy_c_buf_p) = yytext + yyless_macro_arg; \ @@ -1934,7 +1937,7 @@ /* Pop the buffer stack, destroying each element. */ while(YY_CURRENT_BUFFER){ - yy_delete_buffer(YY_CURRENT_BUFFER ); + yy_delete_buffer( YY_CURRENT_BUFFER ); YY_CURRENT_BUFFER_LVALUE = NULL; yypop_buffer_state(); } @@ -1955,7 +1958,7 @@ */ #ifndef yytext_ptr -static void yy_flex_strncpy (char* s1, yyconst char * s2, int n ) +static void yy_flex_strncpy (char* s1, const char * s2, int n ) { int i; @@ -1965,7 +1968,7 @@ #endif #ifdef YY_NEED_STRLEN -static int yy_flex_strlen (yyconst char * s ) +static int yy_flex_strlen (const char * s ) { int n; for ( n = 0; s[n]; ++n ) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 5c23333..7844055 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -516,6 +516,7 @@ new_d->enabled = status & 0x01; new_d->hidden = (status >> 1) & 0x01; + new_d->mandatory = (status >> 2) & 0x01; new_d->chip_instance = chip_instance; chip_instance->ref_count++; @@ -810,6 +811,7 @@ fprintf(fil, "},\n"); fprintf(fil, "\t.enabled = %d,\n", ptr->enabled); fprintf(fil, "\t.hidden = %d,\n", ptr->hidden); + fprintf(fil, "\t.mandatory = %d,\n", ptr->mandatory); fprintf(fil, "\t.on_mainboard = 1,\n"); if (ptr->subsystem_vendor > 0) fprintf(fil, "\t.subsystem_vendor = 0x%04x,\n", diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index eea2a14..60842f1 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -104,6 +104,8 @@ /* Indicates device status (enabled / hidden or not). */ int enabled; int hidden; + /* non-zero if the device should be included in all cases */ + int mandatory; /* Subsystem IDs for the device. */ int subsystem_vendor; diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index 87de6e2..14eb965 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -29,7 +29,8 @@ register {return(REGISTER);} on {yylval.number=1; return(BOOL);} off {yylval.number=0; return(BOOL);} -hidden {yylval.number=3; return(HIDDEN);} +hidden {yylval.number=3; return(STATUS);} +mandatory {yylval.number=5; return(STATUS);} pci {yylval.number=PCI; return(BUS);} ioapic {yylval.number=IOAPIC; return(BUS);} pnp {yylval.number=PNP; return(BUS);} diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index 8e1e57d..f4335c7 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -1,8 +1,8 @@ -/* A Bison parser, made by GNU Bison 3.0.5. */ +/* A Bison parser, made by GNU Bison 3.0.4. */ /* Bison implementation for Yacc-like parsers in C - Copyright (C) 1984, 1989-1990, 2000-2015, 2018 Free Software Foundation, Inc. + Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -44,7 +44,7 @@ #define YYBISON 1 /* Bison version. */ -#define YYBISON_VERSION "3.0.5" +#define YYBISON_VERSION "3.0.4" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -109,8 +109,8 @@ /* In a future release of Bison, this section will be replaced by #include "sconfig.tab.h_shipped". */ -#ifndef YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +#ifndef YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 0 @@ -128,34 +128,35 @@ DEVICE = 259, REGISTER = 260, BOOL = 261, - HIDDEN = 262, - BUS = 263, - RESOURCE = 264, - END = 265, - EQUALS = 266, - HEX = 267, - STRING = 268, - PCI = 269, - PNP = 270, - I2C = 271, - APIC = 272, - CPU_CLUSTER = 273, - CPU = 274, - DOMAIN = 275, - IRQ = 276, - DRQ = 277, - SLOT_DESC = 278, - IO = 279, - NUMBER = 280, - SUBSYSTEMID = 281, - INHERIT = 282, - IOAPIC_IRQ = 283, - IOAPIC = 284, - PCIINT = 285, - GENERIC = 286, - SPI = 287, - USB = 288, - MMIO = 289 + STATUS = 262, + MANDATORY = 263, + BUS = 264, + RESOURCE = 265, + END = 266, + EQUALS = 267, + HEX = 268, + STRING = 269, + PCI = 270, + PNP = 271, + I2C = 272, + APIC = 273, + CPU_CLUSTER = 274, + CPU = 275, + DOMAIN = 276, + IRQ = 277, + DRQ = 278, + SLOT_DESC = 279, + IO = 280, + NUMBER = 281, + SUBSYSTEMID = 282, + INHERIT = 283, + IOAPIC_IRQ = 284, + IOAPIC = 285, + PCIINT = 286, + GENERIC = 287, + SPI = 288, + USB = 289, + MMIO = 290 }; #endif @@ -184,7 +185,7 @@ int yyparse (void); -#endif /* !YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ +#endif /* !YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ /* Copy the second part of user declarations. */ @@ -430,10 +431,10 @@ /* YYFINAL -- State number of the termination state. */ #define YYFINAL 3 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 43 +#define YYLAST 40 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 35 +#define YYNTOKENS 36 /* YYNNTS -- Number of nonterminals. */ #define YYNNTS 15 /* YYNRULES -- Number of rules. */ @@ -444,7 +445,7 @@ /* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned by yylex, with out-of-bounds checking. */ #define YYUNDEFTOK 2 -#define YYMAXUTOK 289 +#define YYMAXUTOK 290 #define YYTRANSLATE(YYX) \ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) @@ -481,7 +482,8 @@ 2, 2, 2, 2, 2, 2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 + 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, + 35 }; #if YYDEBUG @@ -500,12 +502,12 @@ static const char *const yytname[] = { "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "BOOL", - "HIDDEN", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", - "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", - "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", - "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", "$accept", - "devtree", "$@1", "chipchildren", "devicechildren", "chip", "@2", - "device", "@3", "status", "resource", "registers", "subsystemid", + "STATUS", "MANDATORY", "BUS", "RESOURCE", "END", "EQUALS", "HEX", + "STRING", "PCI", "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", + "IRQ", "DRQ", "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", + "IOAPIC_IRQ", "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", + "$accept", "devtree", "$@1", "chipchildren", "devicechildren", "chip", + "@2", "device", "@3", "status", "resource", "registers", "subsystemid", "ioapic_irq", "smbios_slot_desc", YY_NULLPTR }; #endif @@ -518,7 +520,7 @@ 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, - 285, 286, 287, 288, 289 + 285, 286, 287, 288, 289, 290 }; # endif @@ -536,11 +538,11 @@ STATE-NUM. */ static const yytype_int8 yypact[] = { - -12, 11, 9, -12, 1, -12, -12, -12, 0, 5, - 3, -12, -12, -12, -12, -10, 6, 2, 8, -12, - -12, -12, -12, -12, -3, -1, -12, 13, 4, 7, - -12, -12, -12, -12, -12, -12, 16, 15, 10, -11, - 12, 17, -5, 14, -12, 18, -12, -12, -12 + -12, 6, 9, -12, -1, -12, -12, -12, 0, 5, + 1, -12, -12, -12, -12, -10, 7, 3, 8, -12, + -12, -12, -12, -12, -3, -9, -12, 11, 2, 4, + -12, -12, -12, -12, -12, -12, 15, 17, 10, -11, + 12, 18, -5, 13, -12, 19, -12, -12, -12 }; /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. @@ -558,7 +560,7 @@ /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -12, -12, -12, -12, -12, -6, -12, 19, -12, -12, + -12, -12, -12, -12, -12, -6, -12, 16, -12, -12, -12, -12, -12, -12, -12 }; @@ -574,39 +576,39 @@ number is the opposite. If YYTABLE_NINF, syntax error. */ static const yytype_uint8 yytable[] = { - 4, 9, 12, 4, 9, 10, 25, 26, 19, 20, - 11, 3, 4, 15, 6, 17, 16, 18, 30, 43, - 27, 22, 46, 28, 36, 29, 37, 40, 41, 38, - 45, 48, 39, 0, 0, 42, 0, 44, 0, 47, - 0, 0, 0, 31 + 4, 9, 12, 4, 9, 10, 3, 25, 26, 19, + 20, 11, 4, 6, 15, 16, 17, 36, 30, 18, + 43, 27, 22, 46, 28, 37, 29, 40, 38, 0, + 39, 41, 45, 48, 0, 0, 42, 0, 44, 47, + 31 }; static const yytype_int8 yycheck[] = { - 3, 4, 8, 3, 4, 5, 9, 10, 6, 7, - 10, 0, 3, 8, 13, 25, 13, 11, 24, 30, - 23, 13, 27, 26, 25, 28, 13, 11, 13, 25, - 13, 13, 25, -1, -1, 25, -1, 25, -1, 25, - -1, -1, -1, 24 + 3, 4, 8, 3, 4, 5, 0, 10, 11, 6, + 7, 11, 3, 14, 9, 14, 26, 26, 24, 12, + 31, 24, 14, 28, 27, 14, 29, 12, 26, -1, + 26, 14, 14, 14, -1, -1, 26, -1, 26, 26, + 24 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_uint8 yystos[] = { - 0, 36, 37, 0, 3, 40, 13, 41, 38, 4, - 5, 10, 40, 42, 46, 8, 13, 25, 11, 6, - 7, 44, 13, 43, 39, 9, 10, 23, 26, 28, - 40, 42, 45, 47, 48, 49, 25, 13, 25, 25, - 11, 13, 25, 30, 25, 13, 27, 25, 13 + 0, 37, 38, 0, 3, 41, 14, 42, 39, 4, + 5, 11, 41, 43, 47, 9, 14, 26, 12, 6, + 7, 45, 14, 44, 40, 10, 11, 24, 27, 29, + 41, 43, 46, 48, 49, 50, 26, 14, 26, 26, + 12, 14, 26, 31, 26, 14, 28, 26, 14 }; /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_uint8 yyr1[] = { - 0, 35, 37, 36, 38, 38, 38, 38, 39, 39, - 39, 39, 39, 39, 39, 41, 40, 43, 42, 44, - 44, 45, 46, 47, 47, 48, 49, 49, 49 + 0, 36, 38, 37, 39, 39, 39, 39, 40, 40, + 40, 40, 40, 40, 40, 42, 41, 44, 43, 45, + 45, 46, 47, 48, 48, 49, 50, 50, 50 }; /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ @@ -975,7 +977,6 @@ case N: \ yyformat = S; \ break - default: /* Avoid compiler warnings. */ YYCASE_(0, YY_("syntax error")); YYCASE_(1, YY_("syntax error, unexpected %s")); YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s")); diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index bcbd644..272f651 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -1,8 +1,8 @@ -/* A Bison parser, made by GNU Bison 3.0.5. */ +/* A Bison parser, made by GNU Bison 3.0.4. */ /* Bison interface for Yacc-like parsers in C - Copyright (C) 1984, 1989-1990, 2000-2015, 2018 Free Software Foundation, Inc. + Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -30,8 +30,8 @@ This special exception was added by the Free Software Foundation in version 2.2 of Bison. */ -#ifndef YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +#ifndef YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 0 @@ -49,34 +49,35 @@ DEVICE = 259, REGISTER = 260, BOOL = 261, - HIDDEN = 262, - BUS = 263, - RESOURCE = 264, - END = 265, - EQUALS = 266, - HEX = 267, - STRING = 268, - PCI = 269, - PNP = 270, - I2C = 271, - APIC = 272, - CPU_CLUSTER = 273, - CPU = 274, - DOMAIN = 275, - IRQ = 276, - DRQ = 277, - SLOT_DESC = 278, - IO = 279, - NUMBER = 280, - SUBSYSTEMID = 281, - INHERIT = 282, - IOAPIC_IRQ = 283, - IOAPIC = 284, - PCIINT = 285, - GENERIC = 286, - SPI = 287, - USB = 288, - MMIO = 289 + STATUS = 262, + MANDATORY = 263, + BUS = 264, + RESOURCE = 265, + END = 266, + EQUALS = 267, + HEX = 268, + STRING = 269, + PCI = 270, + PNP = 271, + I2C = 272, + APIC = 273, + CPU_CLUSTER = 274, + CPU = 275, + DOMAIN = 276, + IRQ = 277, + DRQ = 278, + SLOT_DESC = 279, + IO = 280, + NUMBER = 281, + SUBSYSTEMID = 282, + INHERIT = 283, + IOAPIC_IRQ = 284, + IOAPIC = 285, + PCIINT = 286, + GENERIC = 287, + SPI = 288, + USB = 289, + MMIO = 290 }; #endif @@ -105,4 +106,4 @@ int yyparse (void); -#endif /* !YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ +#endif /* !YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 0d894a9..d55b18b 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -31,7 +31,7 @@ int number; } -%token CHIP DEVICE REGISTER BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO +%token CHIP DEVICE REGISTER BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO %% devtree: { cur_parent = root_parent; } chip; @@ -56,7 +56,7 @@ cur_parent = $<dev>5->parent; }; -status: BOOL | HIDDEN; +status: BOOL | STATUS ; resource: RESOURCE NUMBER /* == resnum */ EQUALS NUMBER /* == resval */ { add_resource(cur_parent, $<number>1, strtol($<string>2, NULL, 0), strtol($<string>4, NULL, 0)); } ; -- To view, visit https://review.coreboot.org/c/coreboot/+/36221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e Gerrit-Change-Number: 36221 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

13 121

Change in ...coreboot[master]: intel/apollolake: Add early smbus support
by Christian Gmeiner (Code Review) 08 Feb '20

08 Feb '20

Christian Gmeiner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31461 Change subject: intel/apollolake: Add early smbus support ...................................................................... intel/apollolake: Add early smbus support Change-Id: Ic472c71998064d09c9caddc5c80c01e85a381c69 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/include/soc/smbus.h 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31461/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 19cd296..f7ddc6f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -85,6 +85,7 @@ select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PMC + select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SRAM select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index cf3e839..99a9467 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -23,6 +23,7 @@ #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> +#include <intelblocks/smbus.h> #include <intelblocks/systemagent.h> #include <intelblocks/pmclib.h> #include <intelblocks/tco.h> @@ -112,6 +113,9 @@ /* Program TCO Timer Halt */ tco_configure(); + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); + /* Use Nx and paging to prevent the frontend from writing back dirty * cache-as-ram lines to backing store that doesn't exist when the L1I * speculatively fetches a line that is sitting in the L1D. */ diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index 4b252d6..a4ff451 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -16,6 +16,9 @@ #ifndef _SOC_APOLLOLAKE_SMBUS_H_ #define _SOC_APOLLOLAKE_SMBUS_H_ +/* PCI Configuration Space (D31:F3): SMBus */ +#define SMB_RCV_SLVA 0x09 + /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) @@ -25,4 +28,7 @@ #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +/* SMBus I/O bits. */ +#define SMBUS_SLAVE_ADDR 0x24 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic472c71998064d09c9caddc5c80c01e85a381c69 Gerrit-Change-Number: 31461 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Gmeiner <christian.gmeiner(a)gmail.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: intel/smm: Chain .pre_cpu_smm_trigger
by Kyösti Mälkki (Code Review) 08 Feb '20

08 Feb '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37144 ) Change subject: intel/smm: Chain .pre_cpu_smm_trigger ...................................................................... intel/smm: Chain .pre_cpu_smm_trigger Change-Id: I2533fc478441f5b790802df9a3ec63c5a2e496af Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/smm/em64t101.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/cpu/intel/smm_reloc.h M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/cpu.c 9 files changed, 65 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/37144/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index c4c34ca..eb0c22e 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -746,15 +746,23 @@ *parallel = 1; } +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ - smm_relocate(); + smm_trigger(); /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); } +static void chain_smm_trigger(struct mp_ops *mp_ops) +{ + smm_trigger = mp_ops->per_cpu_smm_trigger; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; +} + static void post_mp_init(void) { /* Now that all APs have been relocated as well as the BSP let SMIs @@ -775,7 +783,7 @@ void mp_init_cpus(struct bus *cpu_bus) { select_mp_ops_em64t101_cpu_save(&mp_ops); - mp_ops.per_cpu_smm_trigger = per_cpu_smm_trigger; + chain_smm_trigger(&mp_ops); if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index ac9713f..f9e4827 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -300,15 +300,23 @@ *parallel = 1; } +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ - smm_relocate(); + smm_trigger(); /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); } +static void chain_smm_trigger(struct mp_ops *mp_ops) +{ + smm_trigger = mp_ops->per_cpu_smm_trigger; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; +} + static void post_mp_init(void) { /* Now that all APs have been relocated as well as the BSP let SMIs @@ -330,7 +338,7 @@ void mp_init_cpus(struct bus *cpu_bus) { select_mp_ops_em64t101(&mp_ops); - mp_ops.per_cpu_smm_trigger = per_cpu_smm_trigger; + chain_smm_trigger(&mp_ops); if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index a5e66fe..a00757d 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -526,15 +526,23 @@ *parallel = 1; } +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ - smm_relocate(); + smm_trigger(); /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); } +static void chain_smm_trigger(struct mp_ops *mp_ops) +{ + smm_trigger = mp_ops->per_cpu_smm_trigger; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; +} + static void post_mp_init(void) { /* Now that all APs have been relocated as well as the BSP let SMIs diff --git a/src/cpu/intel/smm/em64t101.c b/src/cpu/intel/smm/em64t101.c index e4dd454..d3e45bc 100644 --- a/src/cpu/intel/smm/em64t101.c +++ b/src/cpu/intel/smm/em64t101.c @@ -54,7 +54,7 @@ * the saving state to each CPU's MSRs. At least one save state size * is required for the initial SMM entry for the BSP to determine if * parallel SMM relocation is even feasible. */ -void smm_relocate(void) +static void per_cpu_smm_trigger(void) { /* * If smm_save_state_in_msrs is non-zero then parallel SMM relocation @@ -68,12 +68,6 @@ smm_initiate_relocation(); } -static void per_cpu_smm_trigger(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); -} - /* The relocation work is actually performed in SMM context, but the code * resides in the ramstage module. This occurs by trampolining from the default * SMRAM entry point to here. */ diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index eccd939..87ce02f 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -33,12 +33,14 @@ #define SMRR_SUPPORTED (1 << 11) +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger_alt_1(void) { set_vmx_and_lock(); /* Relocate the SMM handler. */ - smm_relocate(); + smm_trigger(); } static void per_cpu_smm_trigger_alt_2(void) @@ -66,7 +68,7 @@ } /* Relocate the SMM handler. */ - smm_relocate(); + smm_trigger(); } /* The relocation work is actually performed in SMM context, but the code @@ -116,6 +118,7 @@ struct cpuinfo_x86 c; select_mp_ops_em64t101(mp_ops); + smm_trigger = mp_ops->per_cpu_smm_trigger; mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger_alt_1; diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index 790df30..64dda8d 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -54,9 +54,6 @@ void fill_in_ied_params(struct smm_relocation_params *params); void write_smm_msrs(int cpu, struct smm_relocation_params *relo_params); -/* These helpers are for performing SMM relocation. */ -void smm_relocate(void); - #define D_OPEN (1 << 6) #define D_CLS (1 << 5) #define D_LCK (1 << 4) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 44b3c59..28355bd 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -138,17 +138,25 @@ *parallel = 1; } +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger(void) { const struct pattrs *pattrs = pattrs_get(); /* Relocate SMM space. */ - smm_initiate_relocation(); + smm_trigger(); /* Load microcode after SMM relocation. */ intel_microcode_load_unlocked(pattrs->microcode_patch); } +static void chain_smm_trigger(struct mp_ops *mp_ops) +{ + smm_trigger = mp_ops->per_cpu_smm_trigger; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; +} + static void post_mp_init(void) { smm_southbridge_enable_smi(); @@ -166,7 +174,7 @@ struct bus *cpu_bus = dev->link_list; select_mp_ops_em64t100(&mp_ops); - mp_ops.per_cpu_smm_trigger = per_cpu_smm_trigger; + chain_smm_trigger(&mp_ops); if (mp_init_with_smm(cpu_bus, &mp_ops)) { printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 7454f94..d803013 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -147,6 +147,8 @@ *parallel = 1; } +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger(void) { const struct pattrs *pattrs = pattrs_get(); @@ -158,12 +160,18 @@ intel_microcode_load_unlocked(pattrs->microcode_patch); /* Relocate SMM space. */ - smm_initiate_relocation(); + smm_trigger(); /* Load microcode after SMM relocation. */ intel_microcode_load_unlocked(pattrs->microcode_patch); } +static void chain_smm_trigger(struct mp_ops *mp_ops) +{ + smm_trigger = mp_ops->per_cpu_smm_trigger; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; +} + static void post_mp_init(void) { smm_southbridge_enable_smi(); @@ -184,7 +192,7 @@ __FILE__, __func__, dev_name(dev)); select_mp_ops_em64t100(&mp_ops); - mp_ops.per_cpu_smm_trigger = per_cpu_smm_trigger; + chain_smm_trigger(&mp_ops); if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index f19ee7a..6a514e9 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -635,15 +635,23 @@ *parallel = 1; } +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ - smm_relocate(); + smm_trigger(); /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); } +static void chain_smm_trigger(struct mp_ops *mp_ops) +{ + smm_trigger = mp_ops->per_cpu_smm_trigger; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; +} + static void post_mp_init(void) { /* Set Max Ratio */ @@ -669,7 +677,7 @@ struct bus *cpu_bus = dev->link_list; select_mp_ops_em64t101_cpu_save(&mp_ops); - mp_ops.per_cpu_smm_trigger = per_cpu_smm_trigger; + chain_smm_trigger(&mp_ops); if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/37144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2533fc478441f5b790802df9a3ec63c5a2e496af Gerrit-Change-Number: 37144 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 5

Change in coreboot[master]: [WIP] soc/intel: Refactor device ACPI names
by Kyösti Mälkki (Code Review) 08 Feb '20

08 Feb '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35736 ) Change subject: [WIP] soc/intel: Refactor device ACPI names ...................................................................... [WIP] soc/intel: Refactor device ACPI names Change-Id: I0f2ee991efbd0911dfce5fdf5c5d92de9b7cc652 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/fsp_broadwell_de/southcluster.c M src/soc/intel/icelake/chip.c M src/soc/intel/skylake/acpi.c 5 files changed, 21 insertions(+), 237 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/35736/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 8e516f8..e53bb0c 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -147,65 +147,10 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL; - switch (dev->path.pci.devfn) { - /* DSDT: acpi/northbridge.asl */ - case SA_DEVFN_ROOT: - return "MCHC"; - /* DSDT: acpi/lpc.asl */ - case PCH_DEVFN_LPC: - return "LPCB"; - /* DSDT: acpi/xhci.asl */ - case PCH_DEVFN_XHCI: - return "XHCI"; - /* DSDT: acpi/pch_hda.asl */ - case PCH_DEVFN_HDA: - return "HDAS"; - /* DSDT: acpi/lpss.asl */ - case PCH_DEVFN_UART0: - return "URT1"; - case PCH_DEVFN_UART1: - return "URT2"; - case PCH_DEVFN_UART2: - return "URT3"; - case PCH_DEVFN_UART3: - return "URT4"; - case PCH_DEVFN_SPI0: - return "SPI1"; - case PCH_DEVFN_SPI1: - return "SPI2"; - case PCH_DEVFN_SPI2: - return "SPI3"; - case PCH_DEVFN_PWM: - return "PWM"; - case PCH_DEVFN_I2C0: - return "I2C0"; - case PCH_DEVFN_I2C1: - return "I2C1"; - case PCH_DEVFN_I2C2: - return "I2C2"; - case PCH_DEVFN_I2C3: - return "I2C3"; - case PCH_DEVFN_I2C4: - return "I2C4"; - case PCH_DEVFN_I2C5: - return "I2C5"; - case PCH_DEVFN_I2C6: - return "I2C6"; - case PCH_DEVFN_I2C7: - return "I2C7"; - /* Storage */ - case PCH_DEVFN_SDCARD: - return "SDCD"; - case PCH_DEVFN_EMMC: - return "EMMC"; - case PCH_DEVFN_SDIO: - return "SDIO"; - /* PCIe */ - case PCH_DEVFN_PCIE1: - return "RP03"; - case PCH_DEVFN_PCIE5: - return "RP01"; - } +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif return NULL; } diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0ce2f1a..1754964 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -74,66 +74,10 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL; - switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IGD: return "GFX0"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_CSE: return "CSE1"; - case PCH_DEVFN_CSE_2: return "CSE2"; - case PCH_DEVFN_CSE_IDER: return "CSED"; - case PCH_DEVFN_CSE_KT: return "CSKT"; - case PCH_DEVFN_CSE_3: return "CSE3"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PCIE13: return "RP13"; - case PCH_DEVFN_PCIE14: return "RP14"; - case PCH_DEVFN_PCIE15: return "RP15"; - case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_PCIE17: return "RP17"; - case PCH_DEVFN_PCIE18: return "RP18"; - case PCH_DEVFN_PCIE19: return "RP19"; - case PCH_DEVFN_PCIE20: return "RP20"; - case PCH_DEVFN_PCIE21: return "RP21"; - case PCH_DEVFN_PCIE22: return "RP22"; - case PCH_DEVFN_PCIE23: return "RP23"; - case PCH_DEVFN_PCIE24: return "RP24"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_LPC: return "LPCB"; - case PCH_DEVFN_P2SB: return "P2SB"; - case PCH_DEVFN_PMC: return "PMC_"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_GBE: return "IGBE"; - case PCH_DEVFN_TRACEHUB:return "THUB"; - } +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif return NULL; } diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index 31dcc25..2ad5f52 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -280,10 +280,11 @@ #if CONFIG(HAVE_ACPI_TABLES) static const char *lpc_acpi_name(const struct device *dev) { - if (dev->path.pci.devfn == PCH_DEVFN_LPC) - return "LPC0"; - else - return NULL; +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif + return NULL; } #endif diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 2bb908c..956f35f 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -37,67 +37,10 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL; - switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IGD: return "GFX0"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_CSE: return "CSE1"; - case PCH_DEVFN_CSE_2: return "CSE2"; - case PCH_DEVFN_CSE_IDER: return "CSED"; - case PCH_DEVFN_CSE_KT: return "CSKT"; - case PCH_DEVFN_CSE_3: return "CSE3"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PCIE13: return "RP13"; - case PCH_DEVFN_PCIE14: return "RP14"; - case PCH_DEVFN_PCIE15: return "RP15"; - case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_PCIE17: return "RP17"; - case PCH_DEVFN_PCIE18: return "RP18"; - case PCH_DEVFN_PCIE19: return "RP19"; - case PCH_DEVFN_PCIE20: return "RP20"; - case PCH_DEVFN_PCIE21: return "RP21"; - case PCH_DEVFN_PCIE22: return "RP22"; - case PCH_DEVFN_PCIE23: return "RP23"; - case PCH_DEVFN_PCIE24: return "RP24"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDCARD: return "SDXC"; - /* Keeping ACPI device name coherent with ec.asl */ - case PCH_DEVFN_ESPI: return "LPCB"; - case PCH_DEVFN_P2SB: return "P2SB"; - case PCH_DEVFN_PMC: return "PMC_"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_GBE: return "IGBE"; - case PCH_DEVFN_TRACEHUB:return "THUB"; - } +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif return NULL; } diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 43f9c39..45756b3 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -760,59 +760,10 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL; - switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IGD: return "GFX0"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; - case PCH_DEVFN_CIO: return "ICIO"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_CSE: return "CSE1"; - case PCH_DEVFN_CSE_2: return "CSE2"; - case PCH_DEVFN_CSE_IDER: return "CSED"; - case PCH_DEVFN_CSE_KT: return "CSKT"; - case PCH_DEVFN_CSE_3: return "CSE3"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PCIE13: return "RP13"; - case PCH_DEVFN_PCIE14: return "RP14"; - case PCH_DEVFN_PCIE15: return "RP15"; - case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDIO: return "SDIO"; - case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_LPC: return "LPCB"; - case PCH_DEVFN_P2SB: return "P2SB"; - case PCH_DEVFN_PMC: return "PMC_"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_GBE: return "IGBE"; - case PCH_DEVFN_TRACEHUB:return "THUB"; - } +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f2ee991efbd0911dfce5fdf5c5d92de9b7cc652 Gerrit-Change-Number: 35736 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: trogdor: support mbn_version 6 with python build scripts
by mturney mturney (Code Review) 07 Feb '20

07 Feb '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35506 ) Change subject: trogdor: support mbn_version 6 with python build scripts ...................................................................... trogdor: support mbn_version 6 with python build scripts Developer/Reviewer, be aware of this patch from Mistral: https://review.coreboot.org/c/coreboot/+/33425/18 Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M util/qualcomm/createxbl.py M util/qualcomm/mbn_tools.py 2 files changed, 90 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35506/1 diff --git a/util/qualcomm/createxbl.py b/util/qualcomm/createxbl.py index 4a21854..769e9f1e 100755 --- a/util/qualcomm/createxbl.py +++ b/util/qualcomm/createxbl.py @@ -44,6 +44,7 @@ # # when who what, where, why # -------- --- ------------------------------------------------------ +# 05/21/19 rissha Added --mbn_version to add MBN header accordingly # 03/26/18 tv Added -e to enable extended MBNV5 support # 09/04/15 et Added -x and -d to embed xbl_sec ELF # 02/11/15 ck Fixed missing elf type check in ZI OOB feature @@ -119,6 +120,10 @@ help="Removes ZI segments that have addresses greater" + \ " than 32 bits when converting from a 64 to 32 bit ELF") + parser.add_option("--mbn_version", + action="store", type="int", dest="mbn_version", + help="Add mbn header in elf image. '3', '5' or '6'") + (options, args) = parser.parse_args() if not options.elf_inp_file1: @@ -206,11 +211,16 @@ else: zi_oob_enabled = True + header_version = 3 + if options.elf_inp_xbl_sec: is_ext_mbn_v5 = True + header_version = 5 else: is_ext_mbn_v5 = False + if options.mbn_version: + header_version = options.mbn_version mbn_type = 'elf' header_format = 'reg' @@ -259,7 +269,7 @@ source_elf, target_hash, elf_out_file_name = target_phdr_elf, - secure_type = image_header_secflag) + secure_type = image_header_secflag, header_version = header_version ) if rv: raise RuntimeError, "Failed to run pboot_gen_elf" @@ -270,7 +280,8 @@ target_hash_hd, image_header_secflag, is_ext_mbn_v5, - elf_file_name = source_elf) + elf_file_name = source_elf, + header_version = header_version) if rv: raise RuntimeError, "Failed to create image header for hash segment" diff --git a/util/qualcomm/mbn_tools.py b/util/qualcomm/mbn_tools.py index 12dc210..079e02e 100755 --- a/util/qualcomm/mbn_tools.py +++ b/util/qualcomm/mbn_tools.py @@ -41,6 +41,7 @@ # # when who what, where, why # -------- --- --------------------------------------------------------- +# 05/21/18 rissha Added support for extended MBNV6 and Add support for hashing elf segments with SHA384 # 03/22/18 thiru Added support for extended MBNV5. # 06/06/13 yliong CR 497042: Signed and encrypted image is corrupted. MRC features. # 03/18/13 dhaval Add support for hashing elf segments with SHA256 and @@ -64,23 +65,24 @@ #---------------------------------------------------------------------------- # GLOBAL VARIABLES BEGIN #---------------------------------------------------------------------------- -PAD_BYTE_1 = 255 # Padding byte 1s -PAD_BYTE_0 = 0 # Padding byte 0s -SHA256_SIGNATURE_SIZE = 256 # Support SHA256 -MAX_NUM_ROOT_CERTS = 4 # Maximum number of OEM root certificates -MI_BOOT_IMG_HDR_SIZE = 40 # sizeof(mi_boot_image_header_type) -MI_BOOT_SBL_HDR_SIZE = 80 # sizeof(sbl_header) -BOOT_HEADER_LENGTH = 20 # Boot Header Number of Elements -SBL_HEADER_LENGTH = 20 # SBL Header Number of Elements -FLASH_PARTI_VERSION = 3 # Flash Partition Version Number -MAX_PHDR_COUNT = 100 # Maximum allowable program headers -CERT_CHAIN_ONEROOT_MAXSIZE = 6*1024 # Default Cert Chain Max Size for one root -VIRTUAL_BLOCK_SIZE = 131072 # Virtual block size for MCs insertion in SBL1 if ENABLE_VIRTUAL_BLK ON -MAGIC_COOKIE_LENGTH = 12 # Length of magic Cookie inserted per VIRTUAL_BLOCK_SIZE -MIN_IMAGE_SIZE_WITH_PAD = 256*1024 # Minimum image size for sbl1 Nand based OTA feature +PAD_BYTE_1 = 255 # Padding byte 1s +PAD_BYTE_0 = 0 # Padding byte 0s +SHA256_SIGNATURE_SIZE = 256 # Support SHA256 +MAX_NUM_ROOT_CERTS = 4 # Maximum number of OEM root certificates +MBN_HEADER_VERSION_3 = 3 # Mbn header_version 3 +MBN_HEADER_VERSION_5 = 5 # Mbn header_version 5 +MBN_HEADER_VERSION_6 = 6 # Mbn header_version 6 +MI_BOOT_SBL_HDR_SIZE = 80 # sizeof(sbl_header) +BOOT_HEADER_LENGTH = 20 # Boot Header Number of Elements +SBL_HEADER_LENGTH = 20 # SBL Header Number of Elements +MAX_PHDR_COUNT = 100 # Maximum allowable program headers +CERT_CHAIN_ONEROOT_MAXSIZE = 6*1024 # Default Cert Chain Max Size for one root +VIRTUAL_BLOCK_SIZE = 131072 # Virtual block size for MCs insertion in SBL1 if ENABLE_VIRTUAL_BLK ON +MAGIC_COOKIE_LENGTH = 12 # Length of magic Cookie inserted per VIRTUAL_BLOCK_SIZE +MIN_IMAGE_SIZE_WITH_PAD = 256*1024 # Minimum image size for sbl1 Nand based OTA feature -SBL_AARCH64 = 0xF # Indicate that SBL is a Aarch64 image -SBL_AARCH32 = 0x0 # Indicate that SBL is a Aarch32 image +SBL_AARCH64 = 0xF # Indicate that SBL is a Aarch64 image +SBL_AARCH32 = 0x0 # Indicate that SBL is a Aarch32 image # Magic numbers filled in for boot headers FLASH_CODE_WORD = 0x844BDCD1 @@ -528,7 +530,7 @@ class Boot_Hdr: def __init__(self, init_val): self.image_id = ImageType.NONE_IMG - self.flash_parti_ver = FLASH_PARTI_VERSION + self.flash_parti_ver = MBN_HEADER_VERSION_3 self.image_src = init_val self.image_dest_ptr = init_val self.image_size = init_val @@ -573,6 +575,10 @@ self.reserved_2, self.reserved_3 ] + if self.flash_parti_ver == MBN_HEADER_VERSION_6: + values.insert(10, self.metadata_size_qti) + values.insert(11, self.metadata_size) + if self.image_dest_ptr >= 0x100000000: values[3] = 0xFFFFFFFF @@ -584,8 +590,12 @@ # Write 10 entries(40B) or 20 entries(80B) of boot header if write_full_hdr is False: - s = struct.Struct('I'* 10) - values = values[:10] + if self.flash_parti_ver == MBN_HEADER_VERSION_6: + s = struct.Struct('I'* 12) + values = values[:12] + else: + s = struct.Struct('I'* 10) + values = values[:10] else: s = struct.Struct('I' * self.getLength()) @@ -912,7 +922,8 @@ write_full_hdr = False, in_code_size = None, cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE, - num_of_pages = None): + num_of_pages = None, + header_version = None): # Preliminary checks if (requires_preamble is True) and (preamble_file_name is None): @@ -945,9 +956,12 @@ cert_chain_size = 0 image_size = code_size + if header_version: + assert header_version in [MBN_HEADER_VERSION_3, MBN_HEADER_VERSION_5, MBN_HEADER_VERSION_6], 'Not a valid MBN header version' + # For ELF or hashed images, image destination will be determined from an ELF input file if gen_dict['IMAGE_KEY_MBN_TYPE'] == 'elf': - image_dest = get_hash_address(elf_file_name) + MI_BOOT_IMG_HDR_SIZE + image_dest = get_hash_address(elf_file_name) + (header_size(header_version)) elif gen_dict['IMAGE_KEY_MBN_TYPE'] == 'bin': image_dest = gen_dict['IMAGE_KEY_IMAGE_DEST'] image_source = gen_dict['IMAGE_KEY_IMAGE_SOURCE'] @@ -993,10 +1007,17 @@ boot_header.cert_chain_size = cert_chain_size if is_ext_mbn_v5 == True: - # If platform image integrity check is enabled - boot_header.flash_parti_ver = 5 # version - boot_header.image_src = 0 # sig_size_qc - boot_header.image_dest_ptr = 0 # cert_chain_size_qc + # If platform image integrity check is enabled + boot_header.flash_parti_ver = MBN_HEADER_VERSION_5 # version + boot_header.image_src = 0 # sig_size_qc + boot_header.image_dest_ptr = 0 # cert_chain_size_qc + + if header_version == MBN_HEADER_VERSION_6: + boot_header.flash_parti_ver = MBN_HEADER_VERSION_6 # version + boot_header.image_src = 0 # sig_size_qc + boot_header.image_dest_ptr = 0 # cert_chain_size_qc + boot_header.metadata_size_qti = 0 # qti_metadata size + boot_header.metadata_size = 0 # oem_metadata size # If preamble is required, output the preamble file and update the boot_header if requires_preamble is True: @@ -1021,9 +1042,20 @@ last_phys_addr = None, append_xml_hdr = False, is_sha256_algo = True, - cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE): + cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE, + header_version = None): + sha_algo = 'SHA1' + if is_sha256_algo: + sha_algo = 'SHA256' + + if header_version == MBN_HEADER_VERSION_6: + sha_algo = 'SHA384' global MI_PROG_BOOT_DIGEST_SIZE - if (is_sha256_algo is True): + image_header_size = header_size(header_version) + + if (sha_algo == 'SHA384'): + MI_PROG_BOOT_DIGEST_SIZE = 48 + elif sha_algo == 'SHA256': MI_PROG_BOOT_DIGEST_SIZE = 32 else: MI_PROG_BOOT_DIGEST_SIZE = 20 @@ -1110,7 +1142,7 @@ fbuf = elf_in_fp.read(hash_size) if MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True: - hash = generate_hash(fbuf, is_sha256_algo) + hash = generate_hash(fbuf, sha_algo) else: hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE @@ -1129,7 +1161,7 @@ file_buff = elf_in_fp.read(data_len) if (MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True) and (data_len > 0): - hash = generate_hash(file_buff, is_sha256_algo) + hash = generate_hash(file_buff, sha_algo) else: hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE @@ -1151,7 +1183,7 @@ # Initialize the hash table program header [hash_Phdr, pad_hash_segment, hash_tbl_end_addr, hash_tbl_offset] = \ - initialize_hash_phdr(elf_in_file_name, hashtable_size, MI_BOOT_IMG_HDR_SIZE, ELF_BLOCK_ALIGN, is_elf64) + initialize_hash_phdr(elf_in_file_name, hashtable_size, image_header_size, ELF_BLOCK_ALIGN, is_elf64) # Check if hash segment max size parameter was passed if (hash_seg_max_size is not None): @@ -1252,7 +1284,7 @@ # Read the program header and compute hash proghdr_buff = elf_out_fp.read(elf_header.e_phnum * phdr_size) - hash = generate_hash(elfhdr_buff + proghdr_buff, is_sha256_algo) + hash = generate_hash(elfhdr_buff + proghdr_buff, sha_algo) # Write hash to file as first hash table entry hash_out_fp.seek(0) @@ -1592,7 +1624,7 @@ page = page + elf_in_fp.read(bytes_in_page - len(page)) if (len(page) < DP_PAGE_SIZE): page = page + (struct.pack('b', 0) * (DP_PAGE_SIZE - len(page))) - hashes = hashes + [generate_hash(page, True)] + hashes = hashes + [generate_hash(page, 'SHA256')] bytes_left -= bytes_in_page # And write them to the hash segment @@ -2101,9 +2133,20 @@ #---------------------------------------------------------------------------- # sha1/sha256 hash routine wrapper #---------------------------------------------------------------------------- -def generate_hash(in_buf, is_sha256_algo): +def header_size(header_version): + if header_version == MBN_HEADER_VERSION_6: + return 48 + else: + return 40 + +#---------------------------------------------------------------------------- +# sha1/sha256 hash routine wrapper +#---------------------------------------------------------------------------- +def generate_hash(in_buf, sha_algo): # Initialize a SHA1 object from the Python hash library - if (is_sha256_algo is True): + if sha_algo == 'SHA384': + m = hashlib.sha384() + elif sha_algo == 'SHA256': m = hashlib.sha256() else: m = hashlib.sha1() -- To view, visit https://review.coreboot.org/c/coreboot/+/35506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279 Gerrit-Change-Number: 35506 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: mb/pcengines/apu2: use older AGESA with different headers
by Piotr Kleinschmidt (Code Review) 06 Feb '20

06 Feb '20

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35906 ) Change subject: mb/pcengines/apu2: use older AGESA with different headers ...................................................................... mb/pcengines/apu2: use older AGESA with different headers PC Engines apu2 platforms use AGESA 1.0.0.4 which uses different AGESA.h header than newer AGESA versions. Change-Id: I3d85ee14e35dae8079e8d552b6530a3867f65876 Signed-off-by: Piotr Kleinschmidt <piotr.kleins(a)gmail.com> --- M src/mainboard/pcengines/apu2/Kconfig M src/vendorcode/amd/pi/00730F01/AGESA.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35906/1 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 6c3958b..5a61ed1 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -114,4 +114,8 @@ int default 128 +config AGESA_USE_OLD_HEADER + bool + default y + endif # BOARD_PCENGINES_APU2 diff --git a/src/vendorcode/amd/pi/00730F01/AGESA.h b/src/vendorcode/amd/pi/00730F01/AGESA.h index c25b631..6053f3c 100644 --- a/src/vendorcode/amd/pi/00730F01/AGESA.h +++ b/src/vendorcode/amd/pi/00730F01/AGESA.h @@ -775,6 +775,7 @@ DP_VS_0_4V_9_5DB = 0x18 ///< 0x18 } DP_FIXED_VOLT_SWING_TYPE; +#if CONFIG(AGESA_USE_OLD_HEADER) /// Alternative DRAM MAC typedef enum { MAC_UNTESTEDMAC, ///< Assign 0 to Untested MAC @@ -785,6 +786,7 @@ MAC_300k, ///< Assign 5 to 300k MAC_200k, ///< Assign 6 to 200k } DRAM_MAXIMUM_ACTIVATE_COUNT; +#endif // Macro for statically initializing various structures #define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane} @@ -1547,7 +1549,9 @@ ///< 667 (MHz) ///< 800 (MHz) ///< and so on... +#if CONFIG(AGESA_USE_OLD_HEADER) OUT UINT8 Mac; ///< Maximum Activate Count +#endif OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks) OUT UINT8 Trcd; ///< DCT Trcd (busclocks) OUT UINT8 Trp; ///< DCT Trp (busclocks) @@ -1803,6 +1807,7 @@ ///< ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN} +#if CONFIG(AGESA_USE_OLD_HEADER) // Dram Mac Default IN UINT8 DramMacDefault; ///< Default Maximum Activate Count @@ -1818,6 +1823,7 @@ ///< @BldCfgItem{BLDCFG_MEMORY_EXTENDED_TEMPERATURE_RANGE} // Extended temperature range +#endif // Online Spare IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0. @@ -2721,8 +2727,10 @@ IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving. IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving. IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down. +#if CONFIG(AGESA_USE_OLD_HEADER) IN UINT8 CfgMemoryMacDefault; ///< Memory DRAM MAC Default IN BOOLEAN CfgMemoryExtendedTemperatureRange; ///< Memory Extended Temperature Range +#endif IN UINT32 CfgPowerDownMode; ///< Power Down Mode. IN BOOLEAN CfgOnlineSpare; ///< Online Spare. IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable. -- To view, visit https://review.coreboot.org/c/coreboot/+/35906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d85ee14e35dae8079e8d552b6530a3867f65876 Gerrit-Change-Number: 35906 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

9 32

Change in coreboot[master]: trogdor: Add T32 scripts for full boot chain
by mturney mturney (Code Review) 05 Feb '20

05 Feb '20

Hello ashk(a)codeaurora.org, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35505 to review the following change. Change subject: trogdor: Add T32 scripts for full boot chain ...................................................................... trogdor: Add T32 scripts for full boot chain Change-Id: I4ec1d4f722523f240fa293dd79235ab4e32e4489 Signed-off-by: ashk <ashk(a)codeaurora.org> --- M util/qualcomm/scripts/cmm/debug_cb_common.cmm A util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm A util/qualcomm/scripts/cmm/pbl_to_depthcharge.cmm 3 files changed, 229 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/35505/1 diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm index 5959ee1..cc3dd38 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm @@ -163,22 +163,28 @@ enter ) + +;;;; START OF COMMENTED OUT CODE TO SKIP QCLIB DEBUG + ; go &QCLEntryAddr ; wait !run() -; + ; if &QCLStage ; ( -; &imgpath="3rdparty\blobs\soc\qualcomm\sdm845\QcLib.elf" + ; if (&RAMLoad) -; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /noclear -; else -; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /nocode /noclear -; +; d.load \\snowcone\builds792\PROD\BOOT.XF.3.1-00315-SC7180LCB-1\boot_images\Build\Rennell_qclib\DEBUG_CLANG60LINUX\AARCH64\QcomPkg\QCLib\QcLibCommon\DEBUG\QcLib.dll +; else +; d.load \\snowcone\builds792\PROD\BOOT.XF.3.1-00315-SC7180LCB-1\boot_images\Build\Rennell_qclib\DEBUG_CLANG60LINUX\AARCH64\QcomPkg\QCLib\QcLibCommon\DEBUG\QcLib.dll + + ; print %String "Now the control is in QCLStage, press enter after debugging to go to next stage" ; print %String "Press enter to go to next stage" ; enter ; ) +;;;; END OF QCLIB COMMENTED OUT CODE + go &RAMEntryAddr wait !run() @@ -193,26 +199,6 @@ print %String "Press enter to go to next stage" enter ) - -; BL31 disabled for now -; Next block of code commented out -; go &BL31EntryAddr -; wait !run() -; -; if &BL31Stage -; ( -; &imgpath="build\bl31.elf" -; if (&RAMLoad) -; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath -; else -; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /nocode -; y.spath.srd 3rdparty/arm-trusted-firmware -; print %String "Now the control is in BL31, press enter after debugging to go to next stage" -; print %String "Press enter to go to next stage" -; enter -; ) -; End of commented out code block: bl31 - go &DCEntryAddr wait !run() @@ -220,36 +206,17 @@ ( &imgpath="payloads\external\depthcharge\depthcharge\build\depthcharge.elf" symbol.sourcepath.setbasedir &srcpath\payloads + y.spath.srd payloads\external\depthcharge\depthcharge\src if (&RAMLoad) d.load.elf &imgpath /strippart "payloads" /sourcepath &srcpath else d.load.elf &imgpath /strippart "payloads" /sourcepath &srcpath /nocode - b.d /all - b.set main - b.set halt - b.set &KernelEntryAddr ; kernel entry point - y.spath.srd + payloads/external/depthcharge/depthcharge - y.spath.srd + 3rdparty\vboot_reference - d.dump &RamConsoleAddr /spotlight - &CBTablePtr=Register(X0) - Data.SAVE.Binary CBTablePtr.bin &CBTablePtr++0x400 - print %String "Now the control is in Depthcharge, press enter after debugging to run free" - ;print %String "Use this command to load kernel symbols: d.load.elf vmlinux /nocode /strippart kernel" - print %String "Press enter when done debugging Depthcharge" - enter + print %String "Now the control is in depthcharge, end of script" + d.l + b.s main + ;Execute this command in T32 if you start debugging vboot code, e.g. vboot_select_and_load_kernel() + ;y.spath.srd 3rdparty\vboot\firmware ) -; go &KernelEntryAddr -; wait !run() -; -; if &KernelSyms -; ( -; print %String "Kernel Symbols are being loaded, this requires two files in coreboot root tree:" -; print %String "vmlinux needs to be copied from ChromiumOS build tree" -; print %String "msm-4.4 needs to be symbolic link to kernel source tree" -; d.load.elf vmlinux /strippart "msm-4.4" /nocode -; y.spath.srd msm-4.4 -; print %String "This script now concludes at kernel entry point" -; ) enddo diff --git a/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm b/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm new file mode 100644 index 0000000..276bf45 --- /dev/null +++ b/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm @@ -0,0 +1,158 @@ +;============================================================================ +;## +;## This file is part of the coreboot project. +;## +;## Copyright (C) 2019, The Linux Foundation. All rights reserved. +;## +;## This program is free software; you can redistribute it and/or modify +;## it under the terms of the GNU General Public License version 2 and +;## only version 2 as published by the Free Software Foundation. +;## +;## This program is distributed in the hope that it will be useful, +;## but WITHOUT ANY WARRANTY; without even the implied warranty of +;## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;## GNU General Public License for more details. +;## +;============================================================================ +; Name: +; debug_cb_trogdor.cmm +; +; Description: +; Debug coreboot trogdor front-end +;============================================================================ + +;============================================================================ +; CMM script variables +;============================================================================ + +LOCAL &TargetPkg + +GLOBAL &BBEntryAddr // Bootblock Entry +GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec +GLOBAL &VEREntryAddr // Verstage Entry +GLOBAL &ROMEntryAddr // Romstage Entry +GLOBAL &QCLEntryAddr // QCLstage Entry +GLOBAL &RAMEntryAddr // Ramstage Entry +GLOBAL &BL31EntryAddr // BL31 Entry +GLOBAL &DCEntryAddr // Depthcharge Entry +GLOBAL &KernelEntryAddr // Kernel Entry + +GLOBAL &PreRamConsoleAddr +GLOBAL &RamConsoleAddr +GLOBAL &PreRamCbfsCache +GLOBAL &VBoot2Work +GLOBAL &Stack +GLOBAL &Ttb +GLOBAL &Timestamp +GLOBAL &CbmemTop +GLOBAL &PostRamCbfsCache + +GLOBAL &CBTablePtr +GLOBAL &debug +;============================================================================ + +;--------------------------------------------------- +; Entry point +;--------------------------------------------------- +ENTRY &ImageName + + // Later these can be parameterized + &TargetPkg="trogdorPkg" + + // These settings come from .../src/soc/qualcomm/sc7180/include/soc/memlayout.ld + &BBEntryAddr=0x14815000 + &VEREntryAddr=0x14680000 + &ROMEntryAddr=0x14680000 + &QCLEntryAddr=0x14881950 + &RAMEntryAddr=0x9F860000 + &BL31EntryAddr=0x06820000 + &DCEntryAddr=0xF1000000 + &KernelEntryAddr=0xD0000000 + + &PreRamConsoleAddr=0x14830800 + &VBoot2Work=0x1482E000 + &Stack=0x14847000 + &Ttb=0x14839000 + &Timestamp=0x14838800 + &PreRamCbfsCache=0x1481F000 + &CbmemTop=0x280000000 + &PostRamCbfsCache=0x9F800000 + // End of memlayout.ld settings + + // Common commands irrespective of &Mode + PATH + &CwDir=os.pwd() + PATH + &CwDir + + // position at top of coreboot tree + // find depth count for source loading + cd ..\..\..\.. + &srcpath=os.pwd() + + +;--------------------------------------------------- +; Setup area and log +;--------------------------------------------------- + area.clear + area.reset + area.create CB_Logs 1000. 8192. + area.select CB_Logs + + area.view CB_Logs + + PRINT %String "Source Path: &srcpath" + + symbol.sourcepath.setbasedir &srcpath\src + + // Make parsing simple, upper-case parameters + &ImageName=STRING.UPR("&ImageName") + IF (STR.CP("&ImageName","DEBUG,*")) + ( + &debug="DEBUG" + ) + ELSE + ( + &debug="" + ) + &ImageName=STR.CUT("&ImageName",6) + IF "&debug"=="" + ( + PRINT "SPI_RAM LOAD" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,BB" //for RAM load Bootblock only and jump till DC + ) + PRINT "&ImageName" + ) + ELSE + ( + if (STR.CP("&debug","DEBUG")) + ( + PRINT "DEBUG" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,ALL" //for RAM loading all the images + ) + PRINT "&ImageName" + ) + ) + + sys.d + sys.up + b.d + y.reset + D.S EZAXI:0xC260208 %LE %Long 0x80000000 + + b.s 0x148e7000 /o + go + WAIT !STATE.RUN() + + b.s 0x14815000 /o + go + WAIT !STATE.RUN() + + DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName + + enddo diff --git a/util/qualcomm/scripts/cmm/pbl_to_depthcharge.cmm b/util/qualcomm/scripts/cmm/pbl_to_depthcharge.cmm new file mode 100644 index 0000000..9205d67 --- /dev/null +++ b/util/qualcomm/scripts/cmm/pbl_to_depthcharge.cmm @@ -0,0 +1,53 @@ +sys.d +sys.up +b.d +y.reset + +d.load.elf \\ashk-linux\workspace\ashk\pbl_script\FBC_validation\APPS_PBL.elf + +b.s sec_ctrl_drv_ioctl\273+0xC /P /CMD "r.s x6 0x12345678" /resume +b.s pbl_recoverable_error_handler /o +b.s pbl_non_recoverable_error_handler /o + +snoop.PC on + +b.s 0x148e7000 /o +go +WAIT !STATE.RUN() + +b.s 0x14815000 /o +go +WAIT !STATE.RUN() + +b.d +b.s 0x14680000 /o +go +WAIT !STATE.RUN() + +b.d +b.s 0x14680000 /o +go +WAIT !STATE.RUN() + +b.d +b.s 0x14881950 /o +go +WAIT !STATE.RUN() + +d.load \\ashk-linux\workspace\ashk\test_qclib_8_7\boot.xf.3.1.test_qclib_8_7\boot_images\Build\Rennell_qclib\DEBUG_CLANG60LINUX\AARCH64\QcomPkg\QCLib\QcLibCommon\DEBUG\QcLib.dll +do \\ashk-linux\workspace\ashk\test_qclib_8_7\boot.xf.3.1.test_qclib_8_7\boot_images\QcomPkg\Tools\qclib\qclib_rennell_only_stub_coreboot.cmm + +b.d +b.s 0x9f860000 /o +go +WAIT !STATE.RUN() + +b.d +b.s 0x80c00000 /o +go +WAIT !STATE.RUN() + +b.d +b.s 0xF1000000 /o +go +WAIT !STATE.RUN() -- To view, visit https://review.coreboot.org/c/coreboot/+/35505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ec1d4f722523f240fa293dd79235ab4e32e4489 Gerrit-Change-Number: 35505 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: Make pci and endian handling -Wconversion safe
by Patrick Georgi (Code Review) 05 Feb '20

05 Feb '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37202 ) Change subject: libpayload: Make pci and endian handling -Wconversion safe ...................................................................... libpayload: Make pci and endian handling -Wconversion safe Change-Id: Ibd1b179d647f105579bd74b071344668ca0a41ef Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M payloads/libpayload/include/endian.h M payloads/libpayload/include/pci.h M payloads/libpayload/libpci/libpci.c 3 files changed, 32 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/37202/1 diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index b387e66..b6b5322 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -36,12 +36,12 @@ static inline uint16_t swap_bytes16(uint16_t in) { - return ((in & 0xFF) << 8) | ((in & 0xFF00) >> 8); + return (uint16_t)((in & 0xFF) << 8) | ((in & 0xFF00) >> 8); } static inline uint32_t swap_bytes32(uint32_t in) { - return ((in & 0xFF) << 24) | ((in & 0xFF00) << 8) | + return (uint16_t)((in & 0xFF) << 24) | ((in & 0xFF00) << 8) | ((in & 0xFF0000) >> 8) | ((in & 0xFF000000) >> 24); } @@ -103,28 +103,30 @@ { uint8_t const *p = (uint8_t const *)pp; - return ((p[0] << 8) | p[1]); + return (uint16_t)((p[0] << 8) | p[1]); } static inline uint32_t be32dec(const void *pp) { uint8_t const *p = (uint8_t const *)pp; - return (((unsigned)p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]); + return (((uint32_t)p[0] << 24) | (uint32_t)(p[1] << 16) | + (uint32_t)(p[2] << 8) | p[3]); } static inline uint16_t le16dec(const void *pp) { uint8_t const *p = (uint8_t const *)pp; - return ((p[1] << 8) | p[0]); + return (uint16_t)((p[1] << 8) | p[0]); } static inline uint32_t le32dec(const void *pp) { uint8_t const *p = (uint8_t const *)pp; - return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]); + return ((uint32_t)(p[3] << 24) | (uint32_t)(p[2] << 16) | + (uint32_t)(p[1] << 8) | p[0]); } static inline void bebitenc(void *pp, uint32_t u, uint8_t b) diff --git a/payloads/libpayload/include/pci.h b/payloads/libpayload/include/pci.h index ff07d5c..a1bac4a 100644 --- a/payloads/libpayload/include/pci.h +++ b/payloads/libpayload/include/pci.h @@ -91,11 +91,11 @@ #define HEADER_TYPE_CARDBUS 2 #define HEADER_TYPE_MULTIFUNCTION 0x80 -#define PCI_ADDR(_bus, _dev, _fn, _reg) \ -(0x80000000 | (_bus << 16) | (_dev << 11) | (_fn << 8) | (_reg & ~3)) +#define PCI_DEV(_bus, _dev, _fn) (0x80000000 | \ +(uint32_t)(_bus << 16) | (uint32_t)(_dev << 11) | (uint32_t)(_fn << 8)) -#define PCI_DEV(_bus, _dev, _fn) \ -(0x80000000 | (_bus << 16) | (_dev << 11) | (_fn << 8)) +#define PCI_ADDR(_bus, _dev, _fn, _reg) \ +(PCI_DEV(_bus, _dev, _fn) | (uint8_t)(_reg & ~3)) #define PCI_BUS(_d) ((_d >> 16) & 0xff) #define PCI_SLOT(_d) ((_d >> 11) & 0x1f) diff --git a/payloads/libpayload/libpci/libpci.c b/payloads/libpayload/libpci/libpci.c index 82203a1..fd0332e 100644 --- a/payloads/libpayload/libpci/libpci.c +++ b/payloads/libpayload/libpci/libpci.c @@ -40,34 +40,34 @@ /* libpci interface */ u8 pci_read_byte(struct pci_dev *dev, int pos) { - return pci_read_config8(libpci_to_lb(dev), pos); + return pci_read_config8(libpci_to_lb(dev), (uint16_t)pos); } u16 pci_read_word(struct pci_dev *dev, int pos) { - return pci_read_config16(libpci_to_lb(dev), pos); + return pci_read_config16(libpci_to_lb(dev), (uint16_t)pos); } u32 pci_read_long(struct pci_dev *dev, int pos) { - return pci_read_config32(libpci_to_lb(dev), pos); + return pci_read_config32(libpci_to_lb(dev), (uint16_t)pos); } int pci_write_byte(struct pci_dev *dev, int pos, u8 data) { - pci_write_config8(libpci_to_lb(dev), pos, data); + pci_write_config8(libpci_to_lb(dev), (uint16_t)pos, data); return 1; /* success */ } int pci_write_word(struct pci_dev *dev, int pos, u16 data) { - pci_write_config16(libpci_to_lb(dev), pos, data); + pci_write_config16(libpci_to_lb(dev), (uint16_t)pos, data); return 1; /* success */ } int pci_write_long(struct pci_dev *dev, int pos, u32 data) { - pci_write_config32(libpci_to_lb(dev), pos, data); + pci_write_config32(libpci_to_lb(dev), (uint16_t)pos, data); return 1; /* success */ } @@ -110,29 +110,29 @@ char *funcp = strrchr(id, '.'); if (funcp) { - filter->func = strtoul(funcp+1, &endptr, 0); + filter->func = strtol(funcp+1, &endptr, 0); if (endptr[0] != '\0') return invalid_pci_device_string; } char *devp = strrchr(id, ':'); if (!devp) { - filter->dev = strtoul(id, &endptr, 0); + filter->dev = strtol(id, &endptr, 0); } else { - filter->dev = strtoul(devp+1, &endptr, 0); + filter->dev = strtol(devp+1, &endptr, 0); } if (endptr != funcp) return invalid_pci_device_string; if (!devp) return NULL; char *busp = strchr(id, ':'); if (busp == devp) { - filter->bus = strtoul(id, &endptr, 0); + filter->bus = strtol(id, &endptr, 0); } else { - filter->bus = strtoul(busp+1, &endptr, 0); + filter->bus = strtol(busp+1, &endptr, 0); } if (endptr != funcp) return invalid_pci_device_string; if (busp == devp) return NULL; - filter->domain = strtoul(id, &endptr, 0); + filter->domain = strtol(id, &endptr, 0); if (endptr != busp) return invalid_pci_device_string; return NULL; @@ -155,15 +155,15 @@ return 1; } -static struct pci_dev *pci_scan_single_bus(struct pci_dev *dev, int bus) +static struct pci_dev *pci_scan_single_bus(struct pci_dev *dev, uint8_t bus) { int devfn; u32 val; unsigned char hdr; for (devfn = 0; devfn < 0x100; devfn++) { - int func = devfn & 0x7; - int slot = (devfn >> 3) & 0x1f; + uint8_t func = devfn & 0x7; + uint8_t slot = (devfn >> 3) & 0x1f; val = pci_read_config32(PCI_DEV(bus, slot, func), REG_VENDOR_ID); @@ -179,7 +179,7 @@ dev->dev = slot; dev->func = func; dev->vendor_id = val & 0xffff; - dev->device_id = val >> 16; + dev->device_id = (uint16_t)(val >> 16); dev->next = 0; hdr = pci_read_config8(PCI_DEV(bus, slot, func), @@ -187,10 +187,10 @@ hdr &= 0x7F; if (hdr == HEADER_TYPE_BRIDGE || hdr == HEADER_TYPE_CARDBUS) { - unsigned int busses; - busses = pci_read_config32(PCI_DEV(bus, slot, func), - REG_PRIMARY_BUS); - busses = (busses >> 8) & 0xFF; + uint8_t busses; + busses = (uint8_t)(pci_read_config32( + PCI_DEV(bus, slot, func), + REG_PRIMARY_BUS) >> 8); /* Avoid recursion if the new bus is the same as * the old bus (insert lame The Who joke here) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd1b179d647f105579bd74b071344668ca0a41ef Gerrit-Change-Number: 37202 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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