coreboot-gerrit November 2019

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Change in ...coreboot[master]: soc/intel/denverton_ns: Allow using FSP repo
by Felix Singer (Code Review) 04 Mar '20

04 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30931 Change subject: soc/intel/denverton_ns: Allow using FSP repo ...................................................................... soc/intel/denverton_ns: Allow using FSP repo Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/denverton_ns/Kconfig 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30931/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8156d18..6f5ed2a 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -85,7 +85,8 @@ bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE + SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ + SOC_INTEL_DENVERTON_NS help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 1096549..dfb5c37 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -78,6 +78,16 @@ help The memory location of the Intel FSP-S binary for this platform. +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" + # CAR memory layout on DENVERTON_NS hardware: ## CAR base address - 0xfef00000 ## CAR size 1MB - 0x100 (0xfff00) -- To view, visit https://review.coreboot.org/c/coreboot/+/30931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Gerrit-Change-Number: 30931 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: README: Spell Web site with one space
by Paul Menzel (Code Review) 03 Mar '20

03 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31384 Change subject: README: Spell Web site with one space ...................................................................... README: Spell Web site with one space Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M payloads/libpayload/README 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31384/1 diff --git a/payloads/libpayload/README b/payloads/libpayload/README index fdf9b18..7348934 100644 --- a/payloads/libpayload/README +++ b/payloads/libpayload/README @@ -49,10 +49,10 @@ Please see the sample/ directory for details. -Website and Mailing List +Web site and Mailing List ------------------------ -The main website is https://www.coreboot.org/Libpayload. +The main web site is https://www.coreboot.org/Libpayload. For additional information, patches, and discussions, please join the coreboot mailing list at https://www.coreboot.org/Mailinglist, where most -- To view, visit https://review.coreboot.org/c/coreboot/+/31384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Gerrit-Change-Number: 31384 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/chromeos: Add unzip as a dependency
by Mete Balci (Code Review) 03 Mar '20

03 Mar '20

Mete Balci has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31821 Change subject: util/chromeos: Add unzip as a dependency ...................................................................... util/chromeos: Add unzip as a dependency unzip might not be installed by default, so it is added as a dependency in crosfirmware script. Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc Signed-off-by: Mete Balci <metebalci(a)gmail.com> --- M util/chromeos/crosfirmware.sh 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31821/1 diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index 9d2ca84..0564106 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -37,6 +37,7 @@ exit_if_uninstalled "debugfs" "e2fsprogs" exit_if_uninstalled "parted" "parted" exit_if_uninstalled "curl" "curl" + exit_if_uninstalled "unzip" "unzip" } get_inventory() -- To view, visit https://review.coreboot.org/c/coreboot/+/31821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc Gerrit-Change-Number: 31821 Gerrit-PatchSet: 1 Gerrit-Owner: Mete Balci <metebalci(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: clang-format: set to 80 chars per line
by Philipp Deppenwiese (Code Review) 03 Mar '20

03 Mar '20

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31947 Change subject: clang-format: set to 80 chars per line ...................................................................... clang-format: set to 80 chars per line Change-Id: If785ff5eb5cbadab92b0c2fed67a202b6d0ed5d4 Signed-off-by: zaolin <zaolin.daisuki(a)gmail.com> --- M .clang-format 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/31947/1 diff --git a/.clang-format b/.clang-format index d853f50..c292e2f 100644 --- a/.clang-format +++ b/.clang-format @@ -7,7 +7,7 @@ IndentCaseLabels: false SortIncludes: false ContinuationIndentWidth: 8 -ColumnLimit: 0 +ColumnLimit: 80 AlwaysBreakBeforeMultilineStrings: true AllowShortLoopsOnASingleLine: false AllowShortFunctionsOnASingleLine: false -- To view, visit https://review.coreboot.org/c/coreboot/+/31947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If785ff5eb5cbadab92b0c2fed67a202b6d0ed5d4 Gerrit-Change-Number: 31947 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Kconfig: Have GDB_STUB depend on DRIVERS_UART
by Arthur Heymans (Code Review) 03 Mar '20

03 Mar '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36604 ) Change subject: Kconfig: Have GDB_STUB depend on DRIVERS_UART ...................................................................... Kconfig: Have GDB_STUB depend on DRIVERS_UART There is no reason to hide the GDB_STUB option when SERIAL_CONSOLE is set. Change-Id: Icbf9a1ac0e617939cafa3d66774bbd467dc01cbc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/36604/1 diff --git a/src/Kconfig b/src/Kconfig index 793927a..ad6c18a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -746,7 +746,7 @@ config GDB_STUB bool "GDB debugging support" default n - depends on CONSOLE_SERIAL + depends on DRIVERS_UART help If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/x86/lib/c_start.S for details. -- To view, visit https://review.coreboot.org/c/coreboot/+/36604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbf9a1ac0e617939cafa3d66774bbd467dc01cbc Gerrit-Change-Number: 36604 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/slot_1: Cache romstage XIP execution
by Arthur Heymans (Code Review) 03 Mar '20

03 Mar '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37164 ) Change subject: cpu/intel/slot_1: Cache romstage XIP execution ...................................................................... cpu/intel/slot_1: Cache romstage XIP execution Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/slot_1/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37164/1 diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 7919974..a8d90e8 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -27,6 +27,7 @@ select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE + select SETUP_XIP_CACHE config DCACHE_RAM_BASE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/37164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f Gerrit-Change-Number: 37164 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton/uart.c: Clean up code
by Felix Singer (Code Review) 02 Mar '20

02 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37121 ) Change subject: soc/intel/denverton/uart.c: Clean up code ...................................................................... soc/intel/denverton/uart.c: Clean up code Since there is only one device ID used for UART, an array is not needed. Therefore, just save the device ID to the device variable. Change-Id: Icd325e1102a85cc175f6025519a47a1b64ee5b46 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/denverton_ns/uart.c 1 file changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/37121/1 diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index 28e0e2e..3b851ee 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -57,15 +57,10 @@ .enable = DEVICE_NOOP }; -static const unsigned short uart_ids[] = { - PCI_DEVICE_ID_INTEL_DENVERTON_HSUART, - 0 -}; - static const struct pci_driver uart_driver __pci_driver = { .ops = &uart_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = uart_ids + .device = PCI_DEVICE_ID_INTEL_DENVERTON_HSUART }; static void hide_hsuarts(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/37121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd325e1102a85cc175f6025519a47a1b64ee5b46 Gerrit-Change-Number: 37121 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton: Move PCI IDs to pci_ids.h
by Felix Singer (Code Review) 02 Mar '20

02 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37120 ) Change subject: soc/intel/denverton: Move PCI IDs to pci_ids.h ...................................................................... soc/intel/denverton: Move PCI IDs to pci_ids.h This patch moves the PCI ID definitions to pci_ids.h file and replaces every occurrence with the new names. The resulting binary doesn't differ from the one without this patch. Used documents: - Intel 337018 Change-Id: Ib7d2aae78c8877f3c9287d03b20a5620db293445 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/include/device/pci_ids.h M src/soc/intel/denverton_ns/csme_ie_kt.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/npk.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/denverton_ns/uart.c M src/soc/intel/denverton_ns/xhci.c 10 files changed, 45 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/37120/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 18d6f60..c7b87b0 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2675,6 +2675,40 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 +/* Intel Denverton (Atom C3000 family) */ +#define PCI_DEVICE_ID_INTEL_DENVERTON_SA 0x1980 +#define PCI_DEVICE_ID_INTEL_DENVERTONAD_SA 0x1995 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP0 0x19a4 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP1 0x19a5 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP2 0x19a6 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP3 0x19a7 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP4 0x19a8 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP5 0x19a9 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP6 0x19aa +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP7 0x19ab +#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS 0x19ac +#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1 0x19b2 +#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2 0x19c2 +#define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0 +#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_1 0x19d1 +#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_2 0x19d2 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_1 0x19d3 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_2 0x19d4 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT 0x19d5 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_3 0x19d6 +#define PCI_DEVICE_ID_INTEL_DENVERTON_HSUART 0x19d8 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_1 0x19e5 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_2 0x19e6 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT 0x19e8 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_3 0x19e9 +#define PCI_DEVICE_ID_INTEL_DENVERTON_EMMC 0x19db +#define PCI_DEVICE_ID_INTEL_DENVERTON_LPC 0x19dc +#define PCI_DEVICE_ID_INTEL_DENVERTON_P2SB 0x19dd +#define PCI_DEVICE_ID_INTEL_DENVERTON_PMC 0x19de +#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS_LEGACY 0x19df +#define PCI_DEVICE_ID_INTEL_DENVERTON_SPI 0x19e0 +#define PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB 0x19e1 + /* Intel LPC device ids */ #define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 #define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c index 5967840..2b730e9 100644 --- a/src/soc/intel/denverton_ns/csme_ie_kt.c +++ b/src/soc/intel/denverton_ns/csme_ie_kt.c @@ -77,8 +77,8 @@ }; static const unsigned short pci_device_ids[] = { - ME_MEKT_DEVID, /* DVN CSME KT */ - IE_MEKT_DEVID, /* DVN IE KT */ + PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT, + PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT, 0 }; diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index faa4d92..a300fd4 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -158,46 +158,4 @@ #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) -#define SA_DEVID 0x1980 -#define SA_DEVID_DNVAD 0x1995 -#define SOC_DEVID SA_DEVID -#define RAS_DEVID 0x19a1 -#define RCEC_DEVID 0x19a2 -#define VRP2_DEVID 0x19a3 -#define PCIE_PORT1_DEVID 0x19a4 -#define PCIE_PORT2_DEVID 0x19a5 -#define PCIE_PORT3_DEVID 0x19a6 -#define PCIE_PORT4_DEVID 0x19a7 -#define PCIE_PORT5_DEVID 0x19a8 -#define PCIE_PORT6_DEVID 0x19a9 -#define PCIE_PORT7_DEVID 0x19aa -#define PCIE_PORT8_DEVID 0x19ab -#define SMBUS2_DEVID 0x19ac -#define AHCI_DEVID 0x19b2 -#define AHCI2_DEVID 0x19c2 -#define XHCI_DEVID 0x19d0 -#define VRP0_DEVID 0x19d1 -#define VRP1_DEVID 0x19d2 -#define ME_HECI1_DEVID 0x19d3 -#define ME_HECI2_DEVID 0x19d4 -#define ME_IEDR_DEVID 0x19ea -#define ME_MEKT_DEVID 0x19d5 -#define ME_HECI3_DEVID 0x19d6 -#define HSUART_DEVID 0x19d8 -#define HSUART1_DEVID HSUART_DEVID -#define HSUART2_DEVID HSUART_DEVID -#define HSUART3_DEVID HSUART_DEVID -#define IE_HECI1_DEVID 0x19e5 -#define IE_HECI2_DEVID 0x19e6 -#define IE_IEDR_DEVID 0x19e7 -#define IE_MEKT_DEVID 0x19e8 -#define IE_HECI3_DEVID 0x19e9 -#define MMC_DEVID 0x19db -#define LPC_DEVID 0x19dc -#define P2SB_DEVID 0x19dd -#define PMC_DEVID 0x19de -#define SMBUS_DEVID 0x19df -#define SPI_DEVID 0x19e0 -#define NPK_DEVID 0x19e1 - #endif /* _DENVERTON_NS_PCI_DEVS_H_ */ diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 123fb24..6481cbe 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -324,7 +324,7 @@ static const struct pci_driver lpc_driver __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = LPC_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_LPC, }; static void finalize_chipset(void *unused) diff --git a/src/soc/intel/denverton_ns/npk.c b/src/soc/intel/denverton_ns/npk.c index 0404893..631aac7 100644 --- a/src/soc/intel/denverton_ns/npk.c +++ b/src/soc/intel/denverton_ns/npk.c @@ -46,5 +46,5 @@ static const struct pci_driver pch_pmc __pci_driver = { .ops = &pmc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = NPK_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB, }; diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 8b52087..cbb9a4e 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -113,5 +113,5 @@ static const struct pci_driver pch_pmc __pci_driver = { .ops = &pmc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PMC_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_PMC, }; diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index ddb8b02..d53d553 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -74,8 +74,8 @@ }; static const unsigned short pci_device_ids[] = { - AHCI_DEVID, /* DVN SATA AHCI */ - AHCI2_DEVID, /* DVN SATA2 AHCI */ + PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1, + PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2, 0 }; diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index 00d5228..50f25c0 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -345,8 +345,8 @@ /* IDs for System Agent device of Intel Denverton SoC */ static const unsigned short systemagent_ids[] = { - SA_DEVID, /* DVN System Agent */ - SA_DEVID_DNVAD, /* DVN-AD System Agent */ + PCI_DEVICE_ID_INTEL_DENVERTON_SA, + PCI_DEVICE_ID_INTEL_DENVERTONAD_SA, 0 }; diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index 50f8a29..28e0e2e 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -58,7 +58,7 @@ }; static const unsigned short uart_ids[] = { - HSUART_DEVID, /* HSUART 0/1/2 */ + PCI_DEVICE_ID_INTEL_DENVERTON_HSUART, 0 }; diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c index 0a4b3b1..a0ed6ba 100644 --- a/src/soc/intel/denverton_ns/xhci.c +++ b/src/soc/intel/denverton_ns/xhci.c @@ -47,5 +47,5 @@ static const struct pci_driver pch_usb_xhci __pci_driver = { .ops = &usb_xhci_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = XHCI_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_XHCI, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/37120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d2aae78c8877f3c9287d03b20a5620db293445 Gerrit-Change-Number: 37120 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: x86/acpi_s3: Remove trailing dots from debug message
by Paul Menzel (Code Review) 02 Mar '20

02 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30806 Change subject: x86/acpi_s3: Remove trailing dots from debug message ...................................................................... x86/acpi_s3: Remove trailing dots from debug message The dot is not needed, as it is no sentence and followed by a line break. Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/arch/x86/acpi_s3.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30806/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ad9fe00..07c0332 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -34,10 +34,10 @@ { if (acpi_slp_type < 0) { if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume.\n"); + printk(BIOS_DEBUG, "S3 Resume\n"); acpi_slp_type = ACPI_S3; } else { - printk(BIOS_DEBUG, "Normal boot.\n"); + printk(BIOS_DEBUG, "Normal boot\n"); acpi_slp_type = ACPI_S0; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Gerrit-Change-Number: 30806 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/superiotool: Add AST2400
by Patrick Rudolph (Code Review) 01 Mar '20

01 Mar '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32984 Change subject: util/superiotool: Add AST2400 ...................................................................... util/superiotool: Add AST2400 Add support for AST2400 Super I/O. The device doesn't have an ID register, so probe for PCI devices and known bits in scratch registers. Tested on platform which has an AST2400. Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/superiotool/Makefile A util/superiotool/aspeed.c M util/superiotool/superiotool.h 3 files changed, 161 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/32984/1 diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 3a0bcf0..d1d7f243 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -53,7 +53,7 @@ ifeq ($(CONFIG_PCI), yes) CFLAGS += -DPCI_SUPPORT -OBJS += pci.o via.o amd.o +OBJS += pci.o via.o amd.o aspeed.o LIBS += -lpci ifeq ($(OS_ARCH),NetBSD) LIBS += -lpciutils diff --git a/util/superiotool/aspeed.c b/util/superiotool/aspeed.c new file mode 100644 index 0000000..0a7b624 --- /dev/null +++ b/util/superiotool/aspeed.c @@ -0,0 +1,151 @@ +/* + * This file is part of the superiotool project. + * + * Copyright (C) 2010 Google Inc. + * Written by David Hendricks <dhendrix(a)google.com> for Aspeed Technology Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "superiotool.h" + +#define DEVICE_SCRATCH_REG 0x21 + +static const struct superio_registers reg_table[] = { + {0x00, "AST2400", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x02, "SUART1", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x02,RSVD,EOT}}, + {0x03, "SUART1", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x02,0x00,EOT}}, + {0x04, "SWC", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67, + 0x70,0x71,EOT}, + {0x00,0x08,0xe6,0x08,0xe0,0x08,0xe4,0x08,0xe8, + 0x09,0x01,EOT}}, + {0x05, "Keyboard config (KBC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x72,0x73, + 0xf0,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x0c,0x02, + 0x83,EOT}}, + {0x07, "GPIO", + {0x30,0x38,0x70,0x71,EOT}, + {0x00,0x00,0x0b,0x01,EOT}}, + {0x0b, "SUART3", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x03,0xe8,0x06,0x02,0x00,EOT}}, + {0x0c, "SUART4", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x02,0xe8,0x05,0x02,0x00,EOT}}, + {0x0d, "iLPC2AHB", + {0x30,0x70,0x71,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5, + 0xf6,0xf7,0xf8,0xfe,EOT}, + {0x00,0x09,0x01,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,0x00,0x00,EOT}}, + {0x0e, "Mailbox", + {0x30,0x60,0x61,0x70,0x71,EOT}, + {0x00,0x08,0xc0,0x09,0x01,EOT}}, + {EOT}}}, + {EOT} +}; + +static void enter_conf_mode_ast(uint16_t port) +{ + OUTB(0xa5, port); + OUTB(0xa5, port); +} + +static void exit_conf_mode_ast(uint16_t port) +{ + OUTB(0xaa, port); +} + +static int detect_ast_pci(void) +{ + int i; + static const uint16_t ids[] = { + 0x2000, 0x1150, + }; + + for (i = 0; i < ARRAY_SIZE(ids); i++) { + if (pci_dev_find(0x1a03, ids[i])) + return 1; + } + + return 0; +} + +static int detect_ast_superio(uint16_t port) +{ + int i; + enter_conf_mode_ast(port); + + /* Aspeed devices doesn't have a DEVICE_ID_REG. + * Host cycles that aren't decoded read as 0xff. + * Probe for the scratch register that are initialized to zero. + * The firmware might overwrite that, but it's the best we have. + * Together with PCI detection that should be sufficient. + */ + + for (i = DEVICE_SCRATCH_REG; i < 0x30; i++) { + if (regval(port, i) == 0) + break; + } + if (i == 0x30) { + if (verbose) + printf(NOTFOUND + "scratch registers all read as non zero\n"); + } + exit_conf_mode_ast(port); + + return i < 0x30; +} + +void probe_idregs_aspeed(uint16_t port) +{ + uint16_t chip_id = 0; + + probing_for("Aspeed", "", port); + + if (!detect_ast_pci()) { + if (verbose) + printf(NOTFOUND "missing PCI device\n"); + return; + } + + if (!detect_ast_superio(port)) + return; + + if (superio_unknown(reg_table, chip_id)) { + if (verbose) + printf(NOTFOUND "id=0x%02x\n", chip_id); + return; + } + + printf("Found Aspeed %s (id=0x%02x) at 0x%x\n", + get_superio_name(reg_table, chip_id), chip_id, port); + chip_found = 1; + + enter_conf_mode_ast(port); + dump_superio("Aspeed", reg_table, port, chip_id, LDN_SEL); + exit_conf_mode_ast(port); +} + +void print_aspeed_chips(void) +{ + print_vendor_chips("Aspeed", reg_table); +} diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index 1a10fb6..f2a4d5e 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -184,6 +184,12 @@ void probe_idregs_ali(uint16_t port); void print_ali_chips(void); +/* aspeed.c */ +#ifdef PCI_SUPPORT +void probe_idregs_aspeed(uint16_t port); +void print_aspeed_chips(void); +#endif + /* amd.c */ void probe_idregs_amd(uint16_t port); void print_amd_chips(void); @@ -252,6 +258,8 @@ {probe_idregs_via, {0x2e, 0x4e, 0x3f0, EOT}}, /* in fact read the BASE from HW */ {probe_idregs_amd, {0xaa, EOT}}, + /* Probe for aspeed PCI devices */ + {probe_idregs_aspeed, {0x2e, 0x4e, EOT}}, #endif {probe_idregs_serverengines, {0x2e, EOT}}, {probe_idregs_infineon, {0x2e, 0x4e, EOT}}, @@ -272,6 +280,7 @@ #ifdef PCI_SUPPORT {print_via_chips}, {print_amd_chips}, + {print_aspeed_chips}, #endif {print_serverengines_chips}, {print_infineon_chips}, -- To view, visit https://review.coreboot.org/c/coreboot/+/32984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1 Gerrit-Change-Number: 32984 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019