Change in coreboot[master]: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl

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Maulik V Vaghela (Code Review)

27 Nov 2019 27 Nov '19

7:40 a.m.

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl

New Kconfig for Jasperlake soc was created and fsp_param for Jasperlake has differences compared to Tigerlake. Thus renaming fsp_params.c to fsp_params_tgl.c to point out correct file as per soc selected.

Also, IFD tool now support jsl soc, so correct Kconfig to use correct IFD chipset based on Kconfig.

Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc R src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/romstage/Makefile.inc R src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 5 files changed, 5 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37267/1

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 01ce7d8..5c17b208 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -96,7 +96,8 @@

config IFD_CHIPSET string - default "tgl" + default "tgl" if SOC_INTEL_TIGERLAKE + default "jsl" if SOC_INTEL_JASPERLAKE

config IED_REGION_SIZE hex diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index b402fa0..feb8d32 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y) +ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE),y)

subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode @@ -33,7 +33,7 @@ ramstage-y += elog.c ramstage-y += espi.c ramstage-y += finalize.c -ramstage-y += fsp_params.c +ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += lockdown.c diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params_tgl.c similarity index 100% rename from src/soc/intel/tigerlake/fsp_params.c rename to src/soc/intel/tigerlake/fsp_params_tgl.c diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc index 8d151e3..4701f75 100644 --- a/src/soc/intel/tigerlake/romstage/Makefile.inc +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -13,7 +13,7 @@ # GNU General Public License for more details. #

-romstage-y += fsp_params.c +romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += pch.c diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c similarity index 100% rename from src/soc/intel/tigerlake/romstage/fsp_params.c rename to src/soc/intel/tigerlake/romstage/fsp_params_tgl.c

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Subrata Banik (Code Review)

27 Nov 27 Nov

7:50 a.m.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Kco... PS1, Line 100: default "jsl" if SOC_INTEL_JASPERLAKE considering submitting separate cl

https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Mak... File src/soc/intel/tigerlake/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Mak... PS1, Line 1: CONFIG_SOC_INTEL_TIGERLAKE_BASE consider submitting separate CL

Arthur Heymans (Code Review)

7:51 a.m.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 1:

(1 comment)

Could you add a dummy board for jasperlake and tigerlake? All this is not buildtested and buildtesting is an essential part of QA.

https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Mak... File src/soc/intel/tigerlake/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Mak... PS1, Line 36: fsp_params_tgl.c No fsp_params for jasperlake?

Maulik V Vaghela (Code Review)

11:02 a.m.

Hello Patrick Rudolph, Subrata Banik, Meera Ravindranath, Aamir Bohra, Ronak Kanabar, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37267

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl

Also, IFD tool now support jsl soc, so correct Kconfig to use correct IFD chipset based on Kconfig.

Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/soc/intel/tigerlake/Makefile.inc R src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/romstage/Makefile.inc R src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 4 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37267/2

Maulik V Vaghela (Code Review)

11:05 a.m.

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 2:

(2 comments)

...

Patch Set 1:

(1 comment)

Could you add a dummy board for jasperlake and tigerlake? All this is not buildtested and buildtesting is an essential part of QA.

Hey Arthur,

yes, currently I am just doing basic changes for SOC..will also push patch for mainboard for rvp soon

https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Kco... PS1, Line 100: default "jsl" if SOC_INTEL_JASPERLAKE

...

considering submitting separate cl

Done

https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Mak... File src/soc/intel/tigerlake/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Mak... PS1, Line 1: CONFIG_SOC_INTEL_TIGERLAKE_BASE

...

consider submitting separate CL

yes, will push separate patch for it

Arthur Heymans (Code Review)

11:11 a.m.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 2:

...

Patch Set 2:

(2 comments)

...
Patch Set 1:

(1 comment)

Could you add a dummy board for jasperlake and tigerlake? All this is not buildtested and buildtesting is an essential part of QA.

Hey Arthur,

yes, currently I am just doing basic changes for SOC..will also push patch for mainboard for rvp soon

The tigerlake_rvp code was in pretty bad shape. Consider adding a simple stub in the mean time just to buildtest the soc code.

Maulik V Vaghela (Code Review)

11:12 a.m.

Hello Patrick Rudolph, Subrata Banik, Meera Ravindranath, Aamir Bohra, Ronak Kanabar, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37267

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl

Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/soc/intel/tigerlake/Makefile.inc R src/soc/intel/tigerlake/fsp_params_jsl.c C src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/romstage/Makefile.inc R src/soc/intel/tigerlake/romstage/fsp_params_jsl.c C src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 6 files changed, 4 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37267/3

Aamir Bohra (Code Review)

2:25 p.m.

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 3: Code-Review+1

Aamir Bohra (Code Review)

1 Dec 1 Dec

9:41 a.m.

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 3:

...

Patch Set 2:

(2 comments)

...
Patch Set 1:

(1 comment)

Could you add a dummy board for jasperlake and tigerlake? All this is not buildtested and buildtesting is an essential part of QA.

Hey Arthur,

yes, currently I am just doing basic changes for SOC..will also push patch for mainboard for rvp soon

Arthur, we are planning to push a mainboard copy CL for jslrvp(based on copy from icelake rvp). We are currently pushing clean up CLs on icelake rvp, including addressing of comments for tglrvp copy patch.

https://review.coreboot.org/c/coreboot/+/37356 https://review.coreboot.org/c/coreboot/+/37354 and couple of more to go.

Ronak Kanabar (Code Review)

6 Dec 6 Dec

9:29 a.m.

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 3: Code-Review+1

Aamir Bohra (Code Review)

2:41 p.m.

Aamir Bohra has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Removed Code-Review+1 by Aamir Bohra aamir.bohra@intel.com

Aamir Bohra (Code Review)

2:42 p.m.

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37267/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/37267/3/src/soc/intel/tigerlake/fsp... PS3, Line 17: #include <fsp/api.h> also needs #include <intelblocks/lpss.h>

Maulik V Vaghela (Code Review)

10 Dec 10 Dec

7:33 a.m.

Hello Patrick Rudolph, Karthik Ramasubramanian, Subrata Banik, Meera Ravindranath, Aamir Bohra, Ronak Kanabar, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37267

to look at the new patch set (#4).

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37267/4

Maulik V Vaghela (Code Review)

3:20 p.m.

Hello Patrick Rudolph, Karthik Ramasubramanian, Subrata Banik, Meera Ravindranath, Aamir Bohra, Ronak Kanabar, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37267

to look at the new patch set (#5).

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37267/5

Maulik V Vaghela (Code Review)

3:22 p.m.

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 5:

...

Patch Set 2:

...
Patch Set 2:

(2 comments)

...
Patch Set 1:

(1 comment)

Could you add a dummy board for jasperlake and tigerlake? All this is not buildtested and buildtesting is an essential part of QA.

Hey Arthur,

yes, currently I am just doing basic changes for SOC..will also push patch for mainboard for rvp soon

The tigerlake_rvp code was in pretty bad shape. Consider adding a simple stub in the mean time just to buildtest the soc code.

Hi Arthur,

I have removed dependency on Jasperlake here. I'll just rename file to fsp_params_tgl and later we can add fsp_params_jsl once we have initial board code for Jsl.

Maulik V Vaghela (Code Review)

16 Dec 16 Dec

12:05 p.m.

Hello Patrick Rudolph, Karthik Ramasubramanian, Subrata Banik, Meera Ravindranath, Aamir Bohra, Ronak Kanabar, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37267

to look at the new patch set (#6).

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37267/6

Aamir Bohra (Code Review)

12:35 p.m.

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 7: Code-Review+2

Karthik Ramasubramanian (Code Review)

18 Dec 18 Dec

5:05 a.m.

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 7: Code-Review+2

Ronak Kanabar (Code Review)

10:44 a.m.

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 7: Code-Review+2

Karthik Ramasubramanian (Code Review)

7:09 p.m.

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 7: -Code-Review

Thinking about it further, are fsp_params significantly different between JSL and TGL.

If the difference is small, then we can keep the differences alone in the fsp_params_${soc}.c and keep the common parts in the fsp_params.c.

Maulik V Vaghela (Code Review)

24 Dec 24 Dec

7:15 a.m.

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 7:

...

Patch Set 7: -Code-Review

Thinking about it further, are fsp_params significantly different between JSL and TGL.

If the difference is small, then we can keep the differences alone in the fsp_params_${soc}.c and keep the common parts in the fsp_params.c.

Hi Karthik, Yes, there is significant delta between fsp_param for jsl and tgl (I would say around 40% is common). So even if we move out common params, files would be still bigger and it may be confusing to people.

I feel it will be good to keep fsp_params separately which will also help in debug in case of any issues since we know exactly which files are being compiled for which soc.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Gerrit-Change-Number: 37267 Gerrit-PatchSet: 7 Gerrit-Owner: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Ronak Kanabar ronak.kanabar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Comment-Date: Tue, 24 Dec 2019 06:15:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Wonkyu Kim (Code Review)

3 Jan 3 Jan

2:10 a.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 8: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/37267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Gerrit-Change-Number: 37267 Gerrit-PatchSet: 8 Gerrit-Owner: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Ronak Kanabar ronak.kanabar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 03 Jan 2020 01:10:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Wonkyu Kim (Code Review)

7 Jan 7 Jan

4:37 a.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Patch Set 9: -Code-Review

(1 comment)

https://review.coreboot.org/c/coreboot/+/37267/9/src/soc/intel/tigerlake/Mak... File src/soc/intel/tigerlake/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37267/9/src/soc/intel/tigerlake/Mak... PS9, Line 36: ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c Need fsp_params_jsl.c for compile for JSL

-- To view, visit https://review.coreboot.org/c/coreboot/+/37267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Gerrit-Change-Number: 37267 Gerrit-PatchSet: 9 Gerrit-Owner: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Ronak Kanabar ronak.kanabar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Tue, 07 Jan 2020 03:37:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Aamir Bohra (Code Review)

4:43 a.m.

Aamir Bohra has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl ......................................................................

Removed Code-Review+2 by Aamir Bohra aamir.bohra@intel.com

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Maulik V Vaghela (Code Review)

8 Jan 8 Jan

5:56 a.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig

Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Patrick Georgi, Srinidhi N Kaushik, Karthik Ramasubramanian, Meera Ravindranath, Nick Vaccaro, Ronak Kanabar, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37267

to look at the new patch set (#10).

Change subject: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig ......................................................................

soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig

Also adding new file for fsp_param_jsl for Jasperlake SoC and currently its the copy of fsp_param_tgl. TODO: update files with correct fsp_params

Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/soc/intel/tigerlake/Makefile.inc R src/soc/intel/tigerlake/fsp_params_jsl.c C src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/romstage/Makefile.inc R src/soc/intel/tigerlake/romstage/fsp_params_jsl.c C src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 6 files changed, 4 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37267/10

-- To view, visit https://review.coreboot.org/c/coreboot/+/37267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Gerrit-Change-Number: 37267 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Ronak Kanabar ronak.kanabar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Wonkyu Kim (Code Review)

6:39 a.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig ......................................................................

Patch Set 10: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/37267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Gerrit-Change-Number: 37267 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Ronak Kanabar ronak.kanabar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 08 Jan 2020 05:39:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Maulik V Vaghela (Code Review)

9 Jan 9 Jan

5:54 a.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig ......................................................................

Patch Set 12:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37267/9/src/soc/intel/tigerlake/Mak... File src/soc/intel/tigerlake/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37267/9/src/soc/intel/tigerlake/Mak... PS9, Line 36: ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c

...

Done

Done

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Aamir Bohra (Code Review)

7:01 a.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig ......................................................................

Patch Set 12: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/37267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Gerrit-Change-Number: 37267 Gerrit-PatchSet: 12 Gerrit-Owner: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Ronak Kanabar ronak.kanabar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Thu, 09 Jan 2020 06:01:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Subrata Banik (Code Review)

12:27 p.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig ......................................................................

Patch Set 12: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/37267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Gerrit-Change-Number: 37267 Gerrit-PatchSet: 12 Gerrit-Owner: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Ronak Kanabar ronak.kanabar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Thu, 09 Jan 2020 11:27:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Subrata Banik (Code Review)

12:28 p.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig ......................................................................

Patch Set 12:

can someone take a look into open comments ?

-- To view, visit https://review.coreboot.org/c/coreboot/+/37267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Gerrit-Change-Number: 37267 Gerrit-PatchSet: 12 Gerrit-Owner: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Ronak Kanabar ronak.kanabar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Thu, 09 Jan 2020 11:28:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Maulik V Vaghela (Code Review)

12 Jan 12 Jan

2:33 p.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig ......................................................................

Patch Set 12:

(4 comments)

https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Mak... File src/soc/intel/tigerlake/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Mak... PS1, Line 1: CONFIG_SOC_INTEL_TIGERLAKE_BASE

...

yes, will push separate patch for it

Done

https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Mak... PS1, Line 36: fsp_params_tgl.c

...

No fsp_params for jasperlake?

Done

https://review.coreboot.org/c/coreboot/+/37267/9/src/soc/intel/tigerlake/Mak... File src/soc/intel/tigerlake/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37267/9/src/soc/intel/tigerlake/Mak... PS9, Line 36: ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c

...

Done

Done

https://review.coreboot.org/c/coreboot/+/37267/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/37267/3/src/soc/intel/tigerlake/fsp... PS3, Line 17: #include <fsp/api.h>

...

also needs #include <intelblocks/lpss. […]

Done

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Subrata Banik (Code Review)

13 Jan 13 Jan

4:40 a.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig ......................................................................

soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig

Also adding new file for fsp_param_jsl for Jasperlake SoC and currently its the copy of fsp_param_tgl. TODO: update files with correct fsp_params

Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37267 Reviewed-by: Aamir Bohra aamir.bohra@intel.com Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/Makefile.inc R src/soc/intel/tigerlake/fsp_params_jsl.c C src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/romstage/Makefile.inc R src/soc/intel/tigerlake/romstage/fsp_params_jsl.c C src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 6 files changed, 4 insertions(+), 2 deletions(-)

Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Aamir Bohra: Looks good to me, approved Wonkyu Kim: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 0d5aecb..532861d 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -33,7 +33,8 @@ ramstage-y += elog.c ramstage-y += espi.c ramstage-y += finalize.c -ramstage-y += fsp_params.c +ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c +ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += lockdown.c diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params_jsl.c similarity index 100% rename from src/soc/intel/tigerlake/fsp_params.c rename to src/soc/intel/tigerlake/fsp_params_jsl.c diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params_tgl.c similarity index 100% copy from src/soc/intel/tigerlake/fsp_params.c copy to src/soc/intel/tigerlake/fsp_params_tgl.c diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc index 8d151e3..2bf9812 100644 --- a/src/soc/intel/tigerlake/romstage/Makefile.inc +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -13,7 +13,8 @@ # GNU General Public License for more details. #

-romstage-y += fsp_params.c +romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c +romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += pch.c diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c similarity index 100% rename from src/soc/intel/tigerlake/romstage/fsp_params.c rename to src/soc/intel/tigerlake/romstage/fsp_params_jsl.c diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c similarity index 100% copy from src/soc/intel/tigerlake/romstage/fsp_params.c copy to src/soc/intel/tigerlake/romstage/fsp_params_tgl.c

-- To view, visit https://review.coreboot.org/c/coreboot/+/37267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Gerrit-Change-Number: 37267 Gerrit-PatchSet: 13 Gerrit-Owner: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Ronak Kanabar ronak.kanabar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Reviewer: caveh jalali caveh@chromium.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: merged

9elements QA (Code Review)

4:50 a.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )

Change subject: soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig ......................................................................

Patch Set 13:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : No test failed. EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : No test failed. EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : No test failed.

Please note: This test is under development and might not be accurate at all!

-- To view, visit https://review.coreboot.org/c/coreboot/+/37267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Gerrit-Change-Number: 37267 Gerrit-PatchSet: 13 Gerrit-Owner: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Ronak Kanabar ronak.kanabar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Reviewer: caveh jalali caveh@chromium.org Gerrit-CC: 9elements QA hardwaretestrobot@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Mon, 13 Jan 2020 03:50:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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9elements QA (Code Review)
Aamir Bohra (Code Review)
Arthur Heymans (Code Review)
Karthik Ramasubramanian (Code Review)
Maulik V Vaghela (Code Review)
Ronak Kanabar (Code Review)
Subrata Banik (Code Review)
Wonkyu Kim (Code Review)