Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )
Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl
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Patch Set 2:
(2 comments)
Patch Set 1:
(1 comment)
Could you add a dummy board for jasperlake and tigerlake? All this is not buildtested and buildtesting is an essential part of QA.
Hey Arthur,
yes, currently I am just doing basic changes for SOC..will also push patch for mainboard for rvp soon
https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Kco...
File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Kco...
PS1, Line 100: default "jsl" if SOC_INTEL_JASPERLAKE
considering submitting separate cl
Done
https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Mak...
File src/soc/intel/tigerlake/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37267/1/src/soc/intel/tigerlake/Mak...
PS1, Line 1: CONFIG_SOC_INTEL_TIGERLAKE_BASE
consider submitting separate CL
yes, will push separate patch for it
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1
Gerrit-Change-Number: 37267
Gerrit-PatchSet: 2
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Gerrit-Comment-Date: Wed, 27 Nov 2019 10:05:34 +0000
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