Maulik V Vaghela has uploaded this change for review.

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soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl

New Kconfig for Jasperlake soc was created and fsp_param for Jasperlake
has differences compared to Tigerlake. Thus renaming fsp_params.c to
fsp_params_tgl.c to point out correct file as per soc selected.

Also, IFD tool now support jsl soc, so correct Kconfig to use correct
IFD chipset based on Kconfig.

Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/Makefile.inc
R src/soc/intel/tigerlake/fsp_params_tgl.c
M src/soc/intel/tigerlake/romstage/Makefile.inc
R src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
5 files changed, 5 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37267/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 01ce7d8..5c17b208 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -96,7 +96,8 @@

config IFD_CHIPSET
string
- default "tgl"
+ default "tgl" if SOC_INTEL_TIGERLAKE
+ default "jsl" if SOC_INTEL_JASPERLAKE

config IED_REGION_SIZE
hex
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc
index b402fa0..feb8d32 100644
--- a/src/soc/intel/tigerlake/Makefile.inc
+++ b/src/soc/intel/tigerlake/Makefile.inc
@@ -1,4 +1,4 @@
-ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y)
+ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE),y)

subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode
@@ -33,7 +33,7 @@
ramstage-y += elog.c
ramstage-y += espi.c
ramstage-y += finalize.c
-ramstage-y += fsp_params.c
+ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c
ramstage-y += gpio.c
ramstage-y += graphics.c
ramstage-y += lockdown.c
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
similarity index 100%
rename from src/soc/intel/tigerlake/fsp_params.c
rename to src/soc/intel/tigerlake/fsp_params_tgl.c
diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc
index 8d151e3..4701f75 100644
--- a/src/soc/intel/tigerlake/romstage/Makefile.inc
+++ b/src/soc/intel/tigerlake/romstage/Makefile.inc
@@ -13,7 +13,7 @@
# GNU General Public License for more details.
#

-romstage-y += fsp_params.c
+romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c
romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-y += romstage.c
romstage-y += pch.c
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
similarity index 100%
rename from src/soc/intel/tigerlake/romstage/fsp_params.c
rename to src/soc/intel/tigerlake/romstage/fsp_params_tgl.c

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1
Gerrit-Change-Number: 37267
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Gerrit-MessageType: newchange