Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37267 )
Change subject: soc/intel/tigerlake: Rename fsp_params to fsp_params_tgl
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Patch Set 5:
Patch Set 2:
Patch Set 2:
(2 comments)
Patch Set 1:
(1 comment)
Could you add a dummy board for jasperlake and tigerlake? All this is not buildtested and buildtesting is an essential part of QA.
Hey Arthur,
yes, currently I am just doing basic changes for SOC..will also push patch for mainboard for rvp soon
The tigerlake_rvp code was in pretty bad shape. Consider adding a simple stub in the mean time just to buildtest the soc code.
Hi Arthur,
I have removed dependency on Jasperlake here. I'll just rename file to fsp_params_tgl and later we can add fsp_params_jsl once we have initial board code for Jsl.
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