November 2019 - coreboot-gerrit

Change in coreboot[master]: timestamps: COLLECT_TIMESTAMPS is always optional
by Kyösti Mälkki (Code Review) Nov. 1, 2019

Nov. 1, 2019

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36527 ) Change subject: timestamps: COLLECT_TIMESTAMPS is always optional ...................................................................... Patch Set 2: Aaron, Julius; Anything in chromeos that breaks in case someone leaves timestamps out from CBMEM? -- To view, visit https://review.coreboot.org/c/coreboot/+/36527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ee4195d266440143344781d39db9578cd8bdcb3 Gerrit-Change-Number: 36527 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Nov 2019 11:44:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/portwell/m107: Remove Intel wifi disable
by Wim Vervoorn (Code Review) Nov. 1, 2019

Nov. 1, 2019

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36503 ) Change subject: mb/portwell/m107: Remove Intel wifi disable ...................................................................... mb/portwell/m107: Remove Intel wifi disable The Intel wifi drivers were disabled by default. This should not be done here as the baseboard defines if this present or not. BUG=N/A TEST=build Change-Id: I364a821f8387d580b1fbfb7cf77b32a3a6dceebb Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/portwell/m107/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/36503/1 diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index 6795584..3ab20f0 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -91,8 +91,4 @@ hex "C Bootblock Size" default 0x4000 -config DRIVERS_INTEL_WIFI - bool - default n - endif # BOARD_PORTWELL_M107 -- To view, visit https://review.coreboot.org/c/coreboot/+/36503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364a821f8387d580b1fbfb7cf77b32a3a6dceebb Gerrit-Change-Number: 36503 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/portwell/m107: Add rev 1.3
by Wim Vervoorn (Code Review) Nov. 1, 2019

Nov. 1, 2019

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36502 ) Change subject: mb/portwell/m107: Add rev 1.3 ...................................................................... mb/portwell/m107: Add rev 1.3 Add support for board revision 1.3 containing Kingston memory. BUG=N/A TEST=tested on portwell m107 module Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M Documentation/mainboard/portwell/pq7-m107.md M src/mainboard/portwell/m107/Kconfig M src/mainboard/portwell/m107/Makefile.inc M src/mainboard/portwell/m107/romstage.c A src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex 5 files changed, 272 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/36502/1 diff --git a/Documentation/mainboard/portwell/pq7-m107.md b/Documentation/mainboard/portwell/pq7-m107.md index e4da415..71bd26a 100644 --- a/Documentation/mainboard/portwell/pq7-m107.md +++ b/Documentation/mainboard/portwell/pq7-m107.md @@ -4,9 +4,10 @@ PQ7-M107 are assembled with different onboard memory modules: Rev 1.0 Onboard Samsung K4B8G1646D-MYKO memory - Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory + Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory + Rev 1.3 Onboard Kingston B5116ECMDXGGB memory -Use 'make menuconfig' to configure `onboard memory manufacture` in Mainboard +Use 'make menuconfig' to configure `onboard memory manufacturer` in Mainboard menu. ## Required blobs @@ -53,7 +54,7 @@ - eMMC - SATA - serial port -- SMbus +- SMBus - HDA (codec on carrier) - initialization with FSP MR2 - SeaBIOS payload (version rel-1.11.0-44-g7961917) diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index 8966b6e..6795584 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -41,6 +41,12 @@ bool "Micron" help Micron MT41K512M16HA memory + +config ONBOARD_MEM_KINGSTON + bool "Kingston" + help + Kingston B5116ECMDXGGB memory + endchoice config MAINBOARD_DIR diff --git a/src/mainboard/portwell/m107/Makefile.inc b/src/mainboard/portwell/m107/Makefile.inc index cca992e..7d4725ef 100644 --- a/src/mainboard/portwell/m107/Makefile.inc +++ b/src/mainboard/portwell/m107/Makefile.inc @@ -25,3 +25,4 @@ # Order of names in SPD_SOURCES is important! SPD_SOURCES = SAMSUNG_K4B8G1646D-MYKO SPD_SOURCES += MICRON_MT41K512M16HA-125A +SPD_SOURCES += KINGSTON_B5116ECMDXGGB diff --git a/src/mainboard/portwell/m107/romstage.c b/src/mainboard/portwell/m107/romstage.c index 0fe7686..1307717 100644 --- a/src/mainboard/portwell/m107/romstage.c +++ b/src/mainboard/portwell/m107/romstage.c @@ -33,6 +33,9 @@ if (CONFIG(ONBOARD_MEM_MICRON)) spd_index = 1; + else if (CONFIG(ONBOARD_MEM_KINGSTON)) + spd_index = 2; + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) die("spd.bin not found\n"); diff --git a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex new file mode 100644 index 0000000..c018620 --- /dev/null +++ b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -0,0 +1,258 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Facebook, Inc. +# Copyright (C) 2019 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# +# 8 Gb DDR3 (1600 MHz 11-11-11) Kingston B5116ECMDXGGB +# +# SINGLE DIE +# + +# 64Mx16x8 ( 8 bank, 16 Rows, 10 Col, 2 KB page size ) +# 6-7-8-9-10-11 +# DDR3L-1600 +# tCk 1.25ns +# tRCD 13.75ns +# tRP 13.75ns +# tRAS 35ns +# tRC 48.75ns +# CL-tRCD-tRP 11-11-11 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 3 = 384 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +23 + +# 1 SPD Revision +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0c = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SODIMM +# bits[6:4]: 0 = Not hybrid +# bits[7]: 0 = Not hybrid +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bits[7]: reserverd +05 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[7:6]: 0 = reserved +21 + +# 6 Module Nominal Voltage +# bits[0]: 0 = 1.5V operable +# bits[1]: 1 = 1.35V operable +# bits[2]: 0 = NOT 1.25V operable +# bits[7:3]: reserved +02 + +# 7 Module Organization +# bits[2:0]: 010b = 16 bits SDRAM device +# bits[5:3]: 000b = 1 ranks +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus width +# bits[2:0]: 3 = 64 bits pirmary bus width +# bits[4:3]: 0 = 0 bits bus witdth extension +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) dividend / divisor +# bits[3:0]: 1 = Divisor +# bits[7:4]: 1 = Dividend +11 + +# 10 Medium Timebase (MTB) dividend +# bits[7:0]: 0 = 1 (timebase 0.125ns) +01 + +# 11 Medium Timebase (MTB) divisor +# bits[7:0]: 8 (timebase 0.125ns) +08 + +# 12 SDRAM Minimum cycle time (tCKmin) +# 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +0A + +# 13 Reserved +00 + +# 14 CAS Latencies supported, Least Significate Byte +# Support 6,7,8,9,10,11 +FC + +# 15 CAS Latencies supported, Most Significate Byte +# No supporting CL 12-18 +00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 tWR = 15 ns +78 + +# 18 Minimum RAS to CAS Delay Time (tRCDmin) +# 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C tRRD = 7.5ns DDR3-1600, 2KB +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 21 Upper Nibble for tRAS and tRC +# 3:0 : 1 higher tRAS = 35ns +# 7:0 : 1 higher tRC = 48.125ns +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte +# lower 0x118 : tRAS = 35ns DDR3-1600 +18 + +# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte +# lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin +81 + +# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte +# lower 0xAF0 : tRFC = 350ns 8 Gb +F0 + +# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte +# higher 0xAF0 : tRFC = 350ns 8 Gb +0A + +# 26 tWTRmin +# 0x3C : tWTR = 7.5 ns (DDR3) +3C + +# 27 tRTPmin +# 0x3C : tRTP = 7.5 ns (DDR3) +3C + +# 28 Upper Nibble for tFAW +# Bit [3:0] : 1 = higher 0x140 tFAW = 40ns +01 + +# 29 tFAWmin Lower +# lower 0x140 : tFAW = 40ns +40 + +# 30 SDRAM Optional Features +# byte [0] : 1 = RZQ/6 is support +# byte [1] : 1 = RZQ/7 is supported +# byte [7] : 1 = DLL-Off Mode support +83 + +# 31 Thermal options +# byte [0] : 1 = 0 - 95C +# byte [2] : 0 = Auto Self Refresh (ASR) is not supported +# byte [7] : 0 = Partial Array Self Refres (PASR) is not supported +01 + +# 32 Module Thermal support +# byte [0] : 0 = Thermal sensor accuracy undefined +# byte [7] : 0 = No thermal sensor +00 + +# 33 SDRAM device type +# byte [1:0] : 00b = Signal Loading not specified +# byte [6:4] : 000b = Die count not specified +# byte [7] : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine tCKmin +# 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +00 + +# 35 Fine tAAmin +# 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin +00 + +# 36 Fine tRCDmin +# 0x00 tRCD = 13.125ns DDR3-1600K downbin +00 + +# 37 Fine tRPmin +# 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin +00 + +# 38 Fine tRCmin +# 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin +00 + +# 39-59 reserved, general section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60-116 Module specific section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 + +# 117-118 Module Manufacturer +01 98 + +# 119 Module Manufacturing Location +00 + +# 120-121 Module Manufacturing Date +13 0A + +# 122-125 Module Serial number +00 00 00 00 + +# 126-127 SPD CRC +00 00 + +# 128-145 Module Part number +66 53 49 49 54 69 67 77 68 88 71 71 66 00 00 00 +00 00 + +# 145-146 Module revision code +00 00 + +# 148-149 DRAM Manufacturer ID code +01 98 + +# 150-175 Manufacturer Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 + +# 176-255 Open for Customer Use + +# 176 - 255 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/36502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Gerrit-Change-Number: 36502 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/fbg1701: Disable Intel wifi
by Wim Vervoorn (Code Review) Nov. 1, 2019

Nov. 1, 2019

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36505 ) Change subject: mb/facebook/fbg1701: Disable Intel wifi ...................................................................... mb/facebook/fbg1701: Disable Intel wifi The facebook fbg1701 never contains Intel wifi functionality so this can be disabled. BUG=N/A TEST=tested on facebook fbg1701 Change-Id: Iab7dd760020cb7a9f7fea24812afb19bf5e62183 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/36505/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index e80b7fe..a6c2846 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -104,4 +104,8 @@ hex default 0xFFFF9C00 +config DRIVERS_INTEL_WIFI + bool + default n + endif # BOARD_FACEBOOK_FBG1701 -- To view, visit https://review.coreboot.org/c/coreboot/+/36505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab7dd760020cb7a9f7fea24812afb19bf5e62183 Gerrit-Change-Number: 36505 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/tsc: Replace TSC_CONSTANT_RATE with UNKNOWN_TSC_RATE
by Kyösti Mälkki (Code Review) Nov. 1, 2019

Nov. 1, 2019

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33928 ) Change subject: cpu/x86/tsc: Replace TSC_CONSTANT_RATE with UNKNOWN_TSC_RATE ...................................................................... Patch Set 13: Patrick R: Any ideas how to implement tsc_freq_mhz() for qemu-x86 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/33928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Gerrit-Change-Number: 33928 Gerrit-PatchSet: 13 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Nov 2019 11:40:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/uuid: Add UUID parsing function
by Nico Huber (Code Review) Nov. 1, 2019

Nov. 1, 2019

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36297 ) Change subject: lib/uuid: Add UUID parsing function ...................................................................... lib/uuid: Add UUID parsing function Implement a simple function that parses a canonical UUID string into the common byte representation. Inspired by acpigen_write_uuid(). Change-Id: Ia1bd883c740873699814fde6c6ddc1937a40093e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/include/uuid.h M src/lib/Makefile.inc A src/lib/uuid.c 3 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/36297/1 diff --git a/src/include/uuid.h b/src/include/uuid.h index 0209055..b8827b0 100644 --- a/src/include/uuid.h +++ b/src/include/uuid.h @@ -18,6 +18,22 @@ #include <string.h> +#define UUID_LEN 16 +#define UUID_STRLEN 36 + +/* + * Parses a canonical UUID string into the common byte representation + * where the first three words are interpreted as little endian: + * + * The UUID + * "00112233-4455-6677-8899-aabbccddeeff" + * is stored as + * 33 22 11 00 55 44 77 66 88 99 aa bb cc dd ee ff + * + * Returns negative value on error, 0 on success. + */ +int parse_uuid(uint8_t *uuid, const char *uuid_str); + typedef struct { uint8_t b[16]; } __packed guid_t; diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e5678ff..da7b4bb 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -346,3 +346,5 @@ spd.bin-file := $(LIB_SPD_BIN) spd.bin-type := spd endif + +ramstage-y += uuid.c diff --git a/src/lib/uuid.c b/src/lib/uuid.c new file mode 100644 index 0000000..b5c00d7 --- /dev/null +++ b/src/lib/uuid.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <lib.h> +#include <uuid.h> + +int parse_uuid(uint8_t *const uuid, const char *const uuid_str) +{ + const uint8_t order[] = { 3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15 }; + uint8_t uuid_binstr[UUID_LEN]; + unsigned int i; + + if (strlen(uuid_str) != UUID_STRLEN) + return -1; + if (uuid_str[8] != '-' || uuid_str[13] != '-' || + uuid_str[18] != '-' || uuid_str[23] != '-') + return -1; + if (hexstrtobin(uuid_str, uuid_binstr, UUID_LEN) != UUID_LEN) + return -1; + for (i = 0; i < UUID_LEN; ++i) + uuid[i] = uuid_binstr[order[i]]; + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1bd883c740873699814fde6c6ddc1937a40093e Gerrit-Change-Number: 36297 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/{mediatek,sifive}: Remove unused 'include <arch/barrier.h>'
by HAOUAS Elyes (Code Review) Nov. 1, 2019

Nov. 1, 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36489 ) Change subject: soc/{mediatek,sifive}: Remove unused 'include <arch/barrier.h>' ...................................................................... soc/{mediatek,sifive}: Remove unused 'include <arch/barrier.h>' Change-Id: Ia15824effc8f846ff1143abe698c5a0546df7868 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/include/soc/spm.h M src/soc/sifive/fu540/otp.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/36489/1 diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 6dda102..f9bd507 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/barrier.h> #include <device/mmio.h> #include <assert.h> #include <console/console.h> diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index 3d8e578..d0a7aa7 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -16,7 +16,6 @@ #ifndef SOC_MEDIATEK_MT8183_SPM_H #define SOC_MEDIATEK_MT8183_SPM_H -#include <arch/barrier.h> #include <soc/addressmap.h> #include <stdint.h> #include <types.h> diff --git a/src/soc/sifive/fu540/otp.c b/src/soc/sifive/fu540/otp.c index dfdd960..10647f4 100644 --- a/src/soc/sifive/fu540/otp.c +++ b/src/soc/sifive/fu540/otp.c @@ -15,7 +15,6 @@ #include <stddef.h> #include <delay.h> -#include <arch/barrier.h> #include <device/mmio.h> #include <console/console.h> #include <console/uart.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/36489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15824effc8f846ff1143abe698c5a0546df7868 Gerrit-Change-Number: 36489 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/fsp_baytrail: Remove unused 'barrier()'
by HAOUAS Elyes (Code Review) Nov. 1, 2019

Nov. 1, 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36488 ) Change subject: soc/intel/fsp_baytrail: Remove unused 'barrier()' ...................................................................... soc/intel/fsp_baytrail: Remove unused 'barrier()' Change-Id: I4330fd9b2ec6ca36beae3213642f7a4ae61f7dbe Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/fsp_baytrail/include/soc/baytrail.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/36488/1 diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h index 3a2fcaa..de902aa 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h @@ -47,8 +47,6 @@ #ifndef __ASSEMBLER__ #include <device/device.h> -static inline void barrier(void) { asm("" ::: "memory"); } - int bridge_silicon_revision(void); void rangeley_early_initialization(void); void set_max_freq(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/36488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4330fd9b2ec6ca36beae3213642f7a4ae61f7dbe Gerrit-Change-Number: 36488 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/kontron/bsl6: Add new Skylake COMe module
by Angel Pons (Code Review) Nov. 1, 2019

Nov. 1, 2019

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29480 ) Change subject: [WIP] mb/kontron/bsl6: Add new Skylake COMe module ...................................................................... Patch Set 11: Code-Review+1 (11 comments) Any documentation? https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… File src/mainboard/kontron/bsl6/Kconfig: https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… PS11, Line 3: # dummy Please remove https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… PS11, Line 15: select MAINBOARD_USES_FSP2_0 Not sure if this is needed anymore with SKL FSP 1.1 dropped https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… File src/mainboard/kontron/bsl6/acpi/mainboard.asl: https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… PS11, Line 19: Scope (\_SB) : { : Device (PWRB) Maybe replace with "Device (\_SB.PWRB)" ? https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… File src/mainboard/kontron/bsl6/cmos.layout: PS11: Are all the commented-out entries needed? https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… File src/mainboard/kontron/bsl6/dsdt.asl: https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… PS11, Line 37: Scope (\_SB) { : Device (PCI0) Device (\_SB.PCI0) https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… PS11, Line 46: #include <soc/intel/skylake/acpi/sleepstates.asl> I'd rather #include <southbridge/intel/common/acpi/sleepstates.asl> https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… File src/mainboard/kontron/bsl6/gpio.h: https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… PS11, Line 24: #define GPIO_SPEAKER_MAXIM_AMP_SDMODE GPP_B2 Seems copied off some Google board https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… File src/mainboard/kontron/bsl6/variants/boxer26/devicetree.cb: https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… PS11, Line 104: register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V Seems copied off some Google board https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… PS11, Line 135: device pci 19.1 off end # I2C #5 : device pci 19.2 off end # I2C #4 This inversion looks odd, but I didn't open any datasheet https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… File src/mainboard/kontron/bsl6/variants/bsl6/devicetree.cb: PS11: Some of that would better fit into an overridetree https://review.coreboot.org/c/coreboot/+/29480/11/src/mainboard/kontron/bsl… PS11, Line 120: register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V Looks copied -- To view, visit https://review.coreboot.org/c/coreboot/+/29480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5 Gerrit-Change-Number: 29480 Gerrit-PatchSet: 11 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Nov 2019 11:35:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/i945; Remove unused 'barrier()' function
by HAOUAS Elyes (Code Review) Nov. 1, 2019

Nov. 1, 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36124 ) Change subject: nb/i945; Remove unused 'barrier()' function ...................................................................... nb/i945; Remove unused 'barrier()' function Change-Id: I0c33a1f3f9c33c15a901fe90258ed989e9641701 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/i945.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/36124/1 diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 69a6413..4dd5379 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -361,8 +361,6 @@ #define DMIDRCCFG 0xeb4 /* 32bit */ -static inline void barrier(void) { asm("" ::: "memory"); } - int i945_silicon_revision(void); void i945_early_initialization(void); void i945_late_initialization(int s3resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/36124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c33a1f3f9c33c15a901fe90258ed989e9641701 Gerrit-Change-Number: 36124 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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