coreboot-gerrit November 2019

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Change in coreboot[master]: mb/intel/saddlebrook: Enable Chipset_lockdown coreboot config
by PraveenX Hodagatta Pranesh (Code Review) 01 Nov '19

01 Nov '19

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36451 ) Change subject: mb/intel/saddlebrook: Enable Chipset_lockdown coreboot config ...................................................................... mb/intel/saddlebrook: Enable Chipset_lockdown coreboot config This patch enables lockdown configuration for saddlebrook platform BUG=None TEST=Boot to Linux on saddlebrook and verified MRC is restored on warm, cold, resume boot path's. Change-Id: Ia324c118b0c8e72b66a757dee5be43ba79abbeab Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> --- M src/mainboard/intel/saddlebrook/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/36451/1 diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 385a4be..f6727ef 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -61,6 +61,11 @@ register "serirq_mode" = "SERIRQ_CONTINUOUS" + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | -- To view, visit https://review.coreboot.org/c/coreboot/+/36451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia324c118b0c8e72b66a757dee5be43ba79abbeab Gerrit-Change-Number: 36451 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: mb/intel/saddlebrook: Select coreboot MP init
by PraveenX Hodagatta Pranesh (Code Review) 01 Nov '19

01 Nov '19

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36450 ) Change subject: mb/intel/saddlebrook: Select coreboot MP init ...................................................................... mb/intel/saddlebrook: Select coreboot MP init use coreboot MP init for saddlebrook by default. BUG=None TEST=Boot till linux on saddlebrook and verified the AP's proper initialization using 'cat /proc/cpuinfo' command. Change-Id: I2db2fe92c8ba0e649dccf95ce804a97ae4a05603 Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> --- M src/mainboard/intel/saddlebrook/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/36450/1 diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index cd18541..315104e 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -30,7 +30,6 @@ select SUPERIO_NUVOTON_NCT6776_COM_A select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION - select USE_INTEL_FSP_MP_INIT config IRQ_SLOT_COUNT int -- To view, visit https://review.coreboot.org/c/coreboot/+/36450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2db2fe92c8ba0e649dccf95ce804a97ae4a05603 Gerrit-Change-Number: 36450 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-MessageType: newchange

8 12

Change in coreboot[master]: Documentation: Fix typo
by Patrick Rudolph (Code Review) 01 Nov '19

01 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36540 ) Change subject: Documentation: Fix typo ...................................................................... Documentation: Fix typo The document isn't included in any toc-tree due to a typo. Change-Id: Ic1491dde2d48b5d004fc28c743bbee6de12f433c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/36540/1 diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md index 3ba4c3f..adee88a 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md @@ -7,7 +7,7 @@ ## Supported boards - [X11SSH-TF](x11ssh-tf/x11ssh-tf.md) -- [X11SSM-F](x11ssh-tf/x11ssm-f.md) +- [X11SSM-F](x11ssm-f/x11ssm-f.md) ## Required proprietary blobs -- To view, visit https://review.coreboot.org/c/coreboot/+/36540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1491dde2d48b5d004fc28c743bbee6de12f433c Gerrit-Change-Number: 36540 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: soc/skylake/vr_config: fix VR config for KBL-U CPUs
by Maxim Polyakov (Code Review) 01 Nov '19

01 Nov '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36058 ) Change subject: soc/skylake/vr_config: fix VR config for KBL-U CPUs ...................................................................... soc/skylake/vr_config: fix VR config for KBL-U CPUs These changes are in accordance with the documentation: [1] page 106, 7th Generation Intel(R) Processor Families for U/Y Platforms and 8th Generation Intel(R) Processor Family for U Quad Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019. Document Number: 334661-006 Change-Id: I5232a7a670b97d51ff3b3b71a08f25f961ac1d6f Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/vr_config.c 1 file changed, 15 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/36058/1 diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index b78d336..3cfa70e 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -135,15 +135,17 @@ * SKL-U + OPC (15W) GT3 dual 5.1 29 57/19 * SKL-U (15W) GT2 dual 4.5 29 31 * - * KBL-U/R + OPC (28W) GT3 dual 5.1 32 57/19 - * KBL-U/R + OPC (15W) GT3 dual 5.1 32 57/19 + * KBL-U + OPC (28W) GT3 dual 5.1 32 57/19 + * KBL-U + OPC (15W) GT3 dual 5.1 32 57/19 + * KBL-U (15W) GT1/2 dual 4.5 32 31 + * KBL-U [*] (15W) GT1 quad 4.5 29 31 * * KBL-U/R (15W) GT2 quad 6 64 31 - * KBL-U/R (15W) GT1/2 dual 4.5 32 31 - * KBL-U/R (15W) GT2 quad 4.5 29 31 * * SKL/KBL-Y (6W) 4.1 24 24 * SKL/KBL-Y (4.5W) 4.1 24 24 + * + * [*] Pentium/Celeron CPUs with HD Graphics 610 */ switch (mch_id) { @@ -234,10 +236,17 @@ case PCI_DEVICE_ID_INTEL_KBL_ID_U: { uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.5, 32, 0, 31, 31); - if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || - (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) + if (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM) icc_max[VR_IA_CORE] = VR_CFG_AMP(29); + else if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || + (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) { + const uint16_t icc_max_gt3[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_ICC(5.1, 32, 0, 57, 19); + + return icc_max_gt3[domain]; + } + return icc_max[domain]; } default: -- To view, visit https://review.coreboot.org/c/coreboot/+/36058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5232a7a670b97d51ff3b3b71a08f25f961ac1d6f Gerrit-Change-Number: 36058 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi
by Subrata Banik (Code Review) 01 Nov '19

01 Nov '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36463 ) Change subject: soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi ...................................................................... soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi This patch creates a common instance of sleepstates.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask skl, cnl & icl soc code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/asrock/h110m/dsdt.asl M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/eve/dsdt.asl M src/mainboard/google/fizz/dsdt.asl M src/mainboard/google/glados/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/poppy/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/kblrvp/dsdt.asl M src/mainboard/intel/kunimitsu/dsdt.asl M src/mainboard/intel/saddlebrook/dsdt.asl M src/mainboard/purism/librem_skl/dsdt.asl M src/mainboard/razer/blade_stealth_kbl/dsdt.asl M src/mainboard/supermicro/x11-lga1151-series/dsdt.asl R src/soc/intel/common/block/acpi/acpi/sleepstates.asl D src/soc/intel/icelake/acpi/sleepstates.asl D src/soc/intel/skylake/acpi/sleepstates.asl 21 files changed, 21 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/36463/1 diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl index f3e216d..49919d8 100644 --- a/src/mainboard/asrock/h110m/dsdt.asl +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -48,7 +48,7 @@ } // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index 8a43784..65c7be2 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -49,7 +49,7 @@ #endif // Chipset specific sleep states - #include <soc/intel/icelake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 5ffdf18..4d2c4bf 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -54,7 +54,7 @@ #endif /* Chipset specific sleep states */ - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> /* Low power idle table */ #include <soc/intel/cannonlake/acpi/lpit.asl> diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index a705457..bf207b7 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -48,7 +48,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 03df2b9..112673c 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -48,7 +48,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index af5f99d..6fe0cbd 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -49,7 +49,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 344e4a7..fd3df6e 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -52,10 +52,10 @@ #endif /* Chipset specific sleep states */ - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> - /* Low power idle table */ - #include <soc/intel/cannonlake/acpi/lpit.asl> + /* Low power idle table */ + #include <soc/intel/cannonlake/acpi/lpit.asl> /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 34862df..dd02606 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -55,7 +55,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 22e283f..5cfde62 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -54,7 +54,7 @@ #endif /* Chipset specific sleep states */ - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> /* Low power idle table */ #include <soc/intel/cannonlake/acpi/lpit.asl> diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index 5f4a349..4b7454c 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -45,6 +45,6 @@ #endif // Chipset specific sleep states - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index c5f1136..952f345 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -45,6 +45,6 @@ #endif // Chipset specific sleep states - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 15890f1..c84e41a 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -60,7 +60,7 @@ #endif // Chipset specific sleep states - #include <soc/intel/icelake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 8a16551..83db423 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -57,7 +57,7 @@ #endif // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index af5f99d..6fe0cbd 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -49,7 +49,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index ac929a6..eb053b1 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -43,7 +43,7 @@ } // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index 1bf202e..14525d7 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -44,7 +44,7 @@ } // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl index e110067..72184eb 100644 --- a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl +++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl @@ -43,7 +43,7 @@ } // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> #include "acpi/mainboard.asl" } diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl index ac929a6..eb053b1 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl +++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl @@ -43,7 +43,7 @@ } // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl> // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/soc/intel/cannonlake/acpi/sleepstates.asl b/src/soc/intel/common/block/acpi/acpi/sleepstates.asl similarity index 94% rename from src/soc/intel/cannonlake/acpi/sleepstates.asl rename to src/soc/intel/common/block/acpi/acpi/sleepstates.asl index 2a351b6..1ab0e68 100644 --- a/src/soc/intel/cannonlake/acpi/sleepstates.asl +++ b/src/soc/intel/common/block/acpi/acpi/sleepstates.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. + * Copyright (C) 2019 Intel Corp. * * * This program is free software; you can redistribute it and/or modify diff --git a/src/soc/intel/icelake/acpi/sleepstates.asl b/src/soc/intel/icelake/acpi/sleepstates.asl deleted file mode 100644 index 13cc358..0000000 --- a/src/soc/intel/icelake/acpi/sleepstates.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) diff --git a/src/soc/intel/skylake/acpi/sleepstates.asl b/src/soc/intel/skylake/acpi/sleepstates.asl deleted file mode 100644 index 905a3e2..0000000 --- a/src/soc/intel/skylake/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (\_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) -Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) -- To view, visit https://review.coreboot.org/c/coreboot/+/36463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Gerrit-Change-Number: 36463 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

8 34

Change in coreboot[master]: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi
by Subrata Banik (Code Review) 01 Nov '19

01 Nov '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36455 ) Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ...................................................................... soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi This patch creates a common instance of lpc.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask specific soc code to refer lpc.asl from common code block. Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI rather LPC. TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify Device(LPCB) device presence after booting to OS. Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- D src/soc/intel/apollolake/acpi/lpc.asl M src/soc/intel/apollolake/acpi/southbridge.asl M src/soc/intel/cannonlake/acpi/southbridge.asl R src/soc/intel/common/block/acpi/acpi/lpc.asl M src/soc/intel/denverton_ns/acpi/lpc.asl M src/soc/intel/denverton_ns/include/soc/iomap.h D src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/skylake/acpi/lpc.asl 9 files changed, 48 insertions(+), 340 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/36455/1 diff --git a/src/soc/intel/apollolake/acpi/lpc.asl b/src/soc/intel/apollolake/acpi/lpc.asl deleted file mode 100644 index 749daf7..0000000 --- a/src/soc/intel/apollolake/acpi/lpc.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel LPC Bus Device - 0:1f.0 */ - -Device (LPCB) -{ - Name (_ADR, 0x001f0000) -} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 7c9c873..9acb9ae 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -33,7 +33,7 @@ #include "xhci.asl" /* LPC */ -#include "lpc.asl" +#include <soc/intel/common/block/acpi/acpi/lpc.asl> /* eMMC */ #include "scs.asl" diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 8ba3d89..b52de65 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -32,7 +32,7 @@ #endif /* LPC 0:1f.0 */ -#include "lpc.asl" +#include <soc/intel/common/block/acpi/acpi/lpc.asl> /* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/cannonlake/acpi/lpc.asl b/src/soc/intel/common/block/acpi/acpi/lpc.asl similarity index 78% rename from src/soc/intel/cannonlake/acpi/lpc.asl rename to src/soc/intel/common/block/acpi/acpi/lpc.asl index f1c1bf3..b0f981c 100644 --- a/src/soc/intel/cannonlake/acpi/lpc.asl +++ b/src/soc/intel/common/block/acpi/acpi/lpc.asl @@ -1,9 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,11 +13,28 @@ * GNU General Public License for more details. */ +/* Intel LPC/eSPI Bus Device - 0:1f.0 */ + Device (LPCB) { Name (_ADR, 0x001f0000) Name (_DDN, "LPC Bus Device") + /* DMA Controller */ + Device (DMAC) + { + Name (_HID, EISAID("PNP0200")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x00, 0x00, 0x01, 0x20) + IO (Decode16, 0x81, 0x81, 0x01, 0x11) + IO (Decode16, 0x93, 0x93, 0x01, 0x0d) + IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } + }) + } + + /* Firmware Hub */ Device (FWH) { Name (_HID, EISAID ("INT0800")) @@ -30,9 +45,11 @@ }) } + /* High Precision Event Timer */ Device (HPET) { Name (_HID, EISAID ("PNP0103")) + Name (_CID, 0x010CD041) Name (_DDN, "High Precision Event Timer") Name (_CRS, ResourceTemplate () { @@ -40,10 +57,22 @@ }) Method (_STA, 0) { - Return (0xf) + Return (0xF) } } + /* FPU */ + Device(MATH) + { + Name (_HID, EISAID("PNP0C04")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) + IRQNoFlags() { 13 } + }) + } + + /* AT Interrupt Controller */ Device (PIC) { Name (_HID, EISAID ("PNP0000")) @@ -71,6 +100,7 @@ }) } + /* LPC device: Resource consumption */ Device (LDRC) { Name (_HID, EISAID ("PNP0C02")) @@ -92,6 +122,7 @@ }) } + /* Real Time Clock Device */ Device (RTC) { Name (_HID, EISAID ("PNP0B00")) @@ -102,6 +133,7 @@ }) } + /* Timer */ Device (TIMR) { Name (_HID, EISAID ("PNP0100")) @@ -113,5 +145,4 @@ IRQNoFlags () {0} }) } - } diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl index cc36451..4b6e786 100644 --- a/src/soc/intel/denverton_ns/acpi/lpc.asl +++ b/src/soc/intel/denverton_ns/acpi/lpc.asl @@ -16,10 +16,11 @@ */ // Intel LPC Bus Device - 0:1f.0 +#include <soc/intel/common/block/acpi/acpi/lpc.asl> -Device (LPCB) +Scope (\_SB.PCI0.LPCB) { - Name(_ADR, 0x001f0000) + #include "irqlinks.asl" OperationRegion(LPC0, PCI_Config, 0x00, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) @@ -29,8 +30,6 @@ IOD1, 8, } - #include "irqlinks.asl" - Device(APIC) // IO APIC { Name(_HID,EISAID("PNP0003")) @@ -40,96 +39,6 @@ }) } - Device (HPET) - { - Name (_HID, EISAID("PNP0103")) - Name (_CID, 0x010CD041) - - Method (_STA, 0) // Device Status - { - Return (0xF) // Enable and show device - } - - Name(_CRS, ResourceTemplate() - { - Memory32Fixed(ReadOnly, DEFAULT_HPET_ADDR, 0x400) - }) - } - - Device(PIC) // 8259 Interrupt Controller - { - Name(_HID,EISAID("PNP0000")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device(LDRC) // LPC device: Resource consumption - { - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 2) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x70, 0x70, 0x1, 0x01) // NMI Enable. - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap - - // BIOS ROM shadow memory range - Memory32Fixed(ReadOnly, 0x000E0000, 0x20000) - - // BIOS flash 16MB - Memory32Fixed(ReadOnly,0xFF000000,0x1000000) - }) - } - - Device (RTC) // Real Time Clock - { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } - }) - } - - Device (TIMR) // Intel 8254 timer - { - Name(_HID, EISAID("PNP0100")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} - }) - } - Device(IUR3) // Internal UART 1 { Name(_HID, EISAID("PNP0501")) diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index 8bcef91..c512d55 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -31,6 +31,8 @@ #define ACPI_BASE_ADDRESS DEFAULT_PMBASE #define DEFAULT_TCO_BASE 0x400 +#define HPET_BASE_ADDRESS 0xfed00000 + /* Southbridge internal device MEM BARs (Set to match FSP settings) */ #define DEFAULT_PCR_BASE 0xfd000000 #define DEFAULT_PWRM_BASE 0xfe000000 diff --git a/src/soc/intel/icelake/acpi/espi.asl b/src/soc/intel/icelake/acpi/espi.asl deleted file mode 100644 index 4456812..0000000 --- a/src/soc/intel/icelake/acpi/espi.asl +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/* Device identifier is not changed to ESPI to maintain coherency with ec.asl */ -Device (LPCB) -{ - Name (_ADR, 0x001f0000) - Name (_DDN, "ESPI Bus Device") - - Device (FWH) - { - Name (_HID, EISAID ("INT0800")) - Name (_DDN, "Firmware Hub") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID ("PNP0103")) - Name (_DDN, "High Precision Event Timer") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - Method (_STA, 0) - { - Return (0xf) - } - } - - Device (PIC) - { - Name (_HID, EISAID ("PNP0000")) - Name (_DDN, "8259 Interrupt Controller") - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device (LDRC) - { - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 2) - Name (_DDN, "Legacy Device Resources") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, - 0x1, 0xff) - }) - } - - Device (RTC) - { - Name (_HID, EISAID ("PNP0B00")) - Name (_DDN, "Real Time Clock") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x70, 0x70, 1, 8) - }) - } - - Device (TIMR) - { - Name (_HID, EISAID ("PNP0100")) - Name (_DDN, "8254 Timer") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags () {0} - }) - } - -} diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index ffd2fcc..389963e 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -33,7 +33,7 @@ #include "gpio.asl" /* ESPI 0:1f.0 */ -#include "espi.asl" +#include <soc/intel/common/block/acpi/acpi/lpc.asl> /* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl index c9167ad..7dd0298 100644 --- a/src/soc/intel/skylake/acpi/lpc.asl +++ b/src/soc/intel/skylake/acpi/lpc.asl @@ -15,105 +15,11 @@ * GNU General Public License for more details. */ -Device (LPCB) +// Intel LPC Bus Device - 0:1f.0 +#include <soc/intel/common/block/acpi/acpi/lpc.asl> + +Scope (\_SB.PCI0.LPCB) { - Name (_ADR, 0x001f0000) - Name (_DDN, "LPC Bus Device") - - Device (FWH) - { - Name (_HID, EISAID ("INT0800")) - Name (_DDN, "Firmware Hub") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID ("PNP0103")) - Name (_DDN, "High Precision Event Timer") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - Method (_STA, 0) - { - Return (0xf) - } - } - - Device (PIC) - { - Name (_HID, EISAID ("PNP0000")) - Name (_DDN, "8259 Interrupt Controller") - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device (LDRC) - { - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 2) - Name (_DDN, "Legacy Device Resources") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, - 0x1, 0xff) - }) - } - - Device (RTC) - { - Name (_HID, EISAID ("PNP0B00")) - Name (_DDN, "Real Time Clock") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x70, 0x70, 1, 8) - }) - } - - Device (TIMR) - { - Name (_HID, EISAID ("PNP0100")) - Name (_DDN, "8254 Timer") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags () {0} - }) - } - #include <acpi/ec.asl> #include <acpi/superio.asl> } -- To view, visit https://review.coreboot.org/c/coreboot/+/36455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87 Gerrit-Change-Number: 36455 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

8 26

Change in coreboot[master]: arch/acpi.h: Use the predefined typedef acpi_addr_t
by Name of user not set (Code Review) 01 Nov '19

01 Nov '19

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36429 ) Change subject: arch/acpi.h: Use the predefined typedef acpi_addr_t ...................................................................... arch/acpi.h: Use the predefined typedef acpi_addr_t Use already declared typedef and modify the usage accordingly. Change-Id: Icc8413050bfae896d78605416aaaaa6a52eb39f1 Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com> --- M src/arch/x86/include/arch/acpi.h 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/36429/1 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 20c244c..479067f 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -161,7 +161,7 @@ typedef struct acpi_hpet { acpi_header_t header; u32 id; - struct acpi_gen_regaddr addr; + acpi_addr_t addr; u8 number; u16 min_tick; u8 attributes; @@ -527,7 +527,7 @@ u16 iapc_boot_arch; u8 res2; u32 flags; - struct acpi_gen_regaddr reset_reg; + acpi_addr_t reset_reg; u8 reset_value; u16 ARM_boot_arch; u8 FADT_MinorVersion; @@ -535,14 +535,14 @@ u32 x_firmware_ctl_h; u32 x_dsdt_l; u32 x_dsdt_h; - struct acpi_gen_regaddr x_pm1a_evt_blk; - struct acpi_gen_regaddr x_pm1b_evt_blk; - struct acpi_gen_regaddr x_pm1a_cnt_blk; - struct acpi_gen_regaddr x_pm1b_cnt_blk; - struct acpi_gen_regaddr x_pm2_cnt_blk; - struct acpi_gen_regaddr x_pm_tmr_blk; - struct acpi_gen_regaddr x_gpe0_blk; - struct acpi_gen_regaddr x_gpe1_blk; + acpi_addr_t x_pm1a_evt_blk; + acpi_addr_t x_pm1b_evt_blk; + acpi_addr_t x_pm1a_cnt_blk; + acpi_addr_t x_pm1b_cnt_blk; + acpi_addr_t x_pm2_cnt_blk; + acpi_addr_t x_pm_tmr_blk; + acpi_addr_t x_gpe0_blk; + acpi_addr_t x_gpe1_blk; } __packed acpi_fadt_t; /* FADT TABLE Revision values */ @@ -634,8 +634,8 @@ /* ECDT (Embedded Controller Boot Resources Table) */ typedef struct acpi_ecdt { acpi_header_t header; - struct acpi_gen_regaddr ec_control; /* EC control register */ - struct acpi_gen_regaddr ec_data; /* EC data register */ + acpi_addr_t ec_control; /* EC control register */ + acpi_addr_t ec_data; /* EC data register */ u32 uid; /* UID */ u8 gpe_bit; /* GPE bit */ u8 ec_id[]; /* EC ID */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc8413050bfae896d78605416aaaaa6a52eb39f1 Gerrit-Change-Number: 36429 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: vendorcode/eltan/security: start using vb2 public key
by Wim Vervoorn (Code Review) 01 Nov '19

01 Nov '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36480 ) Change subject: vendorcode/eltan/security: start using vb2 public key ...................................................................... vendorcode/eltan/security: start using vb2 public key Start using the vb2 public key format and process the signature verification using the vb2 routines. BUG=N/A TEST=tested on fbg1701 board Change-Id: Id5d28595bbfb1f5ca5bca0fcfb06134bb1143f25 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/vendorcode/eltan/security/verified_boot/Kconfig M src/vendorcode/eltan/security/verified_boot/Makefile.inc M src/vendorcode/eltan/security/verified_boot/vboot_check.c 3 files changed, 100 insertions(+), 123 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36480/1 diff --git a/src/vendorcode/eltan/security/verified_boot/Kconfig b/src/vendorcode/eltan/security/verified_boot/Kconfig index 3177529..d9e989f 100644 --- a/src/vendorcode/eltan/security/verified_boot/Kconfig +++ b/src/vendorcode/eltan/security/verified_boot/Kconfig @@ -55,9 +55,14 @@ depends on VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST default 0xFFFFF500 +config VENDORCODE_ELTAN_VBOOT_KEY_FILE + string "Verified boot Key File" + depends on VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST + default "3rdparty/eltan/verified_boot/Keys/key.vbpubk2" + config VENDORCODE_ELTAN_VBOOT_KEY_SIZE int - default 554 if VENDORCODE_ELTAN_VBOOT_USE_SHA512 - default 520 + default 610 if VENDORCODE_ELTAN_VBOOT_USE_SHA512 + default 576 endmenu # Verified Boot (verified_boot) diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc index 3f6ba90..357e520 100644 --- a/src/vendorcode/eltan/security/verified_boot/Makefile.inc +++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc @@ -37,12 +37,10 @@ ifeq ($(CONFIG_VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST),y) cbfs-files-y += vboot_public_key.bin -vboot_public_key.bin-file := $(obj)/vboot_public_key.bin +vboot_public_key.bin-file := $(call strip_quotes, $(CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_FILE)) vboot_public_key.bin-position := $(CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION) vboot_public_key.bin-type := raw -$(obj)/vboot_public_key.bin: - dd if=/dev/zero of=$@ bs=$(CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_SIZE) count=1 endif # ($(CONFIG_VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST),y) endif # CONFIG_VENDORCODE_ELTAN_VBOOT diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index e2258b9..07c6902 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -23,65 +23,66 @@ #if CONFIG(VENDORCODE_ELTAN_VBOOT_USE_SHA512) #define DIGEST_SIZE VB2_SHA512_DIGEST_SIZE +#define HASH_ALG VB2_HASH_SHA512 #else #define DIGEST_SIZE VB2_SHA256_DIGEST_SIZE +#define HASH_ALG VB2_HASH_SHA256 #endif int verified_boot_check_manifest(void) { - struct vb2_public_key key; - const struct vb2_workbuf wb; uint8_t *buffer; - uint8_t digest[DIGEST_SIZE]; - uint8_t *signature = NULL; + uint8_t sig_buffer[1024]; /* used to build vb21_signature */ size_t size = 0; - int hash_algorithm; - int status; + struct vb2_public_key key; + struct vb2_workbuf wb; + struct vb21_signature *vb2_sig_hdr = (struct vb21_signature *)sig_buffer; + uint8_t wb_buffer[1024]; + + buffer = cbfs_boot_map_with_leak(RSA_PUBLICKEY_FILE_NAME, CBFS_TYPE_RAW, &size); + if (!buffer || !size) { + printk(BIOS_ERR, "ERROR: Public key not found!\n"); + goto fail; + } + + if ((size != CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_SIZE) || + (buffer != (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION)) { + printk(BIOS_ERR, "ERROR: Illegal public key!\n"); + goto fail; + } + + if (vb21_unpack_key(&key, buffer, size)) { + printk(BIOS_ERR, "ERROR: Invalid public key!\n"); + goto fail; + } cbfs_boot_map_with_leak("oemmanifest.bin", CBFS_TYPE_RAW, &size); - - if (size != (CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * - DIGEST_SIZE) + 256) { + if (size != (CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) + + vb2_rsa_sig_size(VB2_SIG_RSA2048)) { printk(BIOS_ERR, "ERROR: Incorrect manifest size!\n"); goto fail; } - buffer = cbfs_boot_map_with_leak(RSA_PUBLICKEY_FILE_NAME, - CBFS_TYPE_RAW, &size); + /* prepare work buffer structure */ + wb.buf = (uint8_t *)&wb_buffer; + wb.size = sizeof(wb_buffer); - size = DIGEST_SIZE; - if (!vb2_unpack_key_data(&key, buffer, size)) { - printk(BIOS_ERR, "ERROR: Unable to create RSA Public Key !\n"); + /* Build vb2_sig_hdr buffer */ + vb2_sig_hdr->sig_offset = sizeof(struct vb21_signature) + + (CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE); + vb2_sig_hdr->sig_alg = VB2_SIG_RSA2048; + vb2_sig_hdr->sig_size = vb2_rsa_sig_size(VB2_SIG_RSA2048); + vb2_sig_hdr->hash_alg = HASH_ALG; + vb2_sig_hdr->data_size = CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE; + memcpy(&sig_buffer[sizeof(struct vb21_signature)], (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC, size); + + if (vb21_verify_data(&sig_buffer[sizeof(struct vb21_signature)], vb2_sig_hdr->data_size, + (struct vb21_signature *)&sig_buffer, &key, &wb)) { + printk(BIOS_ERR, "ERROR: Signature verification failed for hash table\n"); goto fail; } - if (CONFIG(VENDORCODE_ELTAN_VBOOT_USE_SHA512)) { - key.hash_alg = VB2_HASH_SHA512; - hash_algorithm = VB2_HASH_SHA512; - } else { - key.sig_alg = VB2_HASH_SHA256; - hash_algorithm = VB2_HASH_SHA256; - } - - /* Create a big endian digest */ - status = cb_sha_endian(hash_algorithm, - (const uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC, - CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE, - digest, BIG_ENDIAN_ALGORITHM); - if (status) - goto fail; - - signature = (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC + - CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE; - - if (!vb2_rsa_verify_digest(&key, signature, digest, &wb)) { - printk(BIOS_ERR, "ERROR: Signature verification failed for" - "hash table !!\n"); - goto fail; - } - - printk(BIOS_DEBUG, "%s: Successfully verified hash_table signature.\n", - __func__); + printk(BIOS_INFO, "%s: Successfully verified hash_table signature.\n", __func__); return 0; fail: @@ -151,39 +152,32 @@ int8_t *event_msg, TCG_EVENTTYPE eventType) { int status = TPM_SUCCESS; - EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs; TCG_PCR_EVENT2_HDR tcgEventHdr; - ActivePcrs = tpm2_get_active_pcrs(); - memset(&tcgEventHdr, 0, sizeof(tcgEventHdr)); tcgEventHdr.pcrIndex = pcr; tcgEventHdr.eventType = eventType; if (event_msg) { - status = mboot_hash_extend_log(ActivePcrs, MBOOT_HASH_PROVIDED, - hashData, hashDataLen, &tcgEventHdr, - (uint8_t *)event_msg, 0); - if (status == TPM_SUCCESS) { - printk(BIOS_DEBUG, "%s: Success! %s measured to pcr" - "%d.\n", __func__, event_msg, pcr); - } else { - printk(BIOS_DEBUG, "%s: Fail! %s can't be measured. " - "ABORTING!!!\n", __func__, event_msg); - return status; - } + status = mboot_hash_extend_log(MBOOT_HASH_PROVIDED, hashData, + hashDataLen, &tcgEventHdr, + (uint8_t *)event_msg); + if (status == TPM_SUCCESS) + printk(BIOS_INFO, "%s: Success! %s measured to pcr %d.\n", __func__, + event_msg, pcr); } return status; } #endif -static void verified_boot_check_buffer(const char *name, void *start, - size_t size, uint32_t hash_index, int32_t pcr) +static void verified_boot_check_buffer(const char *name, void *start, size_t size, + uint32_t hash_index, int32_t pcr) { uint8_t digest[DIGEST_SIZE]; int hash_algorithm; - int status; - printk(BIOS_DEBUG, "%s: %s HASH verification buffer %p size %d\n", - __func__, name, start, (int) size); + vb2_error_t status; + + printk(BIOS_DEBUG, "%s: %s HASH verification buffer %p size %d\n", __func__, name, + start, (int)size); if (start && size) { if (CONFIG(VENDORCODE_ELTAN_VBOOT_USE_SHA512)) @@ -191,66 +185,51 @@ else hash_algorithm = VB2_HASH_SHA256; - status = cb_sha_endian(hash_algorithm, (const uint8_t *)start, - size, digest, LITTLE_ENDIAN_ALGORITHM); - + status = cb_sha_endian(hash_algorithm, (const uint8_t *)start, size, digest); if ((CONFIG(VENDORCODE_ELTAN_VBOOT) && memcmp((void *)( (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC + - sizeof(digest) * hash_index), digest, sizeof(digest))) || - status) { + sizeof(digest) * hash_index), digest, sizeof(digest))) || status) { printk(BIOS_DEBUG, "%s: buffer hash\n", __func__); hexdump(digest, sizeof(digest)); printk(BIOS_DEBUG, "%s: manifest hash\n", __func__); - hexdump((void *)( - (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC + - sizeof(digest) * hash_index), sizeof(digest)); + hexdump((void *)( (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC + + sizeof(digest) * hash_index), sizeof(digest)); printk(BIOS_EMERG, "%s ", name); die("HASH verification failed!\n"); } else { #ifndef __BOOTBLOCK__ if (CONFIG(VENDORCODE_ELTAN_MBOOT)) { if (pcr != -1) { - printk(BIOS_DEBUG, "%s: measuring %s\n", - __func__, name); - status = measure_item(pcr, digest, - sizeof(digest), - (int8_t *)name, 0); + printk(BIOS_DEBUG, "%s: measuring %s\n", __func__, name); + if (measure_item(pcr, digest, sizeof(digest), + (int8_t *)name, 0)) + printk(BIOS_DEBUG, "%s: measuring failed!\n", __func__); } } #endif if (CONFIG(VENDORCODE_ELTAN_VBOOT)) - printk(BIOS_DEBUG, "%s HASH verification " - "success\n", name); + printk(BIOS_DEBUG, "%s HASH verification success\n", name); } } else { - printk(BIOS_EMERG, "Invalid buffer "); + printk(BIOS_EMERG, "Invalid buffer\n"); die("HASH verification failed!\n"); } } -void verified_boot_check_cbfsfile(const char *name, uint32_t type, - uint32_t hash_index, void **buffer, uint32_t *filesize, - int32_t pcr) +void verified_boot_check_cbfsfile(const char *name, uint32_t type, uint32_t hash_index, + void **buffer, uint32_t *filesize, int32_t pcr) { void *start; size_t size; - start = cbfs_boot_map_with_leak(name, type & ~VERIFIED_BOOT_COPY_BLOCK, - &size); + start = cbfs_boot_map_with_leak(name, type & ~VERIFIED_BOOT_COPY_BLOCK, &size); if (start && size) { - /* - * Speed up processing by copying the file content to memory - * first - */ + /* Speed up processing by copying the file content to memory first */ #ifndef __PRE_RAM__ - if ((type & VERIFIED_BOOT_COPY_BLOCK) && (buffer) && - (*buffer) && + if ((type & VERIFIED_BOOT_COPY_BLOCK) && (buffer) && (*buffer) && ((uint32_t) start > (uint32_t)(~(CONFIG_CBFS_SIZE-1)))) { - printk(BIOS_DEBUG, "%s: move buffer to " - "memory\n", __func__); - /* Move the file to a memory bufferof which we know it - * doesn't harm - */ + printk(BIOS_DEBUG, "%s: move buffer to memory\n", __func__); + /* Move the file to a memory bufferof which we know it doesn't harm */ memcpy(*buffer, start, size); start = *buffer; printk(BIOS_DEBUG, "%s: done\n", __func__); @@ -258,8 +237,7 @@ #endif // __PRE_RAM__ verified_boot_check_buffer(name, start, size, hash_index, pcr); } else { - printk(BIOS_EMERG, "CBFS Failed to get file content for %s\n", - name); + printk(BIOS_EMERG, "CBFS Failed to get file content for %s\n", name); die("HASH verification failed!\n"); } if (buffer) @@ -275,25 +253,22 @@ while (list[i].type != VERIFY_TERMINATOR) { switch (list[i].type) { case VERIFY_FILE: - verified_boot_check_cbfsfile(list[i].name, - list[i].data.file.cbfs_type, - list[i].hash_index, NULL, NULL, - list[i].pcr); + verified_boot_check_cbfsfile(list[i].name, list[i].data.file.cbfs_type, + list[i].hash_index, NULL, NULL, list[i].pcr); if (list[i].data.file.related_items) { printk(BIOS_SPEW, "process related items\n"); - process_verify_list((verify_item_t *) - list[i].data.file.related_items); + process_verify_list( + (verify_item_t *)list[i].data.file.related_items); } break; case VERIFY_BLOCK: verified_boot_check_buffer(list[i].name, - (void *) list[i].data.block.start, - list[i].data.block.size, - list[i].hash_index, list[i].pcr); + (void *)list[i].data.block.start, + list[i].data.block.size, + list[i].hash_index, list[i].pcr); break; default: - printk(BIOS_EMERG, "INVALID TYPE IN VERIFY" - "LIST 0x%x\n", list[i].type); + printk(BIOS_EMERG, "INVALID TYPE IN VERIFY LIST 0x%x\n", list[i].type); die("HASH verification failed!\n"); } i++; @@ -392,9 +367,8 @@ uint32_t viddevid = 0; if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) { - printk(BIOS_ERR, "Incorrect expansion ROM header " - "signature %04x DONT START\n", - le32_to_cpu(rom_header->signature)); + printk(BIOS_ERR, "Incorrect expansion ROM header signature %04x DONT START\n", + le32_to_cpu(rom_header->signature)); return 0; } @@ -408,22 +382,22 @@ case VERIFY_OPROM: if (viddevid == list[i].data.oprom.viddev) { verified_boot_check_buffer(list[i].name, - (void *) rom_header, - rom_header->size * 512, - list[i].hash_index, list[i].pcr); + (void *)rom_header, + rom_header->size * 512, + list[i].hash_index, list[i].pcr); if (list[i].data.oprom.related_items) { - printk(BIOS_SPEW, "%s: process" - " related items\n", __func__); - process_verify_list((verify_item_t *)list[i].data.oprom.related_items); + printk(BIOS_SPEW, "%s: process related items\n", + __func__); + process_verify_list( + (verify_item_t *)list[i].data.oprom.related_items); } - printk(BIOS_SPEW, "%s: option rom can be" - " started\n", __func__); + printk(BIOS_SPEW, "%s: option rom can be started\n", __func__); return 1; } break; default: - printk(BIOS_EMERG, "%s: INVALID TYPE IN OPTION ROM LIST" - "0x%x\n", __func__, list[i].type); + printk(BIOS_EMERG, "%s: INVALID TYPE IN OPTION ROM LIST 0x%x\n", + __func__, list[i].type); die("HASH verification failed!\n"); } i++; -- To view, visit https://review.coreboot.org/c/coreboot/+/36480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d28595bbfb1f5ca5bca0fcfb06134bb1143f25 Gerrit-Change-Number: 36480 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kukui: Unselect FATAL_ASSERT
by HAOUAS Elyes (Code Review) 01 Nov '19

01 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36508 ) Change subject: mb/google/kukui: Unselect FATAL_ASSERT ...................................................................... mb/google/kukui: Unselect FATAL_ASSERT FATAL_ASSERT is used for debugging purpos. Don't select it by default. Change-Id: If4d521827f3d50fb662b89b24d00fb0517e7af2d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/kukui/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/36508/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 542ee10..e6d604e 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -32,7 +32,6 @@ select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH - select FATAL_ASSERTS select SPI_FLASH_INCLUDE_ALL_DRIVERS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID -- To view, visit https://review.coreboot.org/c/coreboot/+/36508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4d521827f3d50fb662b89b24d00fb0517e7af2d Gerrit-Change-Number: 36508 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: lib/cbmem_top: Add a common cbmem_top implementation
by Arthur Heymans (Code Review) 01 Nov '19

01 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36273 ) Change subject: lib/cbmem_top: Add a common cbmem_top implementation ...................................................................... lib/cbmem_top: Add a common cbmem_top implementation This adds a common cbmem_top implementation to be used by all coreboot target. To ease the review process it is currently guarded by a Kconfig symbol to be able to make transition platforms/arch step by step. To avoid a lot of preprocessor and/or changing file inclusion all current cbmem_top implementations will be renamed cbmem_top_romstage and called by the common cbmem_top function. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/cbmem.h M src/lib/Kconfig M src/lib/Makefile.inc A src/lib/cbmem_top.c 4 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/36273/1 diff --git a/src/include/cbmem.h b/src/include/cbmem.h index f972ba6..a6cd277 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -74,7 +74,9 @@ * upper limit. * x86 boards or chipsets must return NULL before the cbmem backing store has * been initialized. */ +extern uintptr_t _cbmem_top_ptr; void *cbmem_top(void); +void *cbmem_top_romstage(void); /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original diff --git a/src/lib/Kconfig b/src/lib/Kconfig index cb1e4a5..aede4b3 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -24,6 +24,12 @@ help Selected by features that require `libhwbase` in ramstage. +config RAMSTAGE_CBMEM_TOP_ARG + bool + help + Select this if stages run after romstage get the cbmem_top + pointer the function arguments when called from romstage. + config FLATTENED_DEVICE_TREE bool help diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e5678ff..0c569c5 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -149,6 +149,7 @@ ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c +romstage-$(CONFIG_RAMSTAGE_CBMEM_TOP_ARG) += cbmem_top.c romstage-y += cbmem_common.c romstage-y += imd_cbmem.c romstage-y += imd.c diff --git a/src/lib/cbmem_top.c b/src/lib/cbmem_top.c new file mode 100644 index 0000000..6eee0d5 --- /dev/null +++ b/src/lib/cbmem_top.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +#if !ENV_ROMSTAGE +void *cbmem_top(void) +{ + return (void *)_cbmem_top_ptr; +} +#else +void *cbmem_top(void) +{ + /* TODO use a static variable once NO_CAR_GLOBAL_MIGRATION + is implemented */ + return cbmem_top_romstage(); +} + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Gerrit-Change-Number: 36273 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019