November 2019 - coreboot-gerrit

Change in coreboot[master]: timestamps: COLLECT_TIMESTAMPS is always optional
by Arthur Heymans (Code Review) Nov. 1, 2019

Nov. 1, 2019

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36527 ) Change subject: timestamps: COLLECT_TIMESTAMPS is always optional ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ee4195d266440143344781d39db9578cd8bdcb3 Gerrit-Change-Number: 36527 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Nov 2019 07:59:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/tsc: Replace TSC_CONSTANT_RATE with UNKNOWN_TSC_RATE
by Arthur Heymans (Code Review) Nov. 1, 2019

Nov. 1, 2019

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33928 ) Change subject: cpu/x86/tsc: Replace TSC_CONSTANT_RATE with UNKNOWN_TSC_RATE ...................................................................... Patch Set 12: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/33928/12//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/33928/12//COMMIT_MSG@15 PS12, Line 15: For via/epia-m850, switch romstage udelay() from UDELAY_IO to : UDELAY_TSC. Should we wait for the next release? I think the via platform will be dropped. -- To view, visit https://review.coreboot.org/c/coreboot/+/33928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Gerrit-Change-Number: 33928 Gerrit-PatchSet: 12 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Nov 2019 07:58:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: timestamps: COLLECT_TIMESTAMPS is always optional
by HAOUAS Elyes (Code Review) Nov. 1, 2019

Nov. 1, 2019

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36527 ) Change subject: timestamps: COLLECT_TIMESTAMPS is always optional ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ee4195d266440143344781d39db9578cd8bdcb3 Gerrit-Change-Number: 36527 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Nov 2019 07:35:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/intel/pineview: Use defined DEFAULT_RCBA
by HAOUAS Elyes (Code Review) Nov. 1, 2019

Nov. 1, 2019

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36477 ) Change subject: nb/intel/pineview: Use defined DEFAULT_RCBA ...................................................................... Abandoned see https://review.coreboot.org/c/coreboot/+/36464 -- To view, visit https://review.coreboot.org/c/coreboot/+/36477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabf015411ac722d05591d4b11f6189a9a0215231 Gerrit-Change-Number: 36477 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: nb/intel/nehalem: Use defined DEFAULT_RCBA
by HAOUAS Elyes (Code Review) Nov. 1, 2019

Nov. 1, 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36476 ) Change subject: nb/intel/nehalem: Use defined DEFAULT_RCBA ...................................................................... nb/intel/nehalem: Use defined DEFAULT_RCBA Change-Id: I163eb268a0d7ad75b6c286d76fbe77ea36dc58d8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/nehalem/acpi/nehalem.asl 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/36476/1 diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl index df8aad7..404801e 100644 --- a/src/northbridge/intel/nehalem/acpi/nehalem.asl +++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl @@ -16,6 +16,7 @@ #include "../nehalem.h" #include "hostbridge.asl" +#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -24,7 +25,7 @@ Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) -- To view, visit https://review.coreboot.org/c/coreboot/+/36476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I163eb268a0d7ad75b6c286d76fbe77ea36dc58d8 Gerrit-Change-Number: 36476 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: nb/intel/haswell: Use defined DEFAULT_RCBA
by HAOUAS Elyes (Code Review) Nov. 1, 2019

Nov. 1, 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36475 ) Change subject: nb/intel/haswell: Use defined DEFAULT_RCBA ...................................................................... nb/intel/haswell: Use defined DEFAULT_RCBA Change-Id: Id405ac4943618f43d0f2e4b726019915f144cdff Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/haswell/acpi/haswell.asl 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/36475/1 diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 0f0d383..45ebff2 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -16,6 +16,7 @@ #include "../haswell.h" #include "hostbridge.asl" +#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -24,7 +25,7 @@ Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) -- To view, visit https://review.coreboot.org/c/coreboot/+/36475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id405ac4943618f43d0f2e4b726019915f144cdff Gerrit-Change-Number: 36475 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: nb/intel/gm45: Use defined DEFAULT_RCBA
by HAOUAS Elyes (Code Review) Nov. 1, 2019

Nov. 1, 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36474 ) Change subject: nb/intel/gm45: Use defined DEFAULT_RCBA ...................................................................... nb/intel/gm45: Use defined DEFAULT_RCBA Change-Id: I721c0082668c6f6f942e989cd1c4d0f505b946f6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/acpi/gm45.asl 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/36474/1 diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 4678e1f..a3f9e90 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -16,6 +16,7 @@ #include "hostbridge.asl" #include "../gm45.h" +#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -36,7 +37,7 @@ //}) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) -- To view, visit https://review.coreboot.org/c/coreboot/+/36474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I721c0082668c6f6f942e989cd1c4d0f505b946f6 Gerrit-Change-Number: 36474 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel: Use CONFIG_HPET_ADDRESS value
by HAOUAS Elyes (Code Review) Nov. 1, 2019

Nov. 1, 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36468 ) Change subject: soc/intel: Use CONFIG_HPET_ADDRESS value ...................................................................... soc/intel: Use CONFIG_HPET_ADDRESS value Change-Id: I50dacf7fe395788b3db719740888bf14da74d8f8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/baytrail/acpi/lpc.asl M src/soc/intel/braswell/acpi/lpc.asl M src/soc/intel/broadwell/acpi/lpc.asl M src/soc/intel/fsp_baytrail/acpi/lpc.asl M src/soc/intel/fsp_broadwell_de/acpi/lpc.asl 5 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/36468/1 diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 00aac51..7cdf1aa 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -59,7 +59,7 @@ Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) }) } diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 9caa8f1..a8604d6 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -71,7 +71,7 @@ Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) }) } #endif diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl index 70dd6e5..ca44c5c 100644 --- a/src/soc/intel/broadwell/acpi/lpc.asl +++ b/src/soc/intel/broadwell/acpi/lpc.asl @@ -74,7 +74,7 @@ Name (BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -99,15 +99,15 @@ \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) } If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } } diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl index 00aac51..7cdf1aa 100644 --- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl +++ b/src/soc/intel/fsp_baytrail/acpi/lpc.asl @@ -59,7 +59,7 @@ Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) }) } diff --git a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl index 6a7a2f1..ef1e655 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl +++ b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl @@ -44,7 +44,7 @@ Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) }) } -- To view, visit https://review.coreboot.org/c/coreboot/+/36468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50dacf7fe395788b3db719740888bf14da74d8f8 Gerrit-Change-Number: 36468 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: sb/intel/bd82x6x: Use CONFIG_HPET_ADDRESS value
by HAOUAS Elyes (Code Review) Nov. 1, 2019

Nov. 1, 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36469 ) Change subject: sb/intel/bd82x6x: Use CONFIG_HPET_ADDRESS value ...................................................................... sb/intel/bd82x6x: Use CONFIG_HPET_ADDRESS value Change-Id: I78a2a3ed76e0596c2ef7b989aea6b43209cfbd8a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/acpi/lpc.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/36469/1 diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl index 5204b29..06c9ada 100644 --- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -97,7 +97,7 @@ Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -120,15 +120,15 @@ If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) } If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/36469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78a2a3ed76e0596c2ef7b989aea6b43209cfbd8a Gerrit-Change-Number: 36469 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: sb/intel/fsp_rangeley: Use CONFIG_HPET_ADDRESS value
by HAOUAS Elyes (Code Review) Nov. 1, 2019

Nov. 1, 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36470 ) Change subject: sb/intel/fsp_rangeley: Use CONFIG_HPET_ADDRESS value ...................................................................... sb/intel/fsp_rangeley: Use CONFIG_HPET_ADDRESS value Change-Id: I24df64054fc71a2494670f28653ac78a6c4786ae Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/fsp_rangeley/acpi/lpc.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/36470/1 diff --git a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl b/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl index b53e98f..a896dad 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl @@ -97,7 +97,7 @@ Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -120,15 +120,15 @@ If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) } If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/36470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24df64054fc71a2494670f28653ac78a6c4786ae Gerrit-Change-Number: 36470 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2