Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36541 )
Change subject: [TEST] test CB:36444
......................................................................
Patch Set 1:
This change is ready for review.
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Change subject: device/Kconfig: hide display menu when NO_GFX_INIT is selected
......................................................................
Uploaded patch set 3.
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Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36444
to look at the new patch set (#3).
Change subject: device/Kconfig: hide display menu when NO_GFX_INIT is selected
......................................................................
device/Kconfig: hide display menu when NO_GFX_INIT is selected
Hide display menu when NO_GFX_INIT is selected.
This also adds a config to make Jenkins test this.
Change-Id: Iec5a47f84b8c776a45edc6f4b31a03b9ac714b4e
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
A configs/config.no_gfx_init
M src/device/Kconfig
2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/36444/3
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 )
Change subject: soc/intel/tigerlake: Do initial SoC commit
......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/M…
File src/soc/intel/tigerlake/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/M…
PS10, Line 1: feq ($(CONFIG_SOC_INTEL_TIGERLAKE),y)
> > Don't understand your feedback here Arthur. Do you mean that we can remove this guard ? […]
Thanks and this is great.
btw, do you want me to use alt from ICL or lets start using the same from TGL ?
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 )
Change subject: soc/intel/tigerlake: Do initial SoC commit
......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/M…
File src/soc/intel/tigerlake/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/M…
PS10, Line 1: feq ($(CONFIG_SOC_INTEL_TIGERLAKE),y)
> Don't understand your feedback here Arthur. Do you mean that we can remove this guard ?
Oh sry. This was meant for the whole file. If you have:
bootblock-y += somefile.c
verstage-y += somefile.c
romstage-y += somefile.c
postcar-y += somefile.c
ramstage-y += somefile.c
It can now be done with:
all-y += somefile.c
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Change subject: soc/intel/tigerlake: Do initial SoC commit
......................................................................
Patch Set 10:
(7 comments)
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/K…
File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/K…
PS10, Line 73: FSP_USES_CB_STACK
> PLATFORM_USES_FSP2_1 indirectly selects this. You might want to drop the dependency.
Done
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/M…
File src/soc/intel/tigerlake/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/M…
PS10, Line 1: feq ($(CONFIG_SOC_INTEL_TIGERLAKE),y)
> There is now an 'all' class to link code in bootblock,verstage,romstage,postcar,ramstage. […]
Don't understand your feedback here Arthur. Do you mean that we can remove this guard ?
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i…
File src/soc/intel/tigerlake/include/soc/bootblock.h:
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i…
PS10, Line 18:
: #include <intelblocks/systemagent.h>
> Don't include it here but in the file implementing the callbacks below.
Done
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i…
File src/soc/intel/tigerlake/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i…
PS10, Line 18:
: #include <device/device.h>
: #include <intelblocks/msr.h>
> unused here. Include this in the file defining the function.
removed unused
#include <device/device.h>
and#include <intelblocks/msr.h> used here for IRTL_1024_NS so can't move
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i…
PS10, Line 21:
: /* Latency times in units of 32768ns */
: #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d
: #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d
: #define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d
: #define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d
: #define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d
: #define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d
:
: /* Power in units of mW */
: #define C1_POWER 0x3e8
: #define C6_POWER 0x15e
: #define C7_POWER 0xc8
: #define C8_POWER 0xc8
: #define C9_POWER 0xc8
: #define C10_POWER 0xc8
:
: /* Common Timer Copy (CTC) frequency - 38.4MHz. */
: #define CTC_FREQ 38400000
:
: #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
: (((1 << ((base)*5)) * (limit)) / 1000)
: #define C_STATE_LATENCY_FROM_LAT_REG(reg) \
: C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
: (IRTL_1024_NS >> 10))
> Is this used in multiple files? If not better move this inside the compilation unit defining the fun […]
getting also used from acpi.c hence keeping it here
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i…
File src/soc/intel/tigerlake/include/soc/ebda.h:
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i…
PS10, Line 21: struct ebda_config {
: uint32_t signature; /* 0x00 - EBDA signature */
: uint32_t tolum_base; /* 0x04 - coreboot memory start */
: uint32_t reserved_mem_size; /* 0x08 - chipset reserved memory size */
: };
> note: we might get rid of this soon: CB:36362
Sure will remove from TGL copy CL
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i…
File src/soc/intel/tigerlake/include/soc/espi.h:
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i…
PS10, Line 19: #include <stdint.h>
> not needed here?
Done
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36444 )
Change subject: device/Kconfig: hide display menu when NO_GFX_INIT is selected
......................................................................
Patch Set 2:
> > Hmmm, it doesn't have the anticipated effect :-/ I would have
> > expected a Verified -1, because aspeed/ isn't fixed yet. But
> > the error is only triggered with NO_GFX_INIT in the config and
> > that's not the default... I guess there is nothing we can do?
>
> I guess no (without adding some "CONFIG_JENKINS_TEST" or whatever) :S
Hah, we already have that in a way. I just keep forgetting about it. Just
add a config file to configs/... e.g. configs/no-gfx-init
CONFIG_VENDOR_LENOVO=y
CONFIG_NO_GFX_INIT=y
should do the trick, I guess.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 )
Change subject: soc/intel/tigerlake: Do initial SoC commit
......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/g…
File src/soc/intel/tigerlake/graphics.c:
https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/g…
PS10, Line 53: /*
: * GFX PEIM module inside FSP binary is taking care of graphics
: * initialization based on INTEL_GMA_ADD_VBT Kconfig
: * option and input VBT file. Hence no need to load/execute legacy VGA
: * OpROM in order to initialize GFX.
: *
: * In case of non-FSP solution, SoC need to select VGA_ROM_RUN
: * Kconfig to perform GFX initialization through VGA OpRom.
: */
: if (CONFIG(INTEL_GMA_ADD_VBT))
: return;
> This seems like a bad idea to use a Kconfig option to do something that it is not meant for. […]
Done
https://review.coreboot.org/c/coreboot/+/36532
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36225 )
Change subject: soc/intel/common: Include Tigerlake device IDs
......................................................................
Patch Set 6:
can you please rebase this CL alone
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