coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

1 participants
2418 discussions

Change in coreboot[master]: mb/facebook/fbg1701: Add public key to verification
by Wim Vervoorn (Code Review) 01 Nov '19

01 Nov '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36504 ) Change subject: mb/facebook/fbg1701: Add public key to verification ...................................................................... mb/facebook/fbg1701: Add public key to verification The public key was not verified during the verfied boot operation. This is now added. The key is measured to PCR0. BUG=N/A TEST=tested on facebook fbg1701 Change-Id: I85fd391294db0ea796001720c2509f797be5aedf Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/board_verified_boot.c M src/mainboard/facebook/fbg1701/manifest.h M src/vendorcode/eltan/security/verified_boot/Kconfig 3 files changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/36504/1 diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index 24e7037..1ccb0b8e 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -26,6 +26,10 @@ { { (void *)0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE, } }, HASH_IDX_BOOTBLOCK, MBOOT_PCR_INDEX_0 }, + { VERIFY_BLOCK, "PublicKey", + { { (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION, + CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_SIZE, } }, HASH_IDX_PUBLICKEY, + MBOOT_PCR_INDEX_0 }, { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; #endif diff --git a/src/mainboard/facebook/fbg1701/manifest.h b/src/mainboard/facebook/fbg1701/manifest.h index 5a583f4..5fa86ed 100644 --- a/src/mainboard/facebook/fbg1701/manifest.h +++ b/src/mainboard/facebook/fbg1701/manifest.h @@ -30,6 +30,6 @@ #define HASH_IDX_LOGO 7 #define HASH_IDX_DSDT 8 #define HASH_IDX_POSTCAR_STAGE 9 -#define HASH_IDX_BOOTBLOCK 10 /* Should always be the last one */ - +#define HASH_IDX_PUBLICKEY 10 +#define HASH_IDX_BOOTBLOCK 11 /* Should always be the last one */ #endif diff --git a/src/vendorcode/eltan/security/verified_boot/Kconfig b/src/vendorcode/eltan/security/verified_boot/Kconfig index d9e989f..ab254c4 100644 --- a/src/vendorcode/eltan/security/verified_boot/Kconfig +++ b/src/vendorcode/eltan/security/verified_boot/Kconfig @@ -42,8 +42,7 @@ config VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS int "Manifest Items" - default 11 if POSTCAR_STAGE - default 10 + default 12 config VENDORCODE_ELTAN_OEM_MANIFEST_ITEM_SIZE int -- To view, visit https://review.coreboot.org/c/coreboot/+/36504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85fd391294db0ea796001720c2509f797be5aedf Gerrit-Change-Number: 36504 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage
by Subrata Banik (Code Review) 01 Nov '19

01 Nov '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage ...................................................................... Patch Set 12: I have divided this CL into possible logic groups as https://review.coreboot.org/q/topic:%22TGL_UPSTREAM%22+(status:open%20OR%20… Kindly help to review. Also this CL is based on all clean up been done so far with https://review.coreboot.org/q/topic:%22ICL_CLEAN_UP_FOR_TGL_UPSTREAM%22+(st… Thanks to all reviewer so far helping to clean ICL code in order to create soc/intel/tigerlake copy CL as mentioned above. -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 12 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Nov 2019 13:13:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage
by Subrata Banik (Code Review) 01 Nov '19

01 Nov '19

Subrata Banik has uploaded a new patch set (#12) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage ...................................................................... soc/intel/tigerlake: Do initial SoC commit till ramstage Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 5.c Remove dGPU over PCIE enable Kconfig option 6. Add CPU/PCH/SA EDS docuemnt number and chapter number Tiger Lake specific changes will follow in subsequent patches. 1. Include GPIO controller delta over ICL 2. FSP-S related UPD overrides as applicable "The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware." Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/tigerlake/Kconfig A src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/acpi.c A src/soc/intel/tigerlake/chip.c A src/soc/intel/tigerlake/chip.h A src/soc/intel/tigerlake/cpu.c A src/soc/intel/tigerlake/elog.c A src/soc/intel/tigerlake/espi.c A src/soc/intel/tigerlake/finalize.c A src/soc/intel/tigerlake/fsp_params.c A src/soc/intel/tigerlake/gpio.c A src/soc/intel/tigerlake/graphics.c A src/soc/intel/tigerlake/gspi.c A src/soc/intel/tigerlake/i2c.c A src/soc/intel/tigerlake/lockdown.c A src/soc/intel/tigerlake/memmap.c A src/soc/intel/tigerlake/p2sb.c A src/soc/intel/tigerlake/pmc.c A src/soc/intel/tigerlake/pmutil.c A src/soc/intel/tigerlake/reset.c A src/soc/intel/tigerlake/sd.c A src/soc/intel/tigerlake/smihandler.c A src/soc/intel/tigerlake/smmrelocate.c A src/soc/intel/tigerlake/spi.c A src/soc/intel/tigerlake/systemagent.c A src/soc/intel/tigerlake/uart.c 26 files changed, 3,638 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/36087/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 12 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit
by build bot (Jenkins) (Code Review) 01 Nov '19

01 Nov '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit ...................................................................... Patch Set 11: (2 comments) https://review.coreboot.org/c/coreboot/+/36087/11/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/ramstage.h: https://review.coreboot.org/c/coreboot/+/36087/11/src/soc/intel/tigerlake/i… PS11, Line 24: void mainboard_silicon_init_params(FSP_S_CONFIG *params); need consistent spacing around '*' (ctx:WxV) https://review.coreboot.org/c/coreboot/+/36087/11/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/romstage.h: https://review.coreboot.org/c/coreboot/+/36087/11/src/soc/intel/tigerlake/i… PS11, Line 21: void mainboard_memory_init_params(FSPM_UPD *mupd); need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 11 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Nov 2019 12:38:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit
by Subrata Banik (Code Review) 01 Nov '19

01 Nov '19

Subrata Banik has uploaded a new patch set (#11) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit ...................................................................... soc/intel/tigerlake: Do initial SoC commit Clone entirely from Icelake TOT commit: 7d9d63b79f331d6a9c613bce03d6e09ef8745bbe List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 5.c Remove dGPU over PCIE enable Kconfig option 6. Add CPU/PCH/SA EDS docuemnt number and chapter number Tiger Lake specific changes will follow in subsequent patches. "The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware." Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/tigerlake/Kconfig A src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/acpi.c A src/soc/intel/tigerlake/acpi/gpio.asl A src/soc/intel/tigerlake/acpi/northbridge.asl A src/soc/intel/tigerlake/acpi/pch_glan.asl A src/soc/intel/tigerlake/acpi/pch_hda.asl A src/soc/intel/tigerlake/acpi/pci_irqs.asl A src/soc/intel/tigerlake/acpi/pcie.asl A src/soc/intel/tigerlake/acpi/platform.asl A src/soc/intel/tigerlake/acpi/scs.asl A src/soc/intel/tigerlake/acpi/serialio.asl A src/soc/intel/tigerlake/acpi/smbus.asl A src/soc/intel/tigerlake/acpi/southbridge.asl A src/soc/intel/tigerlake/acpi/xhci.asl A src/soc/intel/tigerlake/bootblock/bootblock.c A src/soc/intel/tigerlake/bootblock/cpu.c A src/soc/intel/tigerlake/bootblock/pch.c A src/soc/intel/tigerlake/bootblock/report_platform.c A src/soc/intel/tigerlake/chip.c A src/soc/intel/tigerlake/chip.h A src/soc/intel/tigerlake/cpu.c A src/soc/intel/tigerlake/elog.c A src/soc/intel/tigerlake/espi.c A src/soc/intel/tigerlake/finalize.c A src/soc/intel/tigerlake/fsp_params.c A src/soc/intel/tigerlake/gpio.c A src/soc/intel/tigerlake/graphics.c A src/soc/intel/tigerlake/gspi.c A src/soc/intel/tigerlake/i2c.c A src/soc/intel/tigerlake/include/soc/bootblock.h A src/soc/intel/tigerlake/include/soc/cpu.h A src/soc/intel/tigerlake/include/soc/ebda.h A src/soc/intel/tigerlake/include/soc/espi.h A src/soc/intel/tigerlake/include/soc/gpe.h A src/soc/intel/tigerlake/include/soc/gpio.h A src/soc/intel/tigerlake/include/soc/gpio_defs.h A src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h A src/soc/intel/tigerlake/include/soc/iomap.h A src/soc/intel/tigerlake/include/soc/irq.h A src/soc/intel/tigerlake/include/soc/itss.h A src/soc/intel/tigerlake/include/soc/msr.h A src/soc/intel/tigerlake/include/soc/nvs.h A src/soc/intel/tigerlake/include/soc/p2sb.h A src/soc/intel/tigerlake/include/soc/pch.h A src/soc/intel/tigerlake/include/soc/pci_devs.h A src/soc/intel/tigerlake/include/soc/pcr_ids.h A src/soc/intel/tigerlake/include/soc/pm.h A src/soc/intel/tigerlake/include/soc/pmc.h A src/soc/intel/tigerlake/include/soc/ramstage.h A src/soc/intel/tigerlake/include/soc/romstage.h A src/soc/intel/tigerlake/include/soc/serialio.h A src/soc/intel/tigerlake/include/soc/smbus.h A src/soc/intel/tigerlake/include/soc/smm.h A src/soc/intel/tigerlake/include/soc/soc_chip.h A src/soc/intel/tigerlake/include/soc/systemagent.h A src/soc/intel/tigerlake/include/soc/usb.h A src/soc/intel/tigerlake/lockdown.c A src/soc/intel/tigerlake/memmap.c A src/soc/intel/tigerlake/p2sb.c A src/soc/intel/tigerlake/pmc.c A src/soc/intel/tigerlake/pmutil.c A src/soc/intel/tigerlake/reset.c A src/soc/intel/tigerlake/romstage/Makefile.inc A src/soc/intel/tigerlake/romstage/fsp_params.c A src/soc/intel/tigerlake/romstage/romstage.c A src/soc/intel/tigerlake/romstage/systemagent.c A src/soc/intel/tigerlake/sd.c A src/soc/intel/tigerlake/smihandler.c A src/soc/intel/tigerlake/smmrelocate.c A src/soc/intel/tigerlake/spi.c A src/soc/intel/tigerlake/systemagent.c A src/soc/intel/tigerlake/uart.c 73 files changed, 8,099 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/36087/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 11 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: src/Kconfig: Drop unused HAVE_POSTCAR
by HAOUAS Elyes (Code Review) 01 Nov '19

01 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36497 ) Change subject: src/Kconfig: Drop unused HAVE_POSTCAR ...................................................................... src/Kconfig: Drop unused HAVE_POSTCAR Change-Id: Id8dcba8e83b0f896c26ab684d857908c6f272453 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/Kconfig 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/36497/1 diff --git a/src/Kconfig b/src/Kconfig index 4c71f28..2b41ff2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1229,11 +1229,6 @@ bool default y -config HAVE_POSTCAR - bool - depends on POSTCAR_STAGE - default y - config HAVE_RAMSTAGE bool default n if RAMPAYLOAD -- To view, visit https://review.coreboot.org/c/coreboot/+/36497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8dcba8e83b0f896c26ab684d857908c6f272453 Gerrit-Change-Number: 36497 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: console/kconfig: Move ONBOARD_VGA_IS_PRIMARY to 'devices'
by Arthur Heymans (Code Review) 01 Nov '19

01 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32042 Change subject: console/kconfig: Move ONBOARD_VGA_IS_PRIMARY to 'devices' ...................................................................... console/kconfig: Move ONBOARD_VGA_IS_PRIMARY to 'devices' This has nothing to do with console options. This also improves the help text to reflect what it actually does. Change-Id: I039f4f6bbe144769d6a362192b225838ed3d9d43 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/console/Kconfig M src/device/Kconfig 2 files changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32042/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index 61ba667..fb87e67 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -176,13 +176,6 @@ # TODO: Deps? # TODO: Improve description. -config ONBOARD_VGA_IS_PRIMARY - bool "Use onboard VGA as primary video device" - default n - depends on PCI - help - If not selected, the last adapter found will be used. - config CONSOLE_NE2K bool "Network console over NE2000 compatible Ethernet adapter" default n diff --git a/src/device/Kconfig b/src/device/Kconfig index 8001b43..2da12bc 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -683,4 +683,14 @@ I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. +config ONBOARD_VGA_IS_PRIMARY + bool "Use onboard VGA as primary video device" + default n + depends on PCI + help + This option lets you select which VGA device will be used + to decode legacy VGA cycles. Not all chipsets implement this + however. If not selected, the last adapter found will be used, + else the onboard adapter is used. + endmenu -- To view, visit https://review.coreboot.org/c/coreboot/+/32042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I039f4f6bbe144769d6a362192b225838ed3d9d43 Gerrit-Change-Number: 32042 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mb/apple/macbook21: Use DEBUG_RAM_SETUP
by HAOUAS Elyes (Code Review) 01 Nov '19

01 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36496 ) Change subject: mb/apple/macbook21: Use DEBUG_RAM_SETUP ...................................................................... mb/apple/macbook21: Use DEBUG_RAM_SETUP Also, the loglevel is never set to value of > 8. Change-Id: Ief29e07be6ac075956bf0f9aee85b14eb89af44c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/36496/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index ee5ba80..34cd378 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -226,9 +226,8 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : 0, spd_addrmap); -- To view, visit https://review.coreboot.org/c/coreboot/+/36496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief29e07be6ac075956bf0f9aee85b14eb89af44c Gerrit-Change-Number: 36496 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: mb/facebook/fbg1701: Remove confusing text boxes from menu
by Wim Vervoorn (Code Review) 01 Nov '19

01 Nov '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36481 ) Change subject: mb/facebook/fbg1701: Remove confusing text boxes from menu ...................................................................... mb/facebook/fbg1701: Remove confusing text boxes from menu The Kconfig contained some items that were only intended to set a default and that now were displayed in two locations in the menuconfig. BUG=N/A TEST=build Change-Id: If5d9c993c03a0e901fd6c2a2107a6be6b94d063b Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/36481/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index a607705..e80b7fe 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -73,7 +73,7 @@ default n config VENDORCODE_ELTAN_OEM_MANIFEST_LOC - hex "OEM Manifest working dflt" + hex default 0xFFFE9000 config SPI_FLASH_INCLUDE_ALL_DRIVERS @@ -101,7 +101,7 @@ default "mainboard/facebook/fbg1701/manifest.h" config VENDORCODE_ELTAN_VBOOT_KEY_LOCATION - hex "Key Location working dflt" + hex default 0xFFFF9C00 endif # BOARD_FACEBOOK_FBG1701 -- To view, visit https://review.coreboot.org/c/coreboot/+/36481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5d9c993c03a0e901fd6c2a2107a6be6b94d063b Gerrit-Change-Number: 36481 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/drallion: Add second touch pad support
by EricR Lai (Code Review) 01 Nov '19

01 Nov '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36501 ) Change subject: mb/google/drallion: Add second touch pad support ...................................................................... mb/google/drallion: Add second touch pad support Add second source touch pad with i2c address 0x15. BUG=b:142629138 BRANCH=N/A TEST=check new touch pad can work properly Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Icc58dbcf307f11c368a1a5408f32111ed5841d39 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/36501/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 1f628d6..0de2e94 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -373,6 +373,13 @@ register "probed" = "1" device i2c 2c on end end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "probed" = "1" + device i2c 15 on end + end end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 -- To view, visit https://review.coreboot.org/c/coreboot/+/36501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc58dbcf307f11c368a1a5408f32111ed5841d39 Gerrit-Change-Number: 36501 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 4

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2019