Change in coreboot[master]: mb/portwell/m107: Add rev 1.3
Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36502 ) Change subject: mb/portwell/m107: Add rev 1.3 ...................................................................... mb/portwell/m107: Add rev 1.3 Add support for board revision 1.3 containing Kingston memory. BUG=N/A TEST=tested on portwell m107 module Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> --- M Documentation/mainboard/portwell/pq7-m107.md M src/mainboard/portwell/m107/Kconfig M src/mainboard/portwell/m107/Makefile.inc M src/mainboard/portwell/m107/romstage.c A src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex 5 files changed, 272 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/36502/1 diff --git a/Documentation/mainboard/portwell/pq7-m107.md b/Documentation/mainboard/portwell/pq7-m107.md index e4da415..71bd26a 100644 --- a/Documentation/mainboard/portwell/pq7-m107.md +++ b/Documentation/mainboard/portwell/pq7-m107.md @@ -4,9 +4,10 @@ PQ7-M107 are assembled with different onboard memory modules: Rev 1.0 Onboard Samsung K4B8G1646D-MYKO memory - Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory + Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory + Rev 1.3 Onboard Kingston B5116ECMDXGGB memory -Use 'make menuconfig' to configure `onboard memory manufacture` in Mainboard +Use 'make menuconfig' to configure `onboard memory manufacturer` in Mainboard menu. ## Required blobs @@ -53,7 +54,7 @@ - eMMC - SATA - serial port -- SMbus +- SMBus - HDA (codec on carrier) - initialization with FSP MR2 - SeaBIOS payload (version rel-1.11.0-44-g7961917) diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index 8966b6e..6795584 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -41,6 +41,12 @@ bool "Micron" help Micron MT41K512M16HA memory + +config ONBOARD_MEM_KINGSTON + bool "Kingston" + help + Kingston B5116ECMDXGGB memory + endchoice config MAINBOARD_DIR diff --git a/src/mainboard/portwell/m107/Makefile.inc b/src/mainboard/portwell/m107/Makefile.inc index cca992e..7d4725ef 100644 --- a/src/mainboard/portwell/m107/Makefile.inc +++ b/src/mainboard/portwell/m107/Makefile.inc @@ -25,3 +25,4 @@ # Order of names in SPD_SOURCES is important! SPD_SOURCES = SAMSUNG_K4B8G1646D-MYKO SPD_SOURCES += MICRON_MT41K512M16HA-125A +SPD_SOURCES += KINGSTON_B5116ECMDXGGB diff --git a/src/mainboard/portwell/m107/romstage.c b/src/mainboard/portwell/m107/romstage.c index 0fe7686..1307717 100644 --- a/src/mainboard/portwell/m107/romstage.c +++ b/src/mainboard/portwell/m107/romstage.c @@ -33,6 +33,9 @@ if (CONFIG(ONBOARD_MEM_MICRON)) spd_index = 1; + else if (CONFIG(ONBOARD_MEM_KINGSTON)) + spd_index = 2; + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) die("spd.bin not found\n"); diff --git a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex new file mode 100644 index 0000000..c018620 --- /dev/null +++ b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -0,0 +1,258 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Facebook, Inc. +# Copyright (C) 2019 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# +# 8 Gb DDR3 (1600 MHz 11-11-11) Kingston B5116ECMDXGGB +# +# SINGLE DIE +# + +# 64Mx16x8 ( 8 bank, 16 Rows, 10 Col, 2 KB page size ) +# 6-7-8-9-10-11 +# DDR3L-1600 +# tCk 1.25ns +# tRCD 13.75ns +# tRP 13.75ns +# tRAS 35ns +# tRC 48.75ns +# CL-tRCD-tRP 11-11-11 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 3 = 384 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +23 + +# 1 SPD Revision +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0c = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SODIMM +# bits[6:4]: 0 = Not hybrid +# bits[7]: 0 = Not hybrid +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bits[7]: reserverd +05 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[7:6]: 0 = reserved +21 + +# 6 Module Nominal Voltage +# bits[0]: 0 = 1.5V operable +# bits[1]: 1 = 1.35V operable +# bits[2]: 0 = NOT 1.25V operable +# bits[7:3]: reserved +02 + +# 7 Module Organization +# bits[2:0]: 010b = 16 bits SDRAM device +# bits[5:3]: 000b = 1 ranks +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus width +# bits[2:0]: 3 = 64 bits pirmary bus width +# bits[4:3]: 0 = 0 bits bus witdth extension +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) dividend / divisor +# bits[3:0]: 1 = Divisor +# bits[7:4]: 1 = Dividend +11 + +# 10 Medium Timebase (MTB) dividend +# bits[7:0]: 0 = 1 (timebase 0.125ns) +01 + +# 11 Medium Timebase (MTB) divisor +# bits[7:0]: 8 (timebase 0.125ns) +08 + +# 12 SDRAM Minimum cycle time (tCKmin) +# 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +0A + +# 13 Reserved +00 + +# 14 CAS Latencies supported, Least Significate Byte +# Support 6,7,8,9,10,11 +FC + +# 15 CAS Latencies supported, Most Significate Byte +# No supporting CL 12-18 +00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 tWR = 15 ns +78 + +# 18 Minimum RAS to CAS Delay Time (tRCDmin) +# 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C tRRD = 7.5ns DDR3-1600, 2KB +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 21 Upper Nibble for tRAS and tRC +# 3:0 : 1 higher tRAS = 35ns +# 7:0 : 1 higher tRC = 48.125ns +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte +# lower 0x118 : tRAS = 35ns DDR3-1600 +18 + +# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte +# lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin +81 + +# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte +# lower 0xAF0 : tRFC = 350ns 8 Gb +F0 + +# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte +# higher 0xAF0 : tRFC = 350ns 8 Gb +0A + +# 26 tWTRmin +# 0x3C : tWTR = 7.5 ns (DDR3) +3C + +# 27 tRTPmin +# 0x3C : tRTP = 7.5 ns (DDR3) +3C + +# 28 Upper Nibble for tFAW +# Bit [3:0] : 1 = higher 0x140 tFAW = 40ns +01 + +# 29 tFAWmin Lower +# lower 0x140 : tFAW = 40ns +40 + +# 30 SDRAM Optional Features +# byte [0] : 1 = RZQ/6 is support +# byte [1] : 1 = RZQ/7 is supported +# byte [7] : 1 = DLL-Off Mode support +83 + +# 31 Thermal options +# byte [0] : 1 = 0 - 95C +# byte [2] : 0 = Auto Self Refresh (ASR) is not supported +# byte [7] : 0 = Partial Array Self Refres (PASR) is not supported +01 + +# 32 Module Thermal support +# byte [0] : 0 = Thermal sensor accuracy undefined +# byte [7] : 0 = No thermal sensor +00 + +# 33 SDRAM device type +# byte [1:0] : 00b = Signal Loading not specified +# byte [6:4] : 000b = Die count not specified +# byte [7] : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine tCKmin +# 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +00 + +# 35 Fine tAAmin +# 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin +00 + +# 36 Fine tRCDmin +# 0x00 tRCD = 13.125ns DDR3-1600K downbin +00 + +# 37 Fine tRPmin +# 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin +00 + +# 38 Fine tRCmin +# 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin +00 + +# 39-59 reserved, general section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60-116 Module specific section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 + +# 117-118 Module Manufacturer +01 98 + +# 119 Module Manufacturing Location +00 + +# 120-121 Module Manufacturing Date +13 0A + +# 122-125 Module Serial number +00 00 00 00 + +# 126-127 SPD CRC +00 00 + +# 128-145 Module Part number +66 53 49 49 54 69 67 77 68 88 71 71 66 00 00 00 +00 00 + +# 145-146 Module revision code +00 00 + +# 148-149 DRAM Manufacturer ID code +01 98 + +# 150-175 Manufacturer Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 + +# 176-255 Open for Customer Use + +# 176 - 255 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/36502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Gerrit-Change-Number: 36502 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-MessageType: newchange
Hello Frans Hendriks, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36502 to look at the new patch set (#2). Change subject: mb/portwell/m107: Add Kingston memory support ...................................................................... mb/portwell/m107: Add Kingston memory support Add support for board revision 1.3 containing Kingston memory. BUG=N/A TEST=tested on portwell m107 module Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> --- M Documentation/mainboard/portwell/pq7-m107.md M src/mainboard/portwell/m107/Kconfig M src/mainboard/portwell/m107/Makefile.inc M src/mainboard/portwell/m107/romstage.c A src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex 5 files changed, 272 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/36502/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Gerrit-Change-Number: 36502 Gerrit-PatchSet: 2 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-MessageType: newpatchset
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36502 ) Change subject: mb/portwell/m107: Add Kingston memory support ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Gerrit-Change-Number: 36502 Gerrit-PatchSet: 2 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Thu, 31 Oct 2019 11:01:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36502 ) Change subject: mb/portwell/m107: Add Kingston memory support ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/36502/3/Documentation/mainboard/por... File Documentation/mainboard/portwell/pq7-m107.md: https://review.coreboot.org/c/coreboot/+/36502/3/Documentation/mainboard/por... PS3, Line 6: Rev 1.0 Onboard Samsung K4B8G1646D-MYKO memory : Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory : Rev 1.3 On nit: not sure if the tabs in here serve much of a purpose anymore if one of the lines diverges (for good reason), but that can be changed later. -- To view, visit https://review.coreboot.org/c/coreboot/+/36502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Gerrit-Change-Number: 36502 Gerrit-PatchSet: 3 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Nov 2019 11:43:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36502 ) Change subject: mb/portwell/m107: Add Kingston memory support ...................................................................... mb/portwell/m107: Add Kingston memory support Add support for board revision 1.3 containing Kingston memory. BUG=N/A TEST=tested on portwell m107 module Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> --- M Documentation/mainboard/portwell/pq7-m107.md M src/mainboard/portwell/m107/Kconfig M src/mainboard/portwell/m107/Makefile.inc M src/mainboard/portwell/m107/romstage.c A src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex 5 files changed, 272 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved diff --git a/Documentation/mainboard/portwell/pq7-m107.md b/Documentation/mainboard/portwell/pq7-m107.md index e4da415..71bd26a 100644 --- a/Documentation/mainboard/portwell/pq7-m107.md +++ b/Documentation/mainboard/portwell/pq7-m107.md @@ -4,9 +4,10 @@ PQ7-M107 are assembled with different onboard memory modules: Rev 1.0 Onboard Samsung K4B8G1646D-MYKO memory - Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory + Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory + Rev 1.3 Onboard Kingston B5116ECMDXGGB memory -Use 'make menuconfig' to configure `onboard memory manufacture` in Mainboard +Use 'make menuconfig' to configure `onboard memory manufacturer` in Mainboard menu. ## Required blobs @@ -53,7 +54,7 @@ - eMMC - SATA - serial port -- SMbus +- SMBus - HDA (codec on carrier) - initialization with FSP MR2 - SeaBIOS payload (version rel-1.11.0-44-g7961917) diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index 8966b6e..6795584 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -41,6 +41,12 @@ bool "Micron" help Micron MT41K512M16HA memory + +config ONBOARD_MEM_KINGSTON + bool "Kingston" + help + Kingston B5116ECMDXGGB memory + endchoice config MAINBOARD_DIR diff --git a/src/mainboard/portwell/m107/Makefile.inc b/src/mainboard/portwell/m107/Makefile.inc index cca992e..7d4725ef 100644 --- a/src/mainboard/portwell/m107/Makefile.inc +++ b/src/mainboard/portwell/m107/Makefile.inc @@ -25,3 +25,4 @@ # Order of names in SPD_SOURCES is important! SPD_SOURCES = SAMSUNG_K4B8G1646D-MYKO SPD_SOURCES += MICRON_MT41K512M16HA-125A +SPD_SOURCES += KINGSTON_B5116ECMDXGGB diff --git a/src/mainboard/portwell/m107/romstage.c b/src/mainboard/portwell/m107/romstage.c index 0fe7686..1307717 100644 --- a/src/mainboard/portwell/m107/romstage.c +++ b/src/mainboard/portwell/m107/romstage.c @@ -33,6 +33,9 @@ if (CONFIG(ONBOARD_MEM_MICRON)) spd_index = 1; + else if (CONFIG(ONBOARD_MEM_KINGSTON)) + spd_index = 2; + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) die("spd.bin not found\n"); diff --git a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex new file mode 100644 index 0000000..c018620 --- /dev/null +++ b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -0,0 +1,258 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Facebook, Inc. +# Copyright (C) 2019 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# +# 8 Gb DDR3 (1600 MHz 11-11-11) Kingston B5116ECMDXGGB +# +# SINGLE DIE +# + +# 64Mx16x8 ( 8 bank, 16 Rows, 10 Col, 2 KB page size ) +# 6-7-8-9-10-11 +# DDR3L-1600 +# tCk 1.25ns +# tRCD 13.75ns +# tRP 13.75ns +# tRAS 35ns +# tRC 48.75ns +# CL-tRCD-tRP 11-11-11 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 3 = 384 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +23 + +# 1 SPD Revision +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0c = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SODIMM +# bits[6:4]: 0 = Not hybrid +# bits[7]: 0 = Not hybrid +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bits[7]: reserverd +05 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[7:6]: 0 = reserved +21 + +# 6 Module Nominal Voltage +# bits[0]: 0 = 1.5V operable +# bits[1]: 1 = 1.35V operable +# bits[2]: 0 = NOT 1.25V operable +# bits[7:3]: reserved +02 + +# 7 Module Organization +# bits[2:0]: 010b = 16 bits SDRAM device +# bits[5:3]: 000b = 1 ranks +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus width +# bits[2:0]: 3 = 64 bits pirmary bus width +# bits[4:3]: 0 = 0 bits bus witdth extension +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) dividend / divisor +# bits[3:0]: 1 = Divisor +# bits[7:4]: 1 = Dividend +11 + +# 10 Medium Timebase (MTB) dividend +# bits[7:0]: 0 = 1 (timebase 0.125ns) +01 + +# 11 Medium Timebase (MTB) divisor +# bits[7:0]: 8 (timebase 0.125ns) +08 + +# 12 SDRAM Minimum cycle time (tCKmin) +# 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +0A + +# 13 Reserved +00 + +# 14 CAS Latencies supported, Least Significate Byte +# Support 6,7,8,9,10,11 +FC + +# 15 CAS Latencies supported, Most Significate Byte +# No supporting CL 12-18 +00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 tWR = 15 ns +78 + +# 18 Minimum RAS to CAS Delay Time (tRCDmin) +# 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C tRRD = 7.5ns DDR3-1600, 2KB +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 21 Upper Nibble for tRAS and tRC +# 3:0 : 1 higher tRAS = 35ns +# 7:0 : 1 higher tRC = 48.125ns +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte +# lower 0x118 : tRAS = 35ns DDR3-1600 +18 + +# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte +# lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin +81 + +# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte +# lower 0xAF0 : tRFC = 350ns 8 Gb +F0 + +# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte +# higher 0xAF0 : tRFC = 350ns 8 Gb +0A + +# 26 tWTRmin +# 0x3C : tWTR = 7.5 ns (DDR3) +3C + +# 27 tRTPmin +# 0x3C : tRTP = 7.5 ns (DDR3) +3C + +# 28 Upper Nibble for tFAW +# Bit [3:0] : 1 = higher 0x140 tFAW = 40ns +01 + +# 29 tFAWmin Lower +# lower 0x140 : tFAW = 40ns +40 + +# 30 SDRAM Optional Features +# byte [0] : 1 = RZQ/6 is support +# byte [1] : 1 = RZQ/7 is supported +# byte [7] : 1 = DLL-Off Mode support +83 + +# 31 Thermal options +# byte [0] : 1 = 0 - 95C +# byte [2] : 0 = Auto Self Refresh (ASR) is not supported +# byte [7] : 0 = Partial Array Self Refres (PASR) is not supported +01 + +# 32 Module Thermal support +# byte [0] : 0 = Thermal sensor accuracy undefined +# byte [7] : 0 = No thermal sensor +00 + +# 33 SDRAM device type +# byte [1:0] : 00b = Signal Loading not specified +# byte [6:4] : 000b = Die count not specified +# byte [7] : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine tCKmin +# 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +00 + +# 35 Fine tAAmin +# 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin +00 + +# 36 Fine tRCDmin +# 0x00 tRCD = 13.125ns DDR3-1600K downbin +00 + +# 37 Fine tRPmin +# 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin +00 + +# 38 Fine tRCmin +# 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin +00 + +# 39-59 reserved, general section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60-116 Module specific section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 + +# 117-118 Module Manufacturer +01 98 + +# 119 Module Manufacturing Location +00 + +# 120-121 Module Manufacturing Date +13 0A + +# 122-125 Module Serial number +00 00 00 00 + +# 126-127 SPD CRC +00 00 + +# 128-145 Module Part number +66 53 49 49 54 69 67 77 68 88 71 71 66 00 00 00 +00 00 + +# 145-146 Module revision code +00 00 + +# 148-149 DRAM Manufacturer ID code +01 98 + +# 150-175 Manufacturer Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 + +# 176-255 Open for Customer Use + +# 176 - 255 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/36502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Gerrit-Change-Number: 36502 Gerrit-PatchSet: 4 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-MessageType: merged
participants (3)
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Frans Hendriks (Code Review) -
Patrick Georgi (Code Review)
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Wim Vervoorn (Code Review)