Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36602 )
Change subject: mb/supermicro/x11-lga1151-series: drop console guard in bootblock
......................................................................
mb/supermicro/x11-lga1151-series: drop console guard in bootblock
To make debugging possible in a fallback setup, the serial console must
be set up in bootblock, thus drop the guard.
Change-Id: If0dd3c03ba52b4936eb234e6b2b61bb5ce044fcd
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36602
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/supermicro/x11-lga1151-series/bootblock.c
1 file changed, 1 insertion(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c
index fe76512..75afd2e 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c
+++ b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c
@@ -32,8 +32,7 @@
static void early_config_superio(void)
{
const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1);
- if (CONFIG(CONSOLE_SERIAL))
- aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+ aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
}
void bootblock_mainboard_early_init(void)
--
To view, visit https://review.coreboot.org/c/coreboot/+/36602
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If0dd3c03ba52b4936eb234e6b2b61bb5ce044fcd
Gerrit-Change-Number: 36602
Gerrit-PatchSet: 2
Gerrit-Owner: Michael Niewöhner
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Michael Niewöhner
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36592 )
Change subject: mb/supermicro/x11-lga1151-series: use new console delay Kconfig option
......................................................................
mb/supermicro/x11-lga1151-series: use new console delay Kconfig option
This replaces the hardcoded delay by the new Kconfig option.
Change-Id: I8bf4ef7ad9beea7b3dc22e1567623a423597eff9
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36592
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/supermicro/x11-lga1151-series/Kconfig
M src/mainboard/supermicro/x11-lga1151-series/bootblock.c
2 files changed, 2 insertions(+), 6 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig
index da8038b..a3ed8af 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig
+++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig
@@ -13,6 +13,7 @@
select GENERATE_SMBIOS_TABLES
select IPMI_KCS
select MAINBOARD_NO_FSP_GOP
+ select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND
if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
diff --git a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c
index 27653f5..fe76512 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c
+++ b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c
@@ -32,13 +32,8 @@
static void early_config_superio(void)
{
const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1);
- if (CONFIG(CONSOLE_SERIAL)) {
+ if (CONFIG(CONSOLE_SERIAL))
aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
- /* The serial output is garbeled before this timeout.
- * FIXME: Find out why and remove delay.
- */
- mdelay(1000);
- }
}
void bootblock_mainboard_early_init(void)
--
To view, visit https://review.coreboot.org/c/coreboot/+/36592
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8bf4ef7ad9beea7b3dc22e1567623a423597eff9
Gerrit-Change-Number: 36592
Gerrit-PatchSet: 8
Gerrit-Owner: Michael Niewöhner
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Michael Niewöhner
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36591 )
Change subject: superio/aspeed/common: add workaround for serial routing delay quirk
......................................................................
superio/aspeed/common: add workaround for serial routing delay quirk
Some mainboards with an ASPEED BMC do the serial routing setup in the
BMC boot phase on cold boot. This results in scrambled console output
when this is not finished fast enough.
This adds a delay of 500ms as workaround in the BMCs uart setup that
can be selected at mainboard level.
A user may disable the workaround when using another BMC firmware like
OpenBMC, u-bmc or some custom BMC bootloader with fast serial setup.
Change-Id: I7d6599b76384fc94a00a9cfc1794ebfe34863ff9
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36591
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/superio/aspeed/common/Kconfig
M src/superio/aspeed/common/early_serial.c
2 files changed, 21 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
diff --git a/src/superio/aspeed/common/Kconfig b/src/superio/aspeed/common/Kconfig
index 3f0dabb..f310f3e 100644
--- a/src/superio/aspeed/common/Kconfig
+++ b/src/superio/aspeed/common/Kconfig
@@ -20,3 +20,20 @@
config SUPERIO_ASPEED_COMMON_PRE_RAM
bool
default n
+
+config SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND
+ bool
+ default n
+
+config SUPERIO_ASPEED_USE_UART_DELAY_WORKAROUND
+ bool "Workaround for BMC serial console setup bug"
+ depends on CONSOLE_SERIAL && SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND
+ default y
+ help
+ Some mainboards with an ASPEED BMC have scrambled console output in early boot phases
+ because the serial output routing is not set up fast enough by the BMC. By enabling
+ this a delay of 500ms gets added before setting up the console and before any console
+ output gets printed.
+
+ Note: this problem may disappear with future BMC firmware versions. Another approach
+ is using a different BMC firmware like OpenBMC, u-bmc, ...
diff --git a/src/superio/aspeed/common/early_serial.c b/src/superio/aspeed/common/early_serial.c
index 7ac9474..d2de8ed 100644
--- a/src/superio/aspeed/common/early_serial.c
+++ b/src/superio/aspeed/common/early_serial.c
@@ -35,6 +35,7 @@
*/
#include <arch/io.h>
+#include <delay.h>
#include <device/pnp_def.h>
#include <device/pnp_ops.h>
#include <stdint.h>
@@ -67,4 +68,7 @@
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
+
+ if (CONFIG(SUPERIO_ASPEED_USE_UART_DELAY_WORKAROUND))
+ mdelay(500);
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/36591
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7d6599b76384fc94a00a9cfc1794ebfe34863ff9
Gerrit-Change-Number: 36591
Gerrit-PatchSet: 8
Gerrit-Owner: Michael Niewöhner
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Michael Niewöhner
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36587 )
Change subject: cpu/intel/smm/gen1: Deal with SMM save state compatibility
......................................................................
cpu/intel/smm/gen1: Deal with SMM save state compatibility
Change-Id: I92326e3e0481d750cb9c90f717ed748000e33ad3
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/smm/gen1/smmrelocate.c
1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/36587/1
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 3eb869a..5350d1c 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -168,6 +168,9 @@
if (smm_reloc_params.ied_size)
setup_ied_area(&smm_reloc_params);
+ /* This may not be be correct for older CPU's supported by this code,
+ but given that em64t101_smm_state_save_area_t is larger than the
+ save_state of these CPU's it works. */
*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
}
@@ -191,6 +194,8 @@
{
msr_t mtrr_cap;
struct smm_relocation_params *relo_params = &smm_reloc_params;
+ /* The em64t101 save state is sufficiently compatible with older
+ save states with regards of smbase, smm_revision. */
em64t101_smm_state_save_area_t *save_state;
u32 smbase = staggered_smbase;
u32 iedbase = relo_params->ied_base;
@@ -208,7 +213,10 @@
save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
sizeof(*save_state));
save_state->smbase = smbase;
- save_state->iedbase = iedbase;
+
+ printk(BIOS_SPEW, "SMM revision: 0x%08x\n", save_state->smm_revision);
+ if (save_state->smm_revision == 0x00030101)
+ save_state->iedbase = iedbase;
/* Write EMRR and SMRR MSRs based on indicated support. */
mtrr_cap = rdmsr(MTRR_CAP_MSR);
--
To view, visit https://review.coreboot.org/c/coreboot/+/36587
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I92326e3e0481d750cb9c90f717ed748000e33ad3
Gerrit-Change-Number: 36587
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36578 )
Change subject: mb/*/*{i82801ix}: Use sb/intel/common/acpi/platform.asl
......................................................................
mb/*/*{i82801ix}: Use sb/intel/common/acpi/platform.asl
Change-Id: I9150db163131d4c3f99a4e0b6922a61c96a6d6e2
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
D src/mainboard/asus/p5qc/acpi/platform.asl
M src/mainboard/asus/p5qc/dsdt.asl
D src/mainboard/intel/dg43gt/acpi/platform.asl
M src/mainboard/intel/dg43gt/dsdt.asl
4 files changed, 2 insertions(+), 58 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/36578/1
diff --git a/src/mainboard/asus/p5qc/acpi/platform.asl b/src/mainboard/asus/p5qc/acpi/platform.asl
deleted file mode 100644
index 6c92a4e..0000000
--- a/src/mainboard/asus/p5qc/acpi/platform.asl
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Method(_PIC, 1)
-{
- /* Remember the OS' IRQ routing choice. */
- Store(Arg0, PICM)
-}
-
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
- Store (Arg0, SMIF) /* SMI Function */
- Store (0, TRP0) /* Generate trap */
- Return (SMIF) /* Return value of SMI handler */
-}
diff --git a/src/mainboard/asus/p5qc/dsdt.asl b/src/mainboard/asus/p5qc/dsdt.asl
index 5ec7c19..8ee15fb 100644
--- a/src/mainboard/asus/p5qc/dsdt.asl
+++ b/src/mainboard/asus/p5qc/dsdt.asl
@@ -25,7 +25,7 @@
)
{
// global NVS and variables
- #include "acpi/platform.asl"
+ #include <southbridge/intel/common/acpi/platform.asl>
#include <southbridge/intel/i82801jx/acpi/globalnvs.asl>
Scope (\_SB) {
diff --git a/src/mainboard/intel/dg43gt/acpi/platform.asl b/src/mainboard/intel/dg43gt/acpi/platform.asl
deleted file mode 100644
index 6c92a4e..0000000
--- a/src/mainboard/intel/dg43gt/acpi/platform.asl
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Method(_PIC, 1)
-{
- /* Remember the OS' IRQ routing choice. */
- Store(Arg0, PICM)
-}
-
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
- Store (Arg0, SMIF) /* SMI Function */
- Store (0, TRP0) /* Generate trap */
- Return (SMIF) /* Return value of SMI handler */
-}
diff --git a/src/mainboard/intel/dg43gt/dsdt.asl b/src/mainboard/intel/dg43gt/dsdt.asl
index 911dcee..a43d2dc 100644
--- a/src/mainboard/intel/dg43gt/dsdt.asl
+++ b/src/mainboard/intel/dg43gt/dsdt.asl
@@ -25,7 +25,7 @@
)
{
// global NVS and variables
- #include "acpi/platform.asl"
+ #include <southbridge/intel/common/acpi/platform.asl>
#include <southbridge/intel/i82801jx/acpi/globalnvs.asl>
Scope (\_SB) {
--
To view, visit https://review.coreboot.org/c/coreboot/+/36578
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9150db163131d4c3f99a4e0b6922a61c96a6d6e2
Gerrit-Change-Number: 36578
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange