coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/icelake: Set DCACHE_BSP_STACK_SIZE default ~129KiB uncondit...
by Subrata Banik (Code Review) 04 Nov '19

04 Nov '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36538 ) Change subject: soc/intel/icelake: Set DCACHE_BSP_STACK_SIZE default ~129KiB unconditionally ...................................................................... soc/intel/icelake: Set DCACHE_BSP_STACK_SIZE default ~129KiB unconditionally Icelake default selects PLATFORM_USES_FSP2_1 which means stack will be shared between FSP and coreboot (CONFIG_FSP_USES_CB_STACK) hence no need to have any other default value than 129KiB (128KiB for FSP and 1KiB for coreboot) Change-Id: I856f7e48a4a1e86eb082b9e772e0776664edca51 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/Kconfig 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/36538/1 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 4ae043a..aa59f85 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -70,8 +70,7 @@ config DCACHE_BSP_STACK_SIZE hex - default 0x20400 if FSP_USES_CB_STACK - default 0x4000 + default 0x20400 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be -- To view, visit https://review.coreboot.org/c/coreboot/+/36538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I856f7e48a4a1e86eb082b9e772e0776664edca51 Gerrit-Change-Number: 36538 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/icelake: Remove unused headers
by Subrata Banik (Code Review) 04 Nov '19

04 Nov '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36536 ) Change subject: soc/intel/icelake: Remove unused headers ...................................................................... soc/intel/icelake: Remove unused headers This patch removes inclusion of unused headers from soc/intel/icelake Change-Id: Icb653dee7992538aadf98d84adadd081f816fd01 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/bootblock/bootblock.c M src/soc/intel/icelake/include/soc/bootblock.h M src/soc/intel/icelake/include/soc/cpu.h M src/soc/intel/icelake/include/soc/espi.h 4 files changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/36536/1 diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index db43e50..f348c1b 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -15,6 +15,7 @@ #include <bootblock_common.h> #include <intelblocks/gspi.h> +#include <intelblocks/systemagent.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> #include <soc/iomap.h> diff --git a/src/soc/intel/icelake/include/soc/bootblock.h b/src/soc/intel/icelake/include/soc/bootblock.h index 2f6473d..4ca2c37 100644 --- a/src/soc/intel/icelake/include/soc/bootblock.h +++ b/src/soc/intel/icelake/include/soc/bootblock.h @@ -16,8 +16,6 @@ #ifndef _SOC_ICELAKE_BOOTBLOCK_H_ #define _SOC_ICELAKE_BOOTBLOCK_H_ -#include <intelblocks/systemagent.h> - /* Bootblock pre console init programming */ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h index b5722da..7d170580 100644 --- a/src/soc/intel/icelake/include/soc/cpu.h +++ b/src/soc/intel/icelake/include/soc/cpu.h @@ -16,7 +16,6 @@ #ifndef _SOC_ICELAKE_CPU_H_ #define _SOC_ICELAKE_CPU_H_ -#include <device/device.h> #include <intelblocks/msr.h> /* Latency times in units of 32768ns */ diff --git a/src/soc/intel/icelake/include/soc/espi.h b/src/soc/intel/icelake/include/soc/espi.h index 36ee947..fcc796e 100644 --- a/src/soc/intel/icelake/include/soc/espi.h +++ b/src/soc/intel/icelake/include/soc/espi.h @@ -16,8 +16,6 @@ #ifndef _SOC_ICELAKE_ESPI_H_ #define _SOC_ICELAKE_ESPI_H_ -#include <stdint.h> - /* PCI Configuration Space (D31:F0): ESPI */ #define SCI_IRQ_SEL (7 << 0) #define SCIS_IRQ9 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/36536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb653dee7992538aadf98d84adadd081f816fd01 Gerrit-Change-Number: 36536 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/icelake: Skip BIOS OpRom execution based on CONFIG_RUN_FSP_GOP
by Subrata Banik (Code Review) 04 Nov '19

04 Nov '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36532 ) Change subject: soc/intel/icelake: Skip BIOS OpRom execution based on CONFIG_RUN_FSP_GOP ...................................................................... soc/intel/icelake: Skip BIOS OpRom execution based on CONFIG_RUN_FSP_GOP This patch replaces BIOS OpRpm execution checks from CONFIG_INTEL_GMA_ADD_VBT to CONFIG_RUN_FSP_GOP as adding VBT files doesn't mean GFX PEIM is going to execute to initialize IGD. Change-Id: Ic76529ba11f621f644d4472be6cbbc34682f00bf Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/graphics.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/36532/1 diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 0709033..91f40b9 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -52,14 +52,14 @@ /* * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on INTEL_GMA_ADD_VBT Kconfig + * initialization based on RUN_FSP_GOP Kconfig * option and input VBT file. Hence no need to load/execute legacy VGA * OpROM in order to initialize GFX. * * In case of non-FSP solution, SoC need to select VGA_ROM_RUN * Kconfig to perform GFX initialization through VGA OpRom. */ - if (CONFIG(INTEL_GMA_ADD_VBT)) + if (CONFIG(RUN_FSP_GOP)) return; /* IGD needs to Bus Master */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic76529ba11f621f644d4472be6cbbc34682f00bf Gerrit-Change-Number: 36532 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/icelake: Clean up report_cpu_info() function
by Subrata Banik (Code Review) 04 Nov '19

04 Nov '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36531 ) Change subject: soc/intel/icelake: Clean up report_cpu_info() function ...................................................................... soc/intel/icelake: Clean up report_cpu_info() function This patch makes below clean up for report_cpu_info() function 1. Replace cpu_string with cpu_not_found 2. Assign default string "Platform info not available" to cpu_not_found string 3. Add array out of bound check while skiping leading white space in cpu brand string name Change-Id: I41c76eb93f0c5229c4a49aa041339b8ad51ad34a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/bootblock/report_platform.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/36531/1 diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index a9eef40..b1d9647 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -93,7 +93,8 @@ { struct cpuid_result cpuidr; u32 i, index, cpu_id, cpu_feature_flag; - char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ + const char cpu_not_found[] = "Platform info not available"; + const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ int vt, txt, aes; msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; @@ -102,9 +103,7 @@ index = 0x80000000; cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - } else { + if (cpuidr.eax >= 0x80000004) { int j = 0; for (i = 2; i <= 4; i++) { @@ -118,7 +117,7 @@ cpu_name = (char *)p; } /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ') + while (cpu_name[0] == ' ' && strlen(cpu_name) > 0) cpu_name++; microcode_ver.lo = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/36531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41c76eb93f0c5229c4a49aa041339b8ad51ad34a Gerrit-Change-Number: 36531 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7180: Add UART support
by Roja Rani Yarubandi (Code Review) 04 Nov '19

04 Nov '19

Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35500 ) Change subject: sc7180: Add UART support ...................................................................... Patch Set 12: (1 comment) > Patch Set 11: Code-Review+2 > > (1 comment) https://review.coreboot.org/c/coreboot/+/35500/11/src/soc/qualcomm/sc7180/u… File src/soc/qualcomm/sc7180/uart.c: https://review.coreboot.org/c/coreboot/+/35500/11/src/soc/qualcomm/sc7180/u… PS11, Line 78: XBL > What does XBL mean here? Do you mean QcLib? Yes, QcLib. -- To view, visit https://review.coreboot.org/c/coreboot/+/35500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Gerrit-Change-Number: 35500 Gerrit-PatchSet: 12 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 04 Nov 2019 06:21:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: drop console guard in bootblock
by Arthur Heymans (Code Review) 03 Nov '19

03 Nov '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36602 ) Change subject: mb/supermicro/x11-lga1151-series: drop console guard in bootblock ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0dd3c03ba52b4936eb234e6b2b61bb5ce044fcd Gerrit-Change-Number: 36602 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Nov 2019 21:45:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: drop console guard in bootblock
by Michael Niewöhner (Code Review) 03 Nov '19

03 Nov '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36602 ) Change subject: mb/supermicro/x11-lga1151-series: drop console guard in bootblock ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/36602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0dd3c03ba52b4936eb234e6b2b61bb5ce044fcd Gerrit-Change-Number: 36602 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Nov 2019 21:45:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: use new console delay Kconfig option
by Michael Niewöhner (Code Review) 03 Nov '19

03 Nov '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36592 ) Change subject: mb/supermicro/x11-lga1151-series: use new console delay Kconfig option ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/36592/7/src/mainboard/supermicro/x… File src/mainboard/supermicro/x11-lga1151-series/bootblock.c: https://review.coreboot.org/c/coreboot/+/36592/7/src/mainboard/supermicro/x… PS7, Line 35: if (CONFIG(CONSOLE_SERIAL)) > IMO not really needed anymore since CONSOLE_SERIAL is guarded by against in Kconfig. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/36592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bf4ef7ad9beea7b3dc22e1567623a423597eff9 Gerrit-Change-Number: 36592 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Nov 2019 21:33:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrr/xip_cache.c: Fix inconsistent message
by Angel Pons (Code Review) 03 Nov '19

03 Nov '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36585 ) Change subject: cpu/x86/mtrr/xip_cache.c: Fix inconsistent message ...................................................................... cpu/x86/mtrr/xip_cache.c: Fix inconsistent message Change-Id: Ic99e61632664f86cc12507f2ddffa364fdd79202 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/x86/mtrr/xip_cache.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/36585/1 diff --git a/src/cpu/x86/mtrr/xip_cache.c b/src/cpu/x86/mtrr/xip_cache.c index 112c0dfb..9968eea 100644 --- a/src/cpu/x86/mtrr/xip_cache.c +++ b/src/cpu/x86/mtrr/xip_cache.c @@ -63,7 +63,7 @@ if (cpu_info.x86 == 0xf) { printk(BIOS_NOTICE, "PROG_RUN: CPU does not support caching ROM\n" - "The next stage will run slowly\n"); + "The next stage will run slowly!\n"); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/36585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic99e61632664f86cc12507f2ddffa364fdd79202 Gerrit-Change-Number: 36585 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/{i82801gx,x4x}: Don't select ASPM options
by Arthur Heymans (Code Review) 03 Nov '19

03 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36576 ) Change subject: mb/intel/{i82801gx,x4x}: Don't select ASPM options ...................................................................... mb/intel/{i82801gx,x4x}: Don't select ASPM options These are likely not properly set up and L1 is not even supported on the desktop variant of the southbridge. This fixes observed instability on some PCIe GPUs. Change-Id: I70d3536984342614a6ef04a45bc6591e358e3abe Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/Kconfig M src/mainboard/asus/p5qpl-am/Kconfig M src/mainboard/foxconn/g41s-k/Kconfig M src/mainboard/intel/dg41wv/Kconfig M src/mainboard/lenovo/thinkcentre_a58/Kconfig 5 files changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/36576/1 diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig index e7cbf7a..81b0995 100644 --- a/src/mainboard/asrock/g41c-gs/Kconfig +++ b/src/mainboard/asrock/g41c-gs/Kconfig @@ -30,9 +30,6 @@ || BOARD_ASROCK_G41M_VS3_R2_0 select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME diff --git a/src/mainboard/asus/p5qpl-am/Kconfig b/src/mainboard/asus/p5qpl-am/Kconfig index 7eee9cd..7cdfea9 100644 --- a/src/mainboard/asus/p5qpl-am/Kconfig +++ b/src/mainboard/asus/p5qpl-am/Kconfig @@ -25,9 +25,6 @@ select SUPERIO_WINBOND_W83627DHG select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME diff --git a/src/mainboard/foxconn/g41s-k/Kconfig b/src/mainboard/foxconn/g41s-k/Kconfig index f74fcd6..3597e4c 100644 --- a/src/mainboard/foxconn/g41s-k/Kconfig +++ b/src/mainboard/foxconn/g41s-k/Kconfig @@ -29,9 +29,6 @@ select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE select MAINBOARD_HAS_LPC_TPM - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT diff --git a/src/mainboard/intel/dg41wv/Kconfig b/src/mainboard/intel/dg41wv/Kconfig index 373f6fa..74c7d52 100644 --- a/src/mainboard/intel/dg41wv/Kconfig +++ b/src/mainboard/intel/dg41wv/Kconfig @@ -25,9 +25,6 @@ select SUPERIO_WINBOND_W83627DHG select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig b/src/mainboard/lenovo/thinkcentre_a58/Kconfig index fc1c6a7..6d8b3dc 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Kconfig +++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig @@ -25,9 +25,6 @@ select SUPERIO_SMSC_SMSCSUPERIO select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME -- To view, visit https://review.coreboot.org/c/coreboot/+/36576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70d3536984342614a6ef04a45bc6591e358e3abe Gerrit-Change-Number: 36576 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019