Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36595 )
Change subject: cpu/intel/car/p4-netburst: Remove delay loops ......................................................................
cpu/intel/car/p4-netburst: Remove delay loops
While commented as 10 ms + 250 us, those delay loops actually accounted for a total of 840 ms. And they seem unnecessary as followup code has potentially infinite retries when polling for status changes.
Tested on aopen/dxplplusu, dual-socket P4 Xeon HT model_f2x.
Change-Id: Ib7d1d66ed29c62d97073872f0b7809d719ac2324 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/car/p4-netburst/cache_as_ram.S 1 file changed, 0 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/36595/1
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 2cd0c5e..58e411d 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -177,12 +177,6 @@
hyper_threading_cpu:
- /* delay 10 ms */ - movl $10000, %ecx -1: inb $0x80, %al - dec %ecx - jnz 1b - post_code(0x25)
/* Send Start IPI to all excluding ourself. */ @@ -198,12 +192,6 @@ andl $LAPIC_ICR_BUSY, %ecx jnz 1b
- /* delay 250 us */ - movl $250, %ecx -1: inb $0x80, %al - dec %ecx - jnz 1b - post_code(0x26)
/* Wait for sibling CPU to start. */
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36595 )
Change subject: cpu/intel/car/p4-netburst: Remove delay loops ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36595 )
Change subject: cpu/intel/car/p4-netburst: Remove delay loops ......................................................................
cpu/intel/car/p4-netburst: Remove delay loops
While commented as 10 ms + 250 us, those delay loops actually accounted for a total of 840 ms. And they seem unnecessary as followup code has potentially infinite retries when polling for status changes.
Tested on aopen/dxplplusu, dual-socket P4 Xeon HT model_f2x.
Change-Id: Ib7d1d66ed29c62d97073872f0b7809d719ac2324 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36595 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/car/p4-netburst/cache_as_ram.S 1 file changed, 0 insertions(+), 12 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 2cd0c5e..58e411d 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -177,12 +177,6 @@
hyper_threading_cpu:
- /* delay 10 ms */ - movl $10000, %ecx -1: inb $0x80, %al - dec %ecx - jnz 1b - post_code(0x25)
/* Send Start IPI to all excluding ourself. */ @@ -198,12 +192,6 @@ andl $LAPIC_ICR_BUSY, %ecx jnz 1b
- /* delay 250 us */ - movl $250, %ecx -1: inb $0x80, %al - dec %ecx - jnz 1b - post_code(0x26)
/* Wait for sibling CPU to start. */
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)
-
Patrick Georgi (Code Review)