coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank
by Angel Pons (Code Review) 28 Jan '19

28 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28648 ) Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank ...................................................................... Patch Set 7: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/28648/7/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/#/c/28648/7/src/northbridge/intel/i945/raminit.… PS7, … [View More]

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Change in ...coreboot[master]: cpu/intel/speedstep: Add Netburst
by Paul Menzel (Code Review) 28 Jan '19

28 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22604 ) Change subject: cpu/intel/speedstep: Add Netburst ...................................................................... Patch Set 65: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: … [View More]

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Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage.
by Paul Menzel (Code Review) 28 Jan '19

28 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30331 ) Change subject: google/kukui: Move some initialization from bootblock to verstage. ...................................................................... Patch Set 12: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/30331/12//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30331/12//COMMIT_MSG@7 PS12, Line 7: google/kukui: Move some initialization from bootblock to … [View More]

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Paul Menzel (Code Review) 28 Jan '19

28 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: … [View More]

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Change in ...coreboot[master]: soc/intel/{apl,skl}: Drop redundant `select RTC`
by Nico Huber (Code Review) 28 Jan '19

28 Jan '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31113 Change subject: soc/intel/{apl,skl}: Drop redundant `select RTC` ...................................................................... soc/intel/{apl,skl}: Drop redundant `select RTC` RTC is now implicitly selected through SOC_INTEL_COMMON_BLOCK_RTC and SOC_INTEL_COMMON_PCH_BASE. Change-Id: I1885c419cfe318b75f3bda6220d4a6f6a8e26575 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/… [View More]

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Change in ...coreboot[master]: soc/intel/common/rtc: Enable RTC if common code RTC
by Lijian Zhao (Code Review) 28 Jan '19

28 Jan '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31112 Change subject: soc/intel/common/rtc: Enable RTC if common code RTC ...................................................................... soc/intel/common/rtc: Enable RTC if common code RTC Intel RTC common code driver need to turn on RTC itself. BUG=b:123372643 TEST=build and boot up on sarien platform, check .config to see CONFIG_RTC is set. Signed-off-by: Lijian Zhao <lijian.zhao(a)… [View More]

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Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage.
by Hung-Te Lin (Code Review) 28 Jan '19

28 Jan '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30331 ) Change subject: google/kukui: Move some initialization from bootblock to verstage. ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master … [View More]

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Change in ...coreboot[master]: cpu/intel/speedstep: Add Netburst
by HAOUAS Elyes (Code Review) 28 Jan '19

28 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22604 ) Change subject: cpu/intel/speedstep: Add Netburst ...................................................................... Patch Set 64: (1 comment) https://review.coreboot.org/#/c/22604/64/src/cpu/intel/speedstep/speedstep.c File src/cpu/intel/speedstep/speedstep.c: https://review.coreboot.org/#/c/22604/64/src/cpu/intel/speedstep/speedstep.… PS64, Line 84: !(rdmsr(IA32_MISC_ENABLE).hi … [View More]

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Change in ...coreboot[master]: src/soc/intel/cnl/chip.h: Fix preprocessor condition
by Ronak Kanabar (Code Review) 28 Jan '19

28 Jan '19

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31095 ) Change subject: src/soc/intel/cnl/chip.h: Fix preprocessor condition ...................................................................... Patch Set 5: > Patch Set 4: > > we will take this clean up activity to remove hard coding for sagv config in devicetree.cb and make use of macro as applicable. That would helped us to catch this issue on WHLRVP in absence of hatch board in lab. … [View More]

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Change in ...coreboot[master]: src/soc/intel/cnl/chip.h: Fix preprocessor condition
by Subrata Banik (Code Review) 28 Jan '19

28 Jan '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31095 ) Change subject: src/soc/intel/cnl/chip.h: Fix preprocessor condition ...................................................................... Patch Set 4: we will take this clean up activity to remove hard coding for sagv config in devicetree.cb and make use of macro as applicable. That would helped us to catch this issue on WHLRVP in absence of hatch board in lab. -- To view, visit https://… [View More]

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coreboot-gerrit January 2019