coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: Documentation: Fix up list of releases
by Patrick Georgi (Code Review) 28 Jan '19

28 Jan '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31126 Change subject: Documentation: Fix up list of releases ...................................................................... Documentation: Fix up list of releases 4.9 was still marked as "upcoming" and 4.10 was missing altogether, leading to a sphinx warning. Change-Id: I008d546715b7841eb9f325a6f698380dd4c1a7c2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/releases/index.md 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31126/1 diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md index 4571d12..ccbd6fe 100644 --- a/Documentation/releases/index.md +++ b/Documentation/releases/index.md @@ -9,6 +9,7 @@ * [4.6 - April 2017](coreboot-4.6-relnotes.md) * [4.7 - January 2018](coreboot-4.7-relnotes.md) * [4.8 - May 2018](coreboot-4.8.1-relnotes.md) +* [4.9 - December 2018](coreboot-4.9-relnotes.md) The checklist contains instructions to ensure that a release covers all important things and provides a reliable format for tarballs, branch @@ -20,4 +21,4 @@ ---------------- Please add to the release notes as changes are added: -* [4.9 - November 2018](coreboot-4.9-relnotes.md) +* [4.10 - April 2019](coreboot-4.10-relnotes.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/31126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I008d546715b7841eb9f325a6f698380dd4c1a7c2 Gerrit-Change-Number: 31126 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank
by Angel Pons (Code Review) 28 Jan '19

28 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28648 ) Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank ...................................................................... Patch Set 9: Code-Review+1 > Patch Set 7: > > (1 comment) > > > Also, according to "Intel® 945G/945GZ/945GC/945P/945PL Express > > Chipset Family", this bit is reserved on desktop variants. I don't > > think it should be set. > > "Intel® 945G/945GZ/945GC/945P/945PL Express Chipset Family" is shitty.. :) lol Okay, noted. It definitely does not seem to be confidence-inspiring... -- To view, visit https://review.coreboot.org/c/coreboot/+/28648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Gerrit-Change-Number: 28648 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Jan 2019 20:19:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Angel Pons (Code Review) 28 Jan '19

28 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/31120/2/src/mainboard/intel/cannonlake_rvp/… File src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb: https://review.coreboot.org/#/c/31120/2/src/mainboard/intel/cannonlake_rvp/… PS2, Line 8: SaGv_FixedHigh > For CNL FSP 3 means FixedHigh. It was set 3 previously so I made it fixedhigh. […] Refer to commit 39648bb54b2bdeda3bc5a1bd63b8b5f60478f2f7 (CB:21198) to see what change set SaGv to 3. -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Gerrit-Change-Number: 31120 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Jan 2019 20:04:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ronak Kanabar <ronak.kanabar(a)intel.com> Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Comment-In-Reply-To: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Ronak Kanabar (Code Review) 28 Jan '19

28 Jan '19

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/31120/2/src/mainboard/intel/cannonlake_rvp/… File src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb: https://review.coreboot.org/#/c/31120/2/src/mainboard/intel/cannonlake_rvp/… PS2, Line 8: SaGv_FixedHigh > Yes, I think it should be 4 for this case, SaGV_Enabled. For CNL FSP 3 means FixedHigh. It was set 3 previously so I made it fixedhigh. I am not sure why it was configured 3 previously. I was removing fixed value and replacing with SaGv macro so configured as FixedHigh. CNL FSP SaGv configation options are as follow. 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled You can also refer to macro in following file https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/cannonlake… I need to check previously why it was configured it to 3. so for this patch we can use this value. If it ok to configure it to SaGv_Enable I will push patch for that. -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Gerrit-Change-Number: 31120 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Jan 2019 19:42:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Comment-In-Reply-To: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Lijian Zhao (Code Review) 28 Jan '19

28 Jan '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/31120/2/src/mainboard/intel/cannonlake_rvp/… File src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb: https://review.coreboot.org/#/c/31120/2/src/mainboard/intel/cannonlake_rvp/… PS2, Line 8: SaGv_FixedHigh > Why is this FixedHigh? It previously was SaGv_Enabled=3. Yes, I think it should be 4 for this case, SaGV_Enabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Gerrit-Change-Number: 31120 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Jan 2019 19:19:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/microcode: Enable verbose output
by David Hendricks (Code Review) 28 Jan '19

28 Jan '19

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29864 ) Change subject: cpu/intel/microcode: Enable verbose output ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534aa790c8d37b5f1603e1715635446835513a65 Gerrit-Change-Number: 29864 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Jan 2019 18:52:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Enable RTC support
by Lijian Zhao (Code Review) 28 Jan '19

28 Jan '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31102 Change subject: soc/intel/cannonlake: Enable RTC support ...................................................................... soc/intel/cannonlake: Enable RTC support Turn on RTC support for Cannonlake SOC. BUG=b:123372643 TEST=build and boot up on sarien platform, run cbmem -c, the "timestamp unavilable" error message gone. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I34e73f6508bd83e2c8edf740c33eb253bffa5e6d --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31102/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f8193cd..6bd8a7f 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -49,6 +49,7 @@ select POSTCAR_CONSOLE select POSTCAR_STAGE select REG_SCRIPT + select RTC select SMM_TSEG select SMP select SOC_AHCI_PORT_IMPLEMENTED_INVERT @@ -62,6 +63,7 @@ select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP -- To view, visit https://review.coreboot.org/c/coreboot/+/31102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34e73f6508bd83e2c8edf740c33eb253bffa5e6d Gerrit-Change-Number: 31102 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Access SMBUS through MMIO
by Martin Roth (Code Review) 28 Jan '19

28 Jan '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29258 ) Change subject: soc/amd/stoneyridge: Access SMBUS through MMIO ...................................................................... Patch Set 12: (3 comments) https://review.coreboot.org/#/c/29258/12/src/soc/amd/stoneyridge/include/so… File src/soc/amd/stoneyridge/include/soc/iomap.h: https://review.coreboot.org/#/c/29258/12/src/soc/amd/stoneyridge/include/so… PS12, Line 42: 0xfed80a00 Not sure if there's actually an extra space here or if it's a gerrit artifact. Could you check? https://review.coreboot.org/#/c/29258/12/src/soc/amd/stoneyridge/include/so… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/29258/12/src/soc/amd/stoneyridge/include/so… PS12, Line 116: /* SMBUS MMIO offsets 0xfed80a00 */ Why did these get moved out of smbus.h? If it makes sense to move these, does it make sense just go get rid of smbus.h and move everything here? https://review.coreboot.org/#/c/29258/12/src/soc/amd/stoneyridge/sm.c File src/soc/amd/stoneyridge/sm.c: https://review.coreboot.org/#/c/29258/12/src/soc/amd/stoneyridge/sm.c@64 PS12, Line 64: get_sm_mmio(dev) It seems horribly inefficient to have to do this every time. I know that you didn't change it here, but is there a better way? Maybe in a follow-on patch? OTOH, I don't even know how much these are being used since we're not reading the SPD from the smbus, so maybe it's not worth optimizing further right now. -- To view, visit https://review.coreboot.org/c/coreboot/+/29258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8 Gerrit-Change-Number: 29258 Gerrit-PatchSet: 12 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Jan 2019 18:03:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Duncan Laurie (Code Review) 28 Jan '19

28 Jan '19

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/31120/2/src/mainboard/intel/cannonlake_rvp/… File src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb: https://review.coreboot.org/#/c/31120/2/src/mainboard/intel/cannonlake_rvp/… PS2, Line 8: SaGv_FixedHigh Why is this FixedHigh? It previously was SaGv_Enabled=3. -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Gerrit-Change-Number: 31120 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Jan 2019 17:16:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Use USB2 Port 10 for BT over CnVi
by Aamir Bohra (Code Review) 28 Jan '19

28 Jan '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30809 Change subject: mb/google/hatch: Use USB2 Port 10 for BT over CnVi ...................................................................... mb/google/hatch: Use USB2 Port 10 for BT over CnVi Integrated BT controller in CnVi uses USB port 10 for communication. BUG=b:122552619 TEST=lsusb shows BT device Change-Id: Iad1ca0e9419b534f50a3ce3fdcbd660caf8efb5c Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/30809/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index ca04507..8dd2d84 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -58,7 +58,7 @@ register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera register "usb2_ports[7]" = "USB2_PORT_EMPTY" register "usb2_ports[8]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad1ca0e9419b534f50a3ce3fdcbd660caf8efb5c Gerrit-Change-Number: 30809 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019