coreboot-gerrit January 2019

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Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Angel Pons (Code Review) 29 Jan '19

29 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/31133/1/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h: https://review.coreboot.org/#/c/31133/1/src/soc/intel/cannonlake/chip.h@40 PS1, Line 40: #define IS_CFL_OR_WHL(x, y) (IS_ENABLED(x) || IS_ENABLED(y)) IMHO, there's no need to pass parameters to this macro. It could be something like: #define IS_CFL_OR_WHL (IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE, CONFIG_SOC_INTEL_WHISKEYLAKE) || IS_ENABLED(y)) -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 13:24:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Angel Pons (Code Review) 29 Jan '19

29 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 3: w.r.t. SaGv being set to 3 on CNL-U and CNL-Y, this may be because the FixedMid option did not exist when the boards were added, so 3 was equal to Enabled. When said FixedMid option was added, 3 became FixedHigh on CNL chips. CB:31132 sets SaGv back to Enabled, as intended. -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Gerrit-Change-Number: 31120 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 13:15:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage
by Patrick Georgi (Code Review) 29 Jan '19

29 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30331 ) Change subject: google/kukui: Move some initialization from bootblock to verstage ...................................................................... google/kukui: Move some initialization from bootblock to verstage MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL moves some initialization steps from bootblock to verstage. This will save us about 2700 bytes (before compression) / 1024 bytes (after LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled, these initialization steps will be done in romstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> Reviewed-on: https://review.coreboot.org/c/30331 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/bootblock.c A src/mainboard/google/kukui/early_init.c A src/mainboard/google/kukui/early_init.h M src/mainboard/google/kukui/romstage.c M src/mainboard/google/kukui/verstage.c M src/soc/mediatek/mt8183/Makefile.inc 7 files changed, 72 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 9f8c313..a0556c1 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -2,18 +2,19 @@ bootblock-y += boardid.c bootblock-y += bootblock.c -bootblock-y += chromeos.c bootblock-y += memlayout.ld bootblock-y += reset.c decompressor-y += memlayout.ld verstage-y += chromeos.c +verstage-y += early_init.c verstage-y += reset.c verstage-y += verstage.c verstage-y += memlayout.ld romstage-y += boardid.c romstage-y += chromeos.c +romstage-y += early_init.c romstage-y += memlayout.ld romstage-y += reset.c romstage-y += romstage.c diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c index ab537d4..9d6c38b 100644 --- a/src/mainboard/google/kukui/bootblock.c +++ b/src/mainboard/google/kukui/bootblock.c @@ -14,28 +14,10 @@ */ #include <bootblock_common.h> -#include <gpio.h> -#include <soc/gpio.h> -#include <soc/mt8183.h> #include <soc/spi.h> -#include "gpio.h" - -#define BOOTBLOCK_EN_L (GPIO(KPROW0)) -#define AP_IN_SLEEP_L (GPIO(SRCLKENA0)) - void bootblock_mainboard_init(void) { - mt8183_early_init(); - - setup_chromeos_gpios(); - - /* Turn on real eMMC. */ - gpio_output(BOOTBLOCK_EN_L, 1); - - /* Declare we are in S0 */ - gpio_output(AP_IN_SLEEP_L, 1); - mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz); mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz); } diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c new file mode 100644 index 0000000..a16a335 --- /dev/null +++ b/src/mainboard/google/kukui/early_init.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <gpio.h> +#include <soc/mt8183.h> +#include <soc/spi.h> + +#include "early_init.h" +#include "gpio.h" + +#define BOOTBLOCK_EN_L (GPIO(KPROW0)) +#define AP_IN_SLEEP_L (GPIO(SRCLKENA0)) + +void mainboard_early_init(void) +{ + mt8183_early_init(); + + /* Turn on real eMMC and allow communication to EC. */ + gpio_output(BOOTBLOCK_EN_L, 1); + + setup_chromeos_gpios(); + + /* Declare we are in S0 */ + gpio_output(AP_IN_SLEEP_L, 1); + + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); + gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); +} diff --git a/src/mainboard/google/kukui/early_init.h b/src/mainboard/google/kukui/early_init.h new file mode 100644 index 0000000..a849fe8 --- /dev/null +++ b/src/mainboard/google/kukui/early_init.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GOOGLE_KUKUI_EARLY_INIT_H__ +#define __MAINBOARD_GOOGLE_KUKUI_EARLY_INIT_H__ + +void mainboard_early_init(void); + +#endif diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 629692d..7aad11f 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -18,8 +18,14 @@ #include <soc/mmu_operations.h> #include <soc/mt6358.h> +#include "early_init.h" + void platform_romstage_main(void) { + /* This will be done in verstage if CONFIG_VBOOT is enabled. */ + if (!IS_ENABLED(CONFIG_VBOOT)) + mainboard_early_init(); + mt6358_init(); mt_mem_init(get_sdram_config()); mtk_mmu_after_dram(); diff --git a/src/mainboard/google/kukui/verstage.c b/src/mainboard/google/kukui/verstage.c index 9bf93bf..c12d1b6 100644 --- a/src/mainboard/google/kukui/verstage.c +++ b/src/mainboard/google/kukui/verstage.c @@ -14,13 +14,10 @@ */ #include <security/vboot/vboot_common.h> -#include <soc/gpio.h> -#include <soc/spi.h> -#include "gpio.h" +#include "early_init.h" void verstage_mainboard_init(void) { - mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); - gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); + mainboard_early_init(); } diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index f24fdcc..5770a83 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -29,6 +29,7 @@ romstage-y += dramc_pi_calibration_api.c romstage-y += memory.c romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c +romstage-y += mt8183.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c -- To view, visit https://review.coreboot.org/c/coreboot/+/30331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Gerrit-Change-Number: 30331 Gerrit-PatchSet: 15 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

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Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage
by Patrick Georgi (Code Review) 29 Jan '19

29 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30331 ) Change subject: google/kukui: Move some initialization from bootblock to verstage ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Gerrit-Change-Number: 30331 Gerrit-PatchSet: 14 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 29 Jan 2019 13:10:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage
by You-Cheng Syu (Code Review) 29 Jan '19

29 Jan '19

You-Cheng Syu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30331 ) Change subject: google/kukui: Move some initialization from bootblock to verstage ...................................................................... Patch Set 14: (rebase for merge conflict) -- To view, visit https://review.coreboot.org/c/coreboot/+/30331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Gerrit-Change-Number: 30331 Gerrit-PatchSet: 14 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 29 Jan 2019 12:38:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage
by You-Cheng Syu (Code Review) 29 Jan '19

29 Jan '19

Hello Julius Werner, Paul Menzel, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Chun-ta Lin, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30331 to look at the new patch set (#14). Change subject: google/kukui: Move some initialization from bootblock to verstage ...................................................................... google/kukui: Move some initialization from bootblock to verstage MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL moves some initialization steps from bootblock to verstage. This will save us about 2700 bytes (before compression) / 1024 bytes (after LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled, these initialization steps will be done in romstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/bootblock.c A src/mainboard/google/kukui/early_init.c A src/mainboard/google/kukui/early_init.h M src/mainboard/google/kukui/romstage.c M src/mainboard/google/kukui/verstage.c M src/soc/mediatek/mt8183/Makefile.inc 7 files changed, 72 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30331/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/30331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Gerrit-Change-Number: 30331 Gerrit-PatchSet: 14 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/apollolake: Add GLK usb2eye configuration override
by Seunghwan Kim (Code Review) 29 Jan '19

29 Jan '19

Seunghwan Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31060 Change subject: soc/intel/apollolake: Add GLK usb2eye configuration override ...................................................................... soc/intel/apollolake: Add GLK usb2eye configuration override Now we have usb2eye configuration register in FSPUPD, so we would add an interface to override usb2eye setting. BRANCH=octopus BUG=NONE TEST=Verified usb2eye custom setting works Change-Id: I5c500964658072eaaf59364242aa928df25d99d1 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/include/soc/usb.h 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/31060/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 0d6d6d5..f120f47 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -548,6 +548,25 @@ struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) { #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) + uint8_t port; + + for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { + if (!cfg->usb2eye[port].Usb20OverrideEn) continue; + + silconfig->Usb2AfePehalfbit[port] = + cfg->usb2eye[port].Usb20PerPortTxPeHalf; + + silconfig->Usb2AfePetxiset[port] = + cfg->usb2eye[port].Usb20PerPortPeTxiSet; + + silconfig->Usb2AfeTxiset[port] = + cfg->usb2eye[port].Usb20PerPortTxiSet; + + silconfig->Usb2AfePredeemp[port] = + cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; + } + + silconfig->Gmm = 0; /* On Geminilake, we need to override the default FSP PCIe de-emphasis diff --git a/src/soc/intel/apollolake/include/soc/usb.h b/src/soc/intel/apollolake/include/soc/usb.h index 7dd9ec0..a2a2a63 100644 --- a/src/soc/intel/apollolake/include/soc/usb.h +++ b/src/soc/intel/apollolake/include/soc/usb.h @@ -30,6 +30,9 @@ uint8_t Usb20IUsbTxEmphasisEn; uint8_t Usb20PerPortRXISet; uint8_t Usb20HsNpreDrvSel; +#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) + uint8_t Usb20OverrideEn; +#endif }; #endif /* _SOC_APOLLOLAKE_USB_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c500964658072eaaf59364242aa928df25d99d1 Gerrit-Change-Number: 31060 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: Implement HW reset function
by Tristan Hsieh (Code Review) 29 Jan '19

29 Jan '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31118 Change subject: google/kukui: Implement HW reset function ...................................................................... google/kukui: Implement HW reset function Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW reset for SoC and H1. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot; emerge-kukui coreboot; manually verified the do_board_reset() on Kukui P1 Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/gpio.h A src/mainboard/google/kukui/reset.c M src/soc/mediatek/common/include/soc/wdt.h M src/soc/mediatek/common/wdt.c A src/soc/mediatek/common/wdt_reset.c M src/soc/mediatek/mt8173/Makefile.inc 7 files changed, 58 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/31118/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index acd2c45..9f8c313 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -4,15 +4,18 @@ bootblock-y += bootblock.c bootblock-y += chromeos.c bootblock-y += memlayout.ld +bootblock-y += reset.c decompressor-y += memlayout.ld verstage-y += chromeos.c +verstage-y += reset.c verstage-y += verstage.c verstage-y += memlayout.ld romstage-y += boardid.c romstage-y += chromeos.c romstage-y += memlayout.ld +romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c @@ -20,3 +23,4 @@ ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += memlayout.ld +ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/gpio.h b/src/mainboard/google/kukui/gpio.h index 20a50a6..024b0d7 100644 --- a/src/mainboard/google/kukui/gpio.h +++ b/src/mainboard/google/kukui/gpio.h @@ -21,6 +21,7 @@ #define EC_IRQ GPIO(PERIPHERAL_EN1) #define EC_IN_RW GPIO(PERIPHERAL_EN14) #define CR50_IRQ GPIO(PERIPHERAL_EN3) +#define GPIO_RESET GPIO(PERIPHERAL_EN8) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/kukui/reset.c b/src/mainboard/google/kukui/reset.c new file mode 100644 index 0000000..609ecb4 --- /dev/null +++ b/src/mainboard/google/kukui/reset.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <gpio.h> +#include <reset.h> + +#include "gpio.h" + +void do_board_reset(void) +{ + gpio_output(GPIO_RESET, 1); +} diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h index a15434c..b24be28 100644 --- a/src/soc/mediatek/common/include/soc/wdt.h +++ b/src/soc/mediatek/common/include/soc/wdt.h @@ -17,6 +17,7 @@ #define SOC_MEDIATEK_COMMON_WDT_H #include <stdint.h> +#include <soc/addressmap.h> struct mtk_wdt_regs { u32 wdt_mode; @@ -48,6 +49,8 @@ MTK_WDT_STA_HW_RST = 1 << 31 }; +static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE; + int mtk_wdt_init(void); #endif /* SOC_MEDIATEK_COMMON_WDT_H */ diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 9964c5a..b433c98 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -15,13 +15,9 @@ #include <arch/io.h> #include <console/console.h> -#include <reset.h> -#include <soc/addressmap.h> #include <soc/wdt.h> #include <vendorcode/google/chromeos/chromeos.h> -static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE; - int mtk_wdt_init(void) { uint32_t wdt_sta; @@ -56,8 +52,3 @@ return wdt_sta; } - -void do_board_reset(void) -{ - write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); -} diff --git a/src/soc/mediatek/common/wdt_reset.c b/src/soc/mediatek/common/wdt_reset.c new file mode 100644 index 0000000..855e34f --- /dev/null +++ b/src/soc/mediatek/common/wdt_reset.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <reset.h> +#include <soc/wdt.h> + +void do_board_reset(void) +{ + write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); +} diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index b004c27..91d3f8e 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -27,7 +27,7 @@ bootblock-y += ../common/gpio.c gpio.c gpio_init.c bootblock-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c -bootblock-y += ../common/wdt.c +bootblock-y += ../common/wdt.c ../common/wdt_reset.c bootblock-y += ../common/mmu_operations.c mmu_operations.c ################################################################################ @@ -39,7 +39,7 @@ verstage-y += ../common/timer.c verstage-y += timer.c -verstage-y += ../common/wdt.c +verstage-y += ../common/wdt.c ../common/wdt_reset.c verstage-$(CONFIG_SPI_FLASH) += flash_controller.c verstage-y += ../common/gpio.c gpio.c @@ -75,7 +75,7 @@ ramstage-y += mt6311.c ramstage-y += da9212.c ramstage-y += ../common/gpio.c gpio.c -ramstage-y += ../common/wdt.c +ramstage-y += ../common/wdt.c ../common/wdt_reset.c ramstage-y += ../common/pll.c pll.c ramstage-y += rtc.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a Gerrit-Change-Number: 31118 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

5 13

Change in ...coreboot[master]: mediatek: Seperate WDT reset function from WDT driver
by Tristan Hsieh (Code Review) 29 Jan '19

29 Jan '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31121 Change subject: mediatek: Seperate WDT reset function from WDT driver ...................................................................... mediatek: Seperate WDT reset function from WDT driver Seperate WDT reset function from WDT driver, then we can use the common WDT driver and have a board-specific reset funtion on different boards. In Kukui, we plan to use GPIO HW reset, instead of WDT reset. Add config "MISSING_BOARD_RESET" in Kukui to build pass for now. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot; emerge-kukui coreboot; Change-Id: Ica07fe3a027cd7e9eb6d10202c3ef3ed7bea00c2 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/Kconfig M src/soc/mediatek/common/include/soc/wdt.h A src/soc/mediatek/common/reset.c M src/soc/mediatek/common/wdt.c M src/soc/mediatek/mt8173/Makefile.inc 5 files changed, 30 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31121/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 7635e5f..902fa38 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -37,6 +37,7 @@ select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT + select MISSING_BOARD_RESET config MAINBOARD_DIR string diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h index a15434c..b24be28 100644 --- a/src/soc/mediatek/common/include/soc/wdt.h +++ b/src/soc/mediatek/common/include/soc/wdt.h @@ -17,6 +17,7 @@ #define SOC_MEDIATEK_COMMON_WDT_H #include <stdint.h> +#include <soc/addressmap.h> struct mtk_wdt_regs { u32 wdt_mode; @@ -48,6 +49,8 @@ MTK_WDT_STA_HW_RST = 1 << 31 }; +static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE; + int mtk_wdt_init(void); #endif /* SOC_MEDIATEK_COMMON_WDT_H */ diff --git a/src/soc/mediatek/common/reset.c b/src/soc/mediatek/common/reset.c new file mode 100644 index 0000000..855e34f --- /dev/null +++ b/src/soc/mediatek/common/reset.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <reset.h> +#include <soc/wdt.h> + +void do_board_reset(void) +{ + write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); +} diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 9964c5a..b433c98 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -15,13 +15,9 @@ #include <arch/io.h> #include <console/console.h> -#include <reset.h> -#include <soc/addressmap.h> #include <soc/wdt.h> #include <vendorcode/google/chromeos/chromeos.h> -static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE; - int mtk_wdt_init(void) { uint32_t wdt_sta; @@ -56,8 +52,3 @@ return wdt_sta; } - -void do_board_reset(void) -{ - write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); -} diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index b004c27..4ccc218 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -27,7 +27,7 @@ bootblock-y += ../common/gpio.c gpio.c gpio_init.c bootblock-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c -bootblock-y += ../common/wdt.c +bootblock-y += ../common/wdt.c ../common/reset.c bootblock-y += ../common/mmu_operations.c mmu_operations.c ################################################################################ @@ -39,7 +39,7 @@ verstage-y += ../common/timer.c verstage-y += timer.c -verstage-y += ../common/wdt.c +verstage-y += ../common/wdt.c ../common/reset.c verstage-$(CONFIG_SPI_FLASH) += flash_controller.c verstage-y += ../common/gpio.c gpio.c @@ -75,7 +75,7 @@ ramstage-y += mt6311.c ramstage-y += da9212.c ramstage-y += ../common/gpio.c gpio.c -ramstage-y += ../common/wdt.c +ramstage-y += ../common/wdt.c ../common/reset.c ramstage-y += ../common/pll.c pll.c ramstage-y += rtc.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica07fe3a027cd7e9eb6d10202c3ef3ed7bea00c2 Gerrit-Change-Number: 31121 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: cpu/intel/microcode: Enable verbose output
by Patrick Georgi (Code Review) 29 Jan '19

29 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29864 ) Change subject: cpu/intel/microcode: Enable verbose output ...................................................................... cpu/intel/microcode: Enable verbose output * Check if microcode is really updated. * Enable more verbose output. Change-Id: I534aa790c8d37b5f1603e1715635446835513a65 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/29864 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> --- M src/cpu/intel/microcode/microcode.c 1 file changed, 14 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index abaeeb6..44f7f1f 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -88,8 +88,12 @@ current_rev = read_microcode_rev(); /* No use loading the same revision. */ - if (current_rev == m->rev) + if (current_rev == m->rev) { +#if !defined(__ROMCC__) + printk(BIOS_INFO, "microcode: Update skipped, already up-to-date\n"); +#endif return; + } #if ENV_RAMSTAGE /*SoC specific check to update microcode*/ @@ -103,12 +107,20 @@ msr.hi = 0; wrmsr(IA32_BIOS_UPDT_TRIG, msr); + current_rev = read_microcode_rev(); + if (current_rev == m->rev) { #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "microcode: updated to revision " + printk(BIOS_INFO, "microcode: updated to revision " "0x%x date=%04x-%02x-%02x\n", read_microcode_rev(), m->date & 0xffff, (m->date >> 24) & 0xff, (m->date >> 16) & 0xff); #endif + return; + } + +#if !defined(__ROMCC__) + printk(BIOS_INFO, "microcode: Update failed\n"); +#endif } uint32_t get_current_microcode_rev(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/29864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534aa790c8d37b5f1603e1715635446835513a65 Gerrit-Change-Number: 29864 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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